1f9900dd0SZhengjun Xing[ 2f9900dd0SZhengjun Xing { 35fa2481cSZhengjun Xing "BriefDescription": "ARITH.FPDIV_ACTIVE", 4f9900dd0SZhengjun Xing "CounterMask": "1", 5f9900dd0SZhengjun Xing "EventCode": "0xb0", 6f9900dd0SZhengjun Xing "EventName": "ARITH.FPDIV_ACTIVE", 7f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 8f9900dd0SZhengjun Xing "UMask": "0x1", 9f9900dd0SZhengjun Xing "Unit": "cpu_core" 10f9900dd0SZhengjun Xing }, 11f9900dd0SZhengjun Xing { 12f9900dd0SZhengjun Xing "BriefDescription": "Counts all microcode FP assists.", 13f9900dd0SZhengjun Xing "EventCode": "0xc1", 14f9900dd0SZhengjun Xing "EventName": "ASSISTS.FP", 15*4c12f41aSZhengjun Xing "PublicDescription": "Counts all microcode Floating Point assists.", 16f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 17f9900dd0SZhengjun Xing "UMask": "0x2", 18f9900dd0SZhengjun Xing "Unit": "cpu_core" 19f9900dd0SZhengjun Xing }, 20f9900dd0SZhengjun Xing { 215fa2481cSZhengjun Xing "BriefDescription": "ASSISTS.SSE_AVX_MIX", 22f9900dd0SZhengjun Xing "EventCode": "0xc1", 23f9900dd0SZhengjun Xing "EventName": "ASSISTS.SSE_AVX_MIX", 24f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 25f9900dd0SZhengjun Xing "UMask": "0x10", 26f9900dd0SZhengjun Xing "Unit": "cpu_core" 27f9900dd0SZhengjun Xing }, 28f9900dd0SZhengjun Xing { 295fa2481cSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 30f9900dd0SZhengjun Xing "EventCode": "0xb3", 31f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_0", 32f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 33f9900dd0SZhengjun Xing "UMask": "0x1", 34f9900dd0SZhengjun Xing "Unit": "cpu_core" 35f9900dd0SZhengjun Xing }, 36f9900dd0SZhengjun Xing { 375fa2481cSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 38f9900dd0SZhengjun Xing "EventCode": "0xb3", 39f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_1", 40f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 41f9900dd0SZhengjun Xing "UMask": "0x2", 42f9900dd0SZhengjun Xing "Unit": "cpu_core" 43f9900dd0SZhengjun Xing }, 44f9900dd0SZhengjun Xing { 455fa2481cSZhengjun Xing "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 46f9900dd0SZhengjun Xing "EventCode": "0xb3", 47f9900dd0SZhengjun Xing "EventName": "FP_ARITH_DISPATCHED.PORT_5", 48f9900dd0SZhengjun Xing "SampleAfterValue": "2000003", 49f9900dd0SZhengjun Xing "UMask": "0x4", 50f9900dd0SZhengjun Xing "Unit": "cpu_core" 51f9900dd0SZhengjun Xing }, 52f9900dd0SZhengjun Xing { 53f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 54f9900dd0SZhengjun Xing "EventCode": "0xc7", 55f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 56*4c12f41aSZhengjun Xing "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 57f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 58f9900dd0SZhengjun Xing "UMask": "0x4", 59f9900dd0SZhengjun Xing "Unit": "cpu_core" 60f9900dd0SZhengjun Xing }, 61f9900dd0SZhengjun Xing { 62f9900dd0SZhengjun Xing "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 63f9900dd0SZhengjun Xing "EventCode": "0xc7", 64f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 65*4c12f41aSZhengjun Xing "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 66f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 67f9900dd0SZhengjun Xing "UMask": "0x8", 68f9900dd0SZhengjun Xing "Unit": "cpu_core" 69f9900dd0SZhengjun Xing }, 70f9900dd0SZhengjun Xing { 71f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 72f9900dd0SZhengjun Xing "EventCode": "0xc7", 73f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 74*4c12f41aSZhengjun Xing "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 75f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 76f9900dd0SZhengjun Xing "UMask": "0x10", 77f9900dd0SZhengjun Xing "Unit": "cpu_core" 78f9900dd0SZhengjun Xing }, 79f9900dd0SZhengjun Xing { 80f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 81f9900dd0SZhengjun Xing "EventCode": "0xc7", 82f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 83*4c12f41aSZhengjun Xing "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 84f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 85f9900dd0SZhengjun Xing "UMask": "0x20", 86f9900dd0SZhengjun Xing "Unit": "cpu_core" 87f9900dd0SZhengjun Xing }, 88f9900dd0SZhengjun Xing { 89f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 90f9900dd0SZhengjun Xing "EventCode": "0xc7", 91f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 92*4c12f41aSZhengjun Xing "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 93f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 94f9900dd0SZhengjun Xing "UMask": "0x1", 95f9900dd0SZhengjun Xing "Unit": "cpu_core" 96f9900dd0SZhengjun Xing }, 97f9900dd0SZhengjun Xing { 98f9900dd0SZhengjun Xing "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 99f9900dd0SZhengjun Xing "EventCode": "0xc7", 100f9900dd0SZhengjun Xing "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 101*4c12f41aSZhengjun Xing "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 102f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 103f9900dd0SZhengjun Xing "UMask": "0x2", 104f9900dd0SZhengjun Xing "Unit": "cpu_core" 105*4c12f41aSZhengjun Xing }, 106*4c12f41aSZhengjun Xing { 107*4c12f41aSZhengjun Xing "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 108*4c12f41aSZhengjun Xing "EventCode": "0xc3", 109*4c12f41aSZhengjun Xing "EventName": "MACHINE_CLEARS.FP_ASSIST", 110*4c12f41aSZhengjun Xing "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 111*4c12f41aSZhengjun Xing "SampleAfterValue": "20003", 112*4c12f41aSZhengjun Xing "UMask": "0x4", 113*4c12f41aSZhengjun Xing "Unit": "cpu_atom" 114*4c12f41aSZhengjun Xing }, 115*4c12f41aSZhengjun Xing { 116*4c12f41aSZhengjun Xing "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", 117*4c12f41aSZhengjun Xing "EventCode": "0xc2", 118*4c12f41aSZhengjun Xing "EventName": "UOPS_RETIRED.FPDIV", 119*4c12f41aSZhengjun Xing "PEBS": "1", 120*4c12f41aSZhengjun Xing "SampleAfterValue": "2000003", 121*4c12f41aSZhengjun Xing "UMask": "0x8", 122*4c12f41aSZhengjun Xing "Unit": "cpu_atom" 123f9900dd0SZhengjun Xing } 124f9900dd0SZhengjun Xing] 125