1[ 2 { 3 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5", 6 "EventCode": "0x2e", 7 "EventName": "LONGEST_LAT_CACHE.MISS", 8 "PEBScounters": "0,1,2,3,4,5", 9 "SampleAfterValue": "200003", 10 "Speculative": "1", 11 "UMask": "0x41", 12 "Unit": "cpu_atom" 13 }, 14 { 15 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3,4,5", 18 "EventCode": "0x2e", 19 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 20 "PEBScounters": "0,1,2,3,4,5", 21 "SampleAfterValue": "200003", 22 "Speculative": "1", 23 "UMask": "0x4f", 24 "Unit": "cpu_atom" 25 }, 26 { 27 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3,4,5", 30 "EventCode": "0x34", 31 "EventName": "MEM_BOUND_STALLS.IFETCH", 32 "PEBScounters": "0,1,2,3,4,5", 33 "SampleAfterValue": "200003", 34 "Speculative": "1", 35 "UMask": "0x38", 36 "Unit": "cpu_atom" 37 }, 38 { 39 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 40 "CollectPEBSRecord": "2", 41 "Counter": "0,1,2,3,4,5", 42 "EventCode": "0x34", 43 "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", 44 "PEBScounters": "0,1,2,3,4,5", 45 "SampleAfterValue": "200003", 46 "Speculative": "1", 47 "UMask": "0x20", 48 "Unit": "cpu_atom" 49 }, 50 { 51 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 52 "CollectPEBSRecord": "2", 53 "Counter": "0,1,2,3,4,5", 54 "EventCode": "0x34", 55 "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", 56 "PEBScounters": "0,1,2,3,4,5", 57 "SampleAfterValue": "200003", 58 "Speculative": "1", 59 "UMask": "0x8", 60 "Unit": "cpu_atom" 61 }, 62 { 63 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", 64 "CollectPEBSRecord": "2", 65 "Counter": "0,1,2,3,4,5", 66 "EventCode": "0x34", 67 "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", 68 "PEBScounters": "0,1,2,3,4,5", 69 "SampleAfterValue": "200003", 70 "Speculative": "1", 71 "UMask": "0x10", 72 "Unit": "cpu_atom" 73 }, 74 { 75 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 76 "CollectPEBSRecord": "2", 77 "Counter": "0,1,2,3,4,5", 78 "EventCode": "0x34", 79 "EventName": "MEM_BOUND_STALLS.LOAD", 80 "PEBScounters": "0,1,2,3,4,5", 81 "SampleAfterValue": "200003", 82 "Speculative": "1", 83 "UMask": "0x7", 84 "Unit": "cpu_atom" 85 }, 86 { 87 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 88 "CollectPEBSRecord": "2", 89 "Counter": "0,1,2,3,4,5", 90 "EventCode": "0x34", 91 "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", 92 "PEBScounters": "0,1,2,3,4,5", 93 "SampleAfterValue": "200003", 94 "Speculative": "1", 95 "UMask": "0x4", 96 "Unit": "cpu_atom" 97 }, 98 { 99 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 100 "CollectPEBSRecord": "2", 101 "Counter": "0,1,2,3,4,5", 102 "EventCode": "0x34", 103 "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", 104 "PEBScounters": "0,1,2,3,4,5", 105 "SampleAfterValue": "200003", 106 "Speculative": "1", 107 "UMask": "0x1", 108 "Unit": "cpu_atom" 109 }, 110 { 111 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", 112 "CollectPEBSRecord": "2", 113 "Counter": "0,1,2,3,4,5", 114 "EventCode": "0x34", 115 "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", 116 "PEBScounters": "0,1,2,3,4,5", 117 "SampleAfterValue": "200003", 118 "Speculative": "1", 119 "UMask": "0x2", 120 "Unit": "cpu_atom" 121 }, 122 { 123 "BriefDescription": "Counts the number of load uops retired that hit in DRAM.", 124 "CollectPEBSRecord": "2", 125 "Counter": "0,1,2,3,4,5", 126 "Data_LA": "1", 127 "EventCode": "0xd1", 128 "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 129 "PEBS": "1", 130 "PEBScounters": "0,1,2,3,4,5", 131 "SampleAfterValue": "200003", 132 "UMask": "0x80", 133 "Unit": "cpu_atom" 134 }, 135 { 136 "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", 137 "CollectPEBSRecord": "2", 138 "Counter": "0,1,2,3,4,5", 139 "Data_LA": "1", 140 "EventCode": "0xd1", 141 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 142 "PEBS": "1", 143 "PEBScounters": "0,1,2,3,4,5", 144 "SampleAfterValue": "200003", 145 "UMask": "0x2", 146 "Unit": "cpu_atom" 147 }, 148 { 149 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 150 "CollectPEBSRecord": "2", 151 "Counter": "0,1,2,3,4,5", 152 "Data_LA": "1", 153 "EventCode": "0xd1", 154 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 155 "PEBS": "1", 156 "PEBScounters": "0,1,2,3,4,5", 157 "SampleAfterValue": "200003", 158 "UMask": "0x4", 159 "Unit": "cpu_atom" 160 }, 161 { 162 "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", 163 "CollectPEBSRecord": "2", 164 "Counter": "0,1,2,3,4,5", 165 "EventCode": "0x04", 166 "EventName": "MEM_SCHEDULER_BLOCK.ALL", 167 "PEBScounters": "0,1,2,3,4,5", 168 "SampleAfterValue": "20003", 169 "Speculative": "1", 170 "UMask": "0x7", 171 "Unit": "cpu_atom" 172 }, 173 { 174 "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", 175 "CollectPEBSRecord": "2", 176 "Counter": "0,1,2,3,4,5", 177 "EventCode": "0x04", 178 "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", 179 "PEBScounters": "0,1,2,3,4,5", 180 "SampleAfterValue": "20003", 181 "Speculative": "1", 182 "UMask": "0x2", 183 "Unit": "cpu_atom" 184 }, 185 { 186 "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", 187 "CollectPEBSRecord": "2", 188 "Counter": "0,1,2,3,4,5", 189 "EventCode": "0x04", 190 "EventName": "MEM_SCHEDULER_BLOCK.RSV", 191 "PEBScounters": "0,1,2,3,4,5", 192 "SampleAfterValue": "20003", 193 "Speculative": "1", 194 "UMask": "0x4", 195 "Unit": "cpu_atom" 196 }, 197 { 198 "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", 199 "CollectPEBSRecord": "2", 200 "Counter": "0,1,2,3,4,5", 201 "EventCode": "0x04", 202 "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", 203 "PEBScounters": "0,1,2,3,4,5", 204 "SampleAfterValue": "20003", 205 "Speculative": "1", 206 "UMask": "0x1", 207 "Unit": "cpu_atom" 208 }, 209 { 210 "BriefDescription": "Counts the number of load uops retired.", 211 "CollectPEBSRecord": "2", 212 "Counter": "0,1,2,3,4,5", 213 "Data_LA": "1", 214 "EventCode": "0xd0", 215 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 216 "PEBS": "1", 217 "PEBScounters": "0,1,2,3,4,5", 218 "SampleAfterValue": "200003", 219 "UMask": "0x81", 220 "Unit": "cpu_atom" 221 }, 222 { 223 "BriefDescription": "Counts the number of store uops retired.", 224 "CollectPEBSRecord": "2", 225 "Counter": "0,1,2,3,4,5", 226 "Data_LA": "1", 227 "EventCode": "0xd0", 228 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 229 "PEBS": "1", 230 "PEBScounters": "0,1,2,3,4,5", 231 "SampleAfterValue": "200003", 232 "UMask": "0x82", 233 "Unit": "cpu_atom" 234 }, 235 { 236 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 237 "CollectPEBSRecord": "2", 238 "Counter": "0,1", 239 "Data_LA": "1", 240 "EventCode": "0xd0", 241 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 242 "L1_Hit_Indication": "1", 243 "MSRIndex": "0x3F6", 244 "MSRValue": "0x80", 245 "PEBS": "2", 246 "PEBScounters": "0,1", 247 "SampleAfterValue": "1000003", 248 "TakenAlone": "1", 249 "UMask": "0x5", 250 "Unit": "cpu_atom" 251 }, 252 { 253 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 254 "CollectPEBSRecord": "2", 255 "Counter": "0,1", 256 "Data_LA": "1", 257 "EventCode": "0xd0", 258 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 259 "L1_Hit_Indication": "1", 260 "MSRIndex": "0x3F6", 261 "MSRValue": "0x10", 262 "PEBS": "2", 263 "PEBScounters": "0,1", 264 "SampleAfterValue": "1000003", 265 "TakenAlone": "1", 266 "UMask": "0x5", 267 "Unit": "cpu_atom" 268 }, 269 { 270 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 271 "CollectPEBSRecord": "2", 272 "Counter": "0,1", 273 "Data_LA": "1", 274 "EventCode": "0xd0", 275 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", 276 "L1_Hit_Indication": "1", 277 "MSRIndex": "0x3F6", 278 "MSRValue": "0x100", 279 "PEBS": "2", 280 "PEBScounters": "0,1", 281 "SampleAfterValue": "1000003", 282 "TakenAlone": "1", 283 "UMask": "0x5", 284 "Unit": "cpu_atom" 285 }, 286 { 287 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 288 "CollectPEBSRecord": "2", 289 "Counter": "0,1", 290 "Data_LA": "1", 291 "EventCode": "0xd0", 292 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", 293 "L1_Hit_Indication": "1", 294 "MSRIndex": "0x3F6", 295 "MSRValue": "0x20", 296 "PEBS": "2", 297 "PEBScounters": "0,1", 298 "SampleAfterValue": "1000003", 299 "TakenAlone": "1", 300 "UMask": "0x5", 301 "Unit": "cpu_atom" 302 }, 303 { 304 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 305 "CollectPEBSRecord": "2", 306 "Counter": "0,1", 307 "Data_LA": "1", 308 "EventCode": "0xd0", 309 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", 310 "L1_Hit_Indication": "1", 311 "MSRIndex": "0x3F6", 312 "MSRValue": "0x4", 313 "PEBS": "2", 314 "PEBScounters": "0,1", 315 "SampleAfterValue": "1000003", 316 "TakenAlone": "1", 317 "UMask": "0x5", 318 "Unit": "cpu_atom" 319 }, 320 { 321 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 322 "CollectPEBSRecord": "2", 323 "Counter": "0,1", 324 "Data_LA": "1", 325 "EventCode": "0xd0", 326 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", 327 "L1_Hit_Indication": "1", 328 "MSRIndex": "0x3F6", 329 "MSRValue": "0x200", 330 "PEBS": "2", 331 "PEBScounters": "0,1", 332 "SampleAfterValue": "1000003", 333 "TakenAlone": "1", 334 "UMask": "0x5", 335 "Unit": "cpu_atom" 336 }, 337 { 338 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 339 "CollectPEBSRecord": "2", 340 "Counter": "0,1", 341 "Data_LA": "1", 342 "EventCode": "0xd0", 343 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", 344 "L1_Hit_Indication": "1", 345 "MSRIndex": "0x3F6", 346 "MSRValue": "0x40", 347 "PEBS": "2", 348 "PEBScounters": "0,1", 349 "SampleAfterValue": "1000003", 350 "TakenAlone": "1", 351 "UMask": "0x5", 352 "Unit": "cpu_atom" 353 }, 354 { 355 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 356 "CollectPEBSRecord": "2", 357 "Counter": "0,1", 358 "Data_LA": "1", 359 "EventCode": "0xd0", 360 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", 361 "L1_Hit_Indication": "1", 362 "MSRIndex": "0x3F6", 363 "MSRValue": "0x8", 364 "PEBS": "2", 365 "PEBScounters": "0,1", 366 "SampleAfterValue": "1000003", 367 "TakenAlone": "1", 368 "UMask": "0x5", 369 "Unit": "cpu_atom" 370 }, 371 { 372 "BriefDescription": "Counts the number of retired split load uops.", 373 "CollectPEBSRecord": "2", 374 "Counter": "0,1,2,3,4,5", 375 "Data_LA": "1", 376 "EventCode": "0xd0", 377 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 378 "PEBS": "1", 379 "PEBScounters": "0,1,2,3,4,5", 380 "SampleAfterValue": "200003", 381 "UMask": "0x41", 382 "Unit": "cpu_atom" 383 }, 384 { 385 "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", 386 "CollectPEBSRecord": "2", 387 "Counter": "0,1,2,3,4,5", 388 "Data_LA": "1", 389 "EventCode": "0xd0", 390 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", 391 "L1_Hit_Indication": "1", 392 "PEBS": "2", 393 "PEBScounters": "0,1,2,3,4,5", 394 "SampleAfterValue": "1000003", 395 "UMask": "0x6", 396 "Unit": "cpu_atom" 397 }, 398 { 399 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.", 400 "Counter": "0,1,2,3,4,5", 401 "EventCode": "0xB7", 402 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x3F803C0001", 405 "SampleAfterValue": "100003", 406 "UMask": "0x1", 407 "Unit": "cpu_atom" 408 }, 409 { 410 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 411 "Counter": "0,1,2,3,4,5", 412 "EventCode": "0xB7", 413 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 414 "MSRIndex": "0x1a6,0x1a7", 415 "MSRValue": "0x10003C0001", 416 "SampleAfterValue": "100003", 417 "UMask": "0x1", 418 "Unit": "cpu_atom" 419 }, 420 { 421 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 422 "Counter": "0,1,2,3,4,5", 423 "EventCode": "0xB7", 424 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", 425 "MSRIndex": "0x1a6,0x1a7", 426 "MSRValue": "0x4003C0001", 427 "SampleAfterValue": "100003", 428 "UMask": "0x1", 429 "Unit": "cpu_atom" 430 }, 431 { 432 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 433 "Counter": "0,1,2,3,4,5", 434 "EventCode": "0xB7", 435 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 436 "MSRIndex": "0x1a6,0x1a7", 437 "MSRValue": "0x8003C0001", 438 "SampleAfterValue": "100003", 439 "UMask": "0x1", 440 "Unit": "cpu_atom" 441 }, 442 { 443 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", 444 "Counter": "0,1,2,3,4,5", 445 "EventCode": "0xB7", 446 "EventName": "OCR.DEMAND_RFO.L3_HIT", 447 "MSRIndex": "0x1a6,0x1a7", 448 "MSRValue": "0x3F803C0002", 449 "SampleAfterValue": "100003", 450 "UMask": "0x1", 451 "Unit": "cpu_atom" 452 }, 453 { 454 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 455 "Counter": "0,1,2,3,4,5", 456 "EventCode": "0xB7", 457 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 458 "MSRIndex": "0x1a6,0x1a7", 459 "MSRValue": "0x10003C0002", 460 "SampleAfterValue": "100003", 461 "UMask": "0x1", 462 "Unit": "cpu_atom" 463 }, 464 { 465 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", 466 "CollectPEBSRecord": "2", 467 "Counter": "0,1,2,3,4,5", 468 "EventCode": "0x71", 469 "EventName": "TOPDOWN_FE_BOUND.ICACHE", 470 "PEBScounters": "0,1,2,3,4,5", 471 "SampleAfterValue": "1000003", 472 "Speculative": "1", 473 "UMask": "0x20", 474 "Unit": "cpu_atom" 475 }, 476 { 477 "BriefDescription": "L1D.HWPF_MISS", 478 "CollectPEBSRecord": "2", 479 "Counter": "0,1,2,3", 480 "EventCode": "0x51", 481 "EventName": "L1D.HWPF_MISS", 482 "PEBScounters": "0,1,2,3", 483 "SampleAfterValue": "1000003", 484 "Speculative": "1", 485 "UMask": "0x20", 486 "Unit": "cpu_core" 487 }, 488 { 489 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 490 "CollectPEBSRecord": "2", 491 "Counter": "0,1,2,3", 492 "EventCode": "0x51", 493 "EventName": "L1D.REPLACEMENT", 494 "PEBScounters": "0,1,2,3", 495 "SampleAfterValue": "100003", 496 "Speculative": "1", 497 "UMask": "0x1", 498 "Unit": "cpu_core" 499 }, 500 { 501 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 502 "CollectPEBSRecord": "2", 503 "Counter": "0,1,2,3", 504 "EventCode": "0x48", 505 "EventName": "L1D_PEND_MISS.FB_FULL", 506 "PEBScounters": "0,1,2,3", 507 "SampleAfterValue": "1000003", 508 "Speculative": "1", 509 "UMask": "0x2", 510 "Unit": "cpu_core" 511 }, 512 { 513 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", 514 "CollectPEBSRecord": "2", 515 "Counter": "0,1,2,3", 516 "CounterMask": "1", 517 "EdgeDetect": "1", 518 "EventCode": "0x48", 519 "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", 520 "PEBScounters": "0,1,2,3", 521 "SampleAfterValue": "1000003", 522 "Speculative": "1", 523 "UMask": "0x2", 524 "Unit": "cpu_core" 525 }, 526 { 527 "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", 528 "CollectPEBSRecord": "2", 529 "Counter": "0,1,2,3", 530 "EventCode": "0x48", 531 "EventName": "L1D_PEND_MISS.L2_STALL", 532 "PEBScounters": "0,1,2,3", 533 "SampleAfterValue": "1000003", 534 "Speculative": "1", 535 "UMask": "0x4", 536 "Unit": "cpu_core" 537 }, 538 { 539 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 540 "CollectPEBSRecord": "2", 541 "Counter": "0,1,2,3", 542 "EventCode": "0x48", 543 "EventName": "L1D_PEND_MISS.L2_STALLS", 544 "PEBScounters": "0,1,2,3", 545 "SampleAfterValue": "1000003", 546 "Speculative": "1", 547 "UMask": "0x4", 548 "Unit": "cpu_core" 549 }, 550 { 551 "BriefDescription": "Number of L1D misses that are outstanding", 552 "CollectPEBSRecord": "2", 553 "Counter": "0,1,2,3", 554 "EventCode": "0x48", 555 "EventName": "L1D_PEND_MISS.PENDING", 556 "PEBScounters": "0,1,2,3", 557 "SampleAfterValue": "1000003", 558 "Speculative": "1", 559 "UMask": "0x1", 560 "Unit": "cpu_core" 561 }, 562 { 563 "BriefDescription": "Cycles with L1D load Misses outstanding.", 564 "CollectPEBSRecord": "2", 565 "Counter": "0,1,2,3", 566 "CounterMask": "1", 567 "EventCode": "0x48", 568 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 569 "PEBScounters": "0,1,2,3", 570 "SampleAfterValue": "1000003", 571 "Speculative": "1", 572 "UMask": "0x1", 573 "Unit": "cpu_core" 574 }, 575 { 576 "BriefDescription": "L2 cache lines filling L2", 577 "CollectPEBSRecord": "2", 578 "Counter": "0,1,2,3", 579 "EventCode": "0x25", 580 "EventName": "L2_LINES_IN.ALL", 581 "PEBScounters": "0,1,2,3", 582 "SampleAfterValue": "100003", 583 "Speculative": "1", 584 "UMask": "0x1f", 585 "Unit": "cpu_core" 586 }, 587 { 588 "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 589 "CollectPEBSRecord": "2", 590 "Counter": "0,1,2,3", 591 "EventCode": "0x26", 592 "EventName": "L2_LINES_OUT.USELESS_HWPF", 593 "PEBScounters": "0,1,2,3", 594 "SampleAfterValue": "200003", 595 "Speculative": "1", 596 "UMask": "0x4", 597 "Unit": "cpu_core" 598 }, 599 { 600 "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]", 601 "CollectPEBSRecord": "2", 602 "Counter": "0,1,2,3", 603 "EventCode": "0x24", 604 "EventName": "L2_REQUEST.ALL", 605 "PEBScounters": "0,1,2,3", 606 "SampleAfterValue": "200003", 607 "Speculative": "1", 608 "UMask": "0xff", 609 "Unit": "cpu_core" 610 }, 611 { 612 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", 613 "CollectPEBSRecord": "2", 614 "Counter": "0,1,2,3", 615 "EventCode": "0x24", 616 "EventName": "L2_REQUEST.MISS", 617 "PEBScounters": "0,1,2,3", 618 "SampleAfterValue": "200003", 619 "Speculative": "1", 620 "UMask": "0x3f", 621 "Unit": "cpu_core" 622 }, 623 { 624 "BriefDescription": "L2 code requests", 625 "CollectPEBSRecord": "2", 626 "Counter": "0,1,2,3", 627 "EventCode": "0x24", 628 "EventName": "L2_RQSTS.ALL_CODE_RD", 629 "PEBScounters": "0,1,2,3", 630 "SampleAfterValue": "200003", 631 "Speculative": "1", 632 "UMask": "0xe4", 633 "Unit": "cpu_core" 634 }, 635 { 636 "BriefDescription": "Demand Data Read access L2 cache", 637 "CollectPEBSRecord": "2", 638 "Counter": "0,1,2,3", 639 "EventCode": "0x24", 640 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 641 "PEBScounters": "0,1,2,3", 642 "SampleAfterValue": "200003", 643 "Speculative": "1", 644 "UMask": "0xe1", 645 "Unit": "cpu_core" 646 }, 647 { 648 "BriefDescription": "Demand requests that miss L2 cache", 649 "CollectPEBSRecord": "2", 650 "Counter": "0,1,2,3", 651 "EventCode": "0x24", 652 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 653 "PEBScounters": "0,1,2,3", 654 "SampleAfterValue": "200003", 655 "Speculative": "1", 656 "UMask": "0x27", 657 "Unit": "cpu_core" 658 }, 659 { 660 "BriefDescription": "L2_RQSTS.ALL_HWPF", 661 "CollectPEBSRecord": "2", 662 "Counter": "0,1,2,3", 663 "EventCode": "0x24", 664 "EventName": "L2_RQSTS.ALL_HWPF", 665 "PEBScounters": "0,1,2,3", 666 "SampleAfterValue": "200003", 667 "Speculative": "1", 668 "UMask": "0xf0", 669 "Unit": "cpu_core" 670 }, 671 { 672 "BriefDescription": "RFO requests to L2 cache.", 673 "CollectPEBSRecord": "2", 674 "Counter": "0,1,2,3", 675 "EventCode": "0x24", 676 "EventName": "L2_RQSTS.ALL_RFO", 677 "PEBScounters": "0,1,2,3", 678 "SampleAfterValue": "200003", 679 "Speculative": "1", 680 "UMask": "0xe2", 681 "Unit": "cpu_core" 682 }, 683 { 684 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 685 "CollectPEBSRecord": "2", 686 "Counter": "0,1,2,3", 687 "EventCode": "0x24", 688 "EventName": "L2_RQSTS.CODE_RD_HIT", 689 "PEBScounters": "0,1,2,3", 690 "SampleAfterValue": "200003", 691 "Speculative": "1", 692 "UMask": "0xc4", 693 "Unit": "cpu_core" 694 }, 695 { 696 "BriefDescription": "L2 cache misses when fetching instructions", 697 "CollectPEBSRecord": "2", 698 "Counter": "0,1,2,3", 699 "EventCode": "0x24", 700 "EventName": "L2_RQSTS.CODE_RD_MISS", 701 "PEBScounters": "0,1,2,3", 702 "SampleAfterValue": "200003", 703 "Speculative": "1", 704 "UMask": "0x24", 705 "Unit": "cpu_core" 706 }, 707 { 708 "BriefDescription": "Demand Data Read requests that hit L2 cache", 709 "CollectPEBSRecord": "2", 710 "Counter": "0,1,2,3", 711 "EventCode": "0x24", 712 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 713 "PEBScounters": "0,1,2,3", 714 "SampleAfterValue": "200003", 715 "Speculative": "1", 716 "UMask": "0xc1", 717 "Unit": "cpu_core" 718 }, 719 { 720 "BriefDescription": "Demand Data Read miss L2 cache", 721 "CollectPEBSRecord": "2", 722 "Counter": "0,1,2,3", 723 "EventCode": "0x24", 724 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 725 "PEBScounters": "0,1,2,3", 726 "SampleAfterValue": "200003", 727 "Speculative": "1", 728 "UMask": "0x21", 729 "Unit": "cpu_core" 730 }, 731 { 732 "BriefDescription": "L2_RQSTS.HWPF_MISS", 733 "CollectPEBSRecord": "2", 734 "Counter": "0,1,2,3", 735 "EventCode": "0x24", 736 "EventName": "L2_RQSTS.HWPF_MISS", 737 "PEBScounters": "0,1,2,3", 738 "SampleAfterValue": "200003", 739 "Speculative": "1", 740 "UMask": "0x30", 741 "Unit": "cpu_core" 742 }, 743 { 744 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", 745 "CollectPEBSRecord": "2", 746 "Counter": "0,1,2,3", 747 "EventCode": "0x24", 748 "EventName": "L2_RQSTS.MISS", 749 "PEBScounters": "0,1,2,3", 750 "SampleAfterValue": "200003", 751 "Speculative": "1", 752 "UMask": "0x3f", 753 "Unit": "cpu_core" 754 }, 755 { 756 "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]", 757 "CollectPEBSRecord": "2", 758 "Counter": "0,1,2,3", 759 "EventCode": "0x24", 760 "EventName": "L2_RQSTS.REFERENCES", 761 "PEBScounters": "0,1,2,3", 762 "SampleAfterValue": "200003", 763 "Speculative": "1", 764 "UMask": "0xff", 765 "Unit": "cpu_core" 766 }, 767 { 768 "BriefDescription": "RFO requests that hit L2 cache.", 769 "CollectPEBSRecord": "2", 770 "Counter": "0,1,2,3", 771 "EventCode": "0x24", 772 "EventName": "L2_RQSTS.RFO_HIT", 773 "PEBScounters": "0,1,2,3", 774 "SampleAfterValue": "200003", 775 "Speculative": "1", 776 "UMask": "0xc2", 777 "Unit": "cpu_core" 778 }, 779 { 780 "BriefDescription": "RFO requests that miss L2 cache", 781 "CollectPEBSRecord": "2", 782 "Counter": "0,1,2,3", 783 "EventCode": "0x24", 784 "EventName": "L2_RQSTS.RFO_MISS", 785 "PEBScounters": "0,1,2,3", 786 "SampleAfterValue": "200003", 787 "Speculative": "1", 788 "UMask": "0x22", 789 "Unit": "cpu_core" 790 }, 791 { 792 "BriefDescription": "SW prefetch requests that hit L2 cache.", 793 "CollectPEBSRecord": "2", 794 "Counter": "0,1,2,3", 795 "EventCode": "0x24", 796 "EventName": "L2_RQSTS.SWPF_HIT", 797 "PEBScounters": "0,1,2,3", 798 "SampleAfterValue": "200003", 799 "Speculative": "1", 800 "UMask": "0xc8", 801 "Unit": "cpu_core" 802 }, 803 { 804 "BriefDescription": "SW prefetch requests that miss L2 cache.", 805 "CollectPEBSRecord": "2", 806 "Counter": "0,1,2,3", 807 "EventCode": "0x24", 808 "EventName": "L2_RQSTS.SWPF_MISS", 809 "PEBScounters": "0,1,2,3", 810 "SampleAfterValue": "200003", 811 "Speculative": "1", 812 "UMask": "0x28", 813 "Unit": "cpu_core" 814 }, 815 { 816 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 817 "CollectPEBSRecord": "2", 818 "Counter": "0,1,2,3,4,5,6,7", 819 "EventCode": "0x2e", 820 "EventName": "LONGEST_LAT_CACHE.MISS", 821 "PEBScounters": "0,1,2,3,4,5,6,7", 822 "SampleAfterValue": "100003", 823 "Speculative": "1", 824 "UMask": "0x41", 825 "Unit": "cpu_core" 826 }, 827 { 828 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 829 "CollectPEBSRecord": "2", 830 "Counter": "0,1,2,3,4,5,6,7", 831 "EventCode": "0x2e", 832 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 833 "PEBScounters": "0,1,2,3,4,5,6,7", 834 "SampleAfterValue": "100003", 835 "Speculative": "1", 836 "UMask": "0x4f", 837 "Unit": "cpu_core" 838 }, 839 { 840 "BriefDescription": "Retired load instructions.", 841 "CollectPEBSRecord": "2", 842 "Counter": "0,1,2,3", 843 "Data_LA": "1", 844 "EventCode": "0xd0", 845 "EventName": "MEM_INST_RETIRED.ALL_LOADS", 846 "PEBS": "1", 847 "PEBScounters": "0,1,2,3", 848 "SampleAfterValue": "1000003", 849 "UMask": "0x81", 850 "Unit": "cpu_core" 851 }, 852 { 853 "BriefDescription": "Retired store instructions.", 854 "CollectPEBSRecord": "2", 855 "Counter": "0,1,2,3", 856 "Data_LA": "1", 857 "EventCode": "0xd0", 858 "EventName": "MEM_INST_RETIRED.ALL_STORES", 859 "L1_Hit_Indication": "1", 860 "PEBS": "1", 861 "PEBScounters": "0,1,2,3", 862 "SampleAfterValue": "1000003", 863 "UMask": "0x82", 864 "Unit": "cpu_core" 865 }, 866 { 867 "BriefDescription": "All retired memory instructions.", 868 "CollectPEBSRecord": "2", 869 "Counter": "0,1,2,3", 870 "Data_LA": "1", 871 "EventCode": "0xd0", 872 "EventName": "MEM_INST_RETIRED.ANY", 873 "L1_Hit_Indication": "1", 874 "PEBS": "1", 875 "PEBScounters": "0,1,2,3", 876 "SampleAfterValue": "1000003", 877 "UMask": "0x83", 878 "Unit": "cpu_core" 879 }, 880 { 881 "BriefDescription": "Retired load instructions with locked access.", 882 "CollectPEBSRecord": "2", 883 "Counter": "0,1,2,3", 884 "Data_LA": "1", 885 "EventCode": "0xd0", 886 "EventName": "MEM_INST_RETIRED.LOCK_LOADS", 887 "PEBS": "1", 888 "PEBScounters": "0,1,2,3", 889 "SampleAfterValue": "100007", 890 "UMask": "0x21", 891 "Unit": "cpu_core" 892 }, 893 { 894 "BriefDescription": "Retired load instructions that split across a cacheline boundary.", 895 "CollectPEBSRecord": "2", 896 "Counter": "0,1,2,3", 897 "Data_LA": "1", 898 "EventCode": "0xd0", 899 "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", 900 "PEBS": "1", 901 "PEBScounters": "0,1,2,3", 902 "SampleAfterValue": "100003", 903 "UMask": "0x41", 904 "Unit": "cpu_core" 905 }, 906 { 907 "BriefDescription": "Retired store instructions that split across a cacheline boundary.", 908 "CollectPEBSRecord": "2", 909 "Counter": "0,1,2,3", 910 "Data_LA": "1", 911 "EventCode": "0xd0", 912 "EventName": "MEM_INST_RETIRED.SPLIT_STORES", 913 "L1_Hit_Indication": "1", 914 "PEBS": "1", 915 "PEBScounters": "0,1,2,3", 916 "SampleAfterValue": "100003", 917 "UMask": "0x42", 918 "Unit": "cpu_core" 919 }, 920 { 921 "BriefDescription": "Retired load instructions that miss the STLB.", 922 "CollectPEBSRecord": "2", 923 "Counter": "0,1,2,3", 924 "Data_LA": "1", 925 "EventCode": "0xd0", 926 "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", 927 "PEBS": "1", 928 "PEBScounters": "0,1,2,3", 929 "SampleAfterValue": "100003", 930 "UMask": "0x11", 931 "Unit": "cpu_core" 932 }, 933 { 934 "BriefDescription": "Retired store instructions that miss the STLB.", 935 "CollectPEBSRecord": "2", 936 "Counter": "0,1,2,3", 937 "Data_LA": "1", 938 "EventCode": "0xd0", 939 "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", 940 "L1_Hit_Indication": "1", 941 "PEBS": "1", 942 "PEBScounters": "0,1,2,3", 943 "SampleAfterValue": "100003", 944 "UMask": "0x12", 945 "Unit": "cpu_core" 946 }, 947 { 948 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 949 "CollectPEBSRecord": "2", 950 "Counter": "0,1,2,3", 951 "EventCode": "0x43", 952 "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", 953 "PEBScounters": "0,1,2,3", 954 "SampleAfterValue": "1000003", 955 "Speculative": "1", 956 "UMask": "0xfd", 957 "Unit": "cpu_core" 958 }, 959 { 960 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 961 "CollectPEBSRecord": "2", 962 "Counter": "0,1,2,3", 963 "Data_LA": "1", 964 "EventCode": "0xd2", 965 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", 966 "PEBS": "1", 967 "PEBScounters": "0,1,2,3", 968 "SampleAfterValue": "20011", 969 "UMask": "0x4", 970 "Unit": "cpu_core" 971 }, 972 { 973 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 974 "CollectPEBSRecord": "2", 975 "Counter": "0,1,2,3", 976 "Data_LA": "1", 977 "EventCode": "0xd2", 978 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 979 "PEBS": "1", 980 "PEBScounters": "0,1,2,3", 981 "SampleAfterValue": "20011", 982 "UMask": "0x2", 983 "Unit": "cpu_core" 984 }, 985 { 986 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 987 "CollectPEBSRecord": "2", 988 "Counter": "0,1,2,3", 989 "Data_LA": "1", 990 "EventCode": "0xd2", 991 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 992 "PEBS": "1", 993 "PEBScounters": "0,1,2,3", 994 "SampleAfterValue": "20011", 995 "UMask": "0x4", 996 "Unit": "cpu_core" 997 }, 998 { 999 "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 1000 "CollectPEBSRecord": "2", 1001 "Counter": "0,1,2,3", 1002 "Data_LA": "1", 1003 "EventCode": "0xd2", 1004 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 1005 "PEBS": "1", 1006 "PEBScounters": "0,1,2,3", 1007 "SampleAfterValue": "20011", 1008 "UMask": "0x1", 1009 "Unit": "cpu_core" 1010 }, 1011 { 1012 "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", 1013 "CollectPEBSRecord": "2", 1014 "Counter": "0,1,2,3", 1015 "Data_LA": "1", 1016 "EventCode": "0xd2", 1017 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 1018 "PEBS": "1", 1019 "PEBScounters": "0,1,2,3", 1020 "SampleAfterValue": "100003", 1021 "UMask": "0x8", 1022 "Unit": "cpu_core" 1023 }, 1024 { 1025 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 1026 "CollectPEBSRecord": "2", 1027 "Counter": "0,1,2,3", 1028 "Data_LA": "1", 1029 "EventCode": "0xd2", 1030 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", 1031 "PEBS": "1", 1032 "PEBScounters": "0,1,2,3", 1033 "SampleAfterValue": "20011", 1034 "UMask": "0x2", 1035 "Unit": "cpu_core" 1036 }, 1037 { 1038 "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", 1039 "Counter": "0,1,2,3", 1040 "Data_LA": "1", 1041 "EventCode": "0xd3", 1042 "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", 1043 "PEBScounters": "0,1,2,3", 1044 "SampleAfterValue": "100007", 1045 "UMask": "0x1", 1046 "Unit": "cpu_core" 1047 }, 1048 { 1049 "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", 1050 "CollectPEBSRecord": "2", 1051 "Counter": "0,1,2,3", 1052 "Data_LA": "1", 1053 "EventCode": "0xd4", 1054 "EventName": "MEM_LOAD_MISC_RETIRED.UC", 1055 "PEBS": "1", 1056 "PEBScounters": "0,1,2,3", 1057 "SampleAfterValue": "100007", 1058 "UMask": "0x4", 1059 "Unit": "cpu_core" 1060 }, 1061 { 1062 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 1063 "CollectPEBSRecord": "2", 1064 "Counter": "0,1,2,3", 1065 "Data_LA": "1", 1066 "EventCode": "0xd1", 1067 "EventName": "MEM_LOAD_RETIRED.FB_HIT", 1068 "PEBS": "1", 1069 "PEBScounters": "0,1,2,3", 1070 "SampleAfterValue": "100007", 1071 "UMask": "0x40", 1072 "Unit": "cpu_core" 1073 }, 1074 { 1075 "BriefDescription": "Retired load instructions with L1 cache hits as data sources", 1076 "CollectPEBSRecord": "2", 1077 "Counter": "0,1,2,3", 1078 "Data_LA": "1", 1079 "EventCode": "0xd1", 1080 "EventName": "MEM_LOAD_RETIRED.L1_HIT", 1081 "PEBS": "1", 1082 "PEBScounters": "0,1,2,3", 1083 "SampleAfterValue": "1000003", 1084 "UMask": "0x1", 1085 "Unit": "cpu_core" 1086 }, 1087 { 1088 "BriefDescription": "Retired load instructions missed L1 cache as data sources", 1089 "CollectPEBSRecord": "2", 1090 "Counter": "0,1,2,3", 1091 "Data_LA": "1", 1092 "EventCode": "0xd1", 1093 "EventName": "MEM_LOAD_RETIRED.L1_MISS", 1094 "PEBS": "1", 1095 "PEBScounters": "0,1,2,3", 1096 "SampleAfterValue": "200003", 1097 "UMask": "0x8", 1098 "Unit": "cpu_core" 1099 }, 1100 { 1101 "BriefDescription": "Retired load instructions with L2 cache hits as data sources", 1102 "CollectPEBSRecord": "2", 1103 "Counter": "0,1,2,3", 1104 "Data_LA": "1", 1105 "EventCode": "0xd1", 1106 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 1107 "PEBS": "1", 1108 "PEBScounters": "0,1,2,3", 1109 "SampleAfterValue": "200003", 1110 "UMask": "0x2", 1111 "Unit": "cpu_core" 1112 }, 1113 { 1114 "BriefDescription": "Retired load instructions missed L2 cache as data sources", 1115 "CollectPEBSRecord": "2", 1116 "Counter": "0,1,2,3", 1117 "Data_LA": "1", 1118 "EventCode": "0xd1", 1119 "EventName": "MEM_LOAD_RETIRED.L2_MISS", 1120 "PEBS": "1", 1121 "PEBScounters": "0,1,2,3", 1122 "SampleAfterValue": "100021", 1123 "UMask": "0x10", 1124 "Unit": "cpu_core" 1125 }, 1126 { 1127 "BriefDescription": "Retired load instructions with L3 cache hits as data sources", 1128 "CollectPEBSRecord": "2", 1129 "Counter": "0,1,2,3", 1130 "Data_LA": "1", 1131 "EventCode": "0xd1", 1132 "EventName": "MEM_LOAD_RETIRED.L3_HIT", 1133 "PEBS": "1", 1134 "PEBScounters": "0,1,2,3", 1135 "SampleAfterValue": "100021", 1136 "UMask": "0x4", 1137 "Unit": "cpu_core" 1138 }, 1139 { 1140 "BriefDescription": "Retired load instructions missed L3 cache as data sources", 1141 "CollectPEBSRecord": "2", 1142 "Counter": "0,1,2,3", 1143 "Data_LA": "1", 1144 "EventCode": "0xd1", 1145 "EventName": "MEM_LOAD_RETIRED.L3_MISS", 1146 "PEBS": "1", 1147 "PEBScounters": "0,1,2,3", 1148 "SampleAfterValue": "50021", 1149 "UMask": "0x20", 1150 "Unit": "cpu_core" 1151 }, 1152 { 1153 "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", 1154 "CollectPEBSRecord": "2", 1155 "Counter": "0,1,2,3", 1156 "EventCode": "0x44", 1157 "EventName": "MEM_STORE_RETIRED.L2_HIT", 1158 "PEBScounters": "0,1,2,3", 1159 "SampleAfterValue": "200003", 1160 "UMask": "0x1", 1161 "Unit": "cpu_core" 1162 }, 1163 { 1164 "BriefDescription": "Retired memory uops for any access", 1165 "Counter": "0,1,2,3,4,5,6,7", 1166 "EventCode": "0xe5", 1167 "EventName": "MEM_UOP_RETIRED.ANY", 1168 "PEBScounters": "0,1,2,3,4,5,6,7", 1169 "SampleAfterValue": "1000003", 1170 "UMask": "0x3", 1171 "Unit": "cpu_core" 1172 }, 1173 { 1174 "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 1175 "Counter": "0,1,2,3,4,5,6,7", 1176 "EventCode": "0x2A,0x2B", 1177 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 1178 "MSRIndex": "0x1a6,0x1a7", 1179 "MSRValue": "0x10003C0001", 1180 "SampleAfterValue": "100003", 1181 "UMask": "0x1", 1182 "Unit": "cpu_core" 1183 }, 1184 { 1185 "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1186 "Counter": "0,1,2,3,4,5,6,7", 1187 "EventCode": "0x2A,0x2B", 1188 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1189 "MSRIndex": "0x1a6,0x1a7", 1190 "MSRValue": "0x8003C0001", 1191 "SampleAfterValue": "100003", 1192 "UMask": "0x1", 1193 "Unit": "cpu_core" 1194 }, 1195 { 1196 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 1197 "Counter": "0,1,2,3,4,5,6,7", 1198 "EventCode": "0x2A,0x2B", 1199 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 1200 "MSRIndex": "0x1a6,0x1a7", 1201 "MSRValue": "0x10003C0002", 1202 "SampleAfterValue": "100003", 1203 "UMask": "0x1", 1204 "Unit": "cpu_core" 1205 }, 1206 { 1207 "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", 1208 "CollectPEBSRecord": "2", 1209 "Counter": "0,1,2,3", 1210 "EventCode": "0x21", 1211 "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", 1212 "PEBScounters": "0,1,2,3", 1213 "SampleAfterValue": "100003", 1214 "Speculative": "1", 1215 "UMask": "0x80", 1216 "Unit": "cpu_core" 1217 }, 1218 { 1219 "BriefDescription": "Demand and prefetch data reads", 1220 "CollectPEBSRecord": "2", 1221 "Counter": "0,1,2,3", 1222 "EventCode": "0x21", 1223 "EventName": "OFFCORE_REQUESTS.DATA_RD", 1224 "PEBScounters": "0,1,2,3", 1225 "SampleAfterValue": "100003", 1226 "Speculative": "1", 1227 "UMask": "0x8", 1228 "Unit": "cpu_core" 1229 }, 1230 { 1231 "BriefDescription": "Demand Data Read requests sent to uncore", 1232 "CollectPEBSRecord": "2", 1233 "Counter": "0,1,2,3", 1234 "EventCode": "0x21", 1235 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 1236 "PEBScounters": "0,1,2,3", 1237 "SampleAfterValue": "100003", 1238 "Speculative": "1", 1239 "UMask": "0x1", 1240 "Unit": "cpu_core" 1241 }, 1242 { 1243 "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1244 "CollectPEBSRecord": "2", 1245 "Counter": "0,1,2,3", 1246 "Errata": "ADL038", 1247 "EventCode": "0x20", 1248 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 1249 "PEBScounters": "0,1,2,3", 1250 "SampleAfterValue": "1000003", 1251 "Speculative": "1", 1252 "UMask": "0x8", 1253 "Unit": "cpu_core" 1254 }, 1255 { 1256 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1257 "CollectPEBSRecord": "2", 1258 "Counter": "0,1,2,3", 1259 "CounterMask": "1", 1260 "Errata": "ADL038", 1261 "EventCode": "0x20", 1262 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1263 "PEBScounters": "0,1,2,3", 1264 "SampleAfterValue": "1000003", 1265 "Speculative": "1", 1266 "UMask": "0x8", 1267 "Unit": "cpu_core" 1268 }, 1269 { 1270 "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", 1271 "CollectPEBSRecord": "2", 1272 "Counter": "0,1,2,3", 1273 "CounterMask": "1", 1274 "EventCode": "0x20", 1275 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 1276 "PEBScounters": "0,1,2,3", 1277 "SampleAfterValue": "1000003", 1278 "Speculative": "1", 1279 "UMask": "0x4", 1280 "Unit": "cpu_core" 1281 }, 1282 { 1283 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1284 "CollectPEBSRecord": "2", 1285 "Counter": "0,1,2,3", 1286 "Errata": "ADL038", 1287 "EventCode": "0x20", 1288 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1289 "PEBScounters": "0,1,2,3", 1290 "SampleAfterValue": "1000003", 1291 "Speculative": "1", 1292 "UMask": "0x8", 1293 "Unit": "cpu_core" 1294 }, 1295 { 1296 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 1297 "CollectPEBSRecord": "2", 1298 "Counter": "0,1,2,3", 1299 "EventCode": "0x40", 1300 "EventName": "SW_PREFETCH_ACCESS.NTA", 1301 "PEBScounters": "0,1,2,3", 1302 "SampleAfterValue": "100003", 1303 "Speculative": "1", 1304 "UMask": "0x1", 1305 "Unit": "cpu_core" 1306 }, 1307 { 1308 "BriefDescription": "Number of PREFETCHW instructions executed.", 1309 "CollectPEBSRecord": "2", 1310 "Counter": "0,1,2,3", 1311 "EventCode": "0x40", 1312 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 1313 "PEBScounters": "0,1,2,3", 1314 "SampleAfterValue": "100003", 1315 "Speculative": "1", 1316 "UMask": "0x8", 1317 "Unit": "cpu_core" 1318 }, 1319 { 1320 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 1321 "CollectPEBSRecord": "2", 1322 "Counter": "0,1,2,3", 1323 "EventCode": "0x40", 1324 "EventName": "SW_PREFETCH_ACCESS.T0", 1325 "PEBScounters": "0,1,2,3", 1326 "SampleAfterValue": "100003", 1327 "Speculative": "1", 1328 "UMask": "0x2", 1329 "Unit": "cpu_core" 1330 }, 1331 { 1332 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 1333 "CollectPEBSRecord": "2", 1334 "Counter": "0,1,2,3", 1335 "EventCode": "0x40", 1336 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 1337 "PEBScounters": "0,1,2,3", 1338 "SampleAfterValue": "100003", 1339 "Speculative": "1", 1340 "UMask": "0x4", 1341 "Unit": "cpu_core" 1342 } 1343] 1344