1[ 2 { 3 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5", 6 "EventCode": "0x34", 7 "EventName": "MEM_BOUND_STALLS.IFETCH", 8 "PEBScounters": "0,1,2,3,4,5", 9 "SampleAfterValue": "200003", 10 "Speculative": "1", 11 "UMask": "0x38", 12 "Unit": "cpu_atom" 13 }, 14 { 15 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3,4,5", 18 "EventCode": "0x34", 19 "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", 20 "PEBScounters": "0,1,2,3,4,5", 21 "SampleAfterValue": "200003", 22 "Speculative": "1", 23 "UMask": "0x20", 24 "Unit": "cpu_atom" 25 }, 26 { 27 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3,4,5", 30 "EventCode": "0x34", 31 "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", 32 "PEBScounters": "0,1,2,3,4,5", 33 "SampleAfterValue": "200003", 34 "Speculative": "1", 35 "UMask": "0x8", 36 "Unit": "cpu_atom" 37 }, 38 { 39 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", 40 "CollectPEBSRecord": "2", 41 "Counter": "0,1,2,3,4,5", 42 "EventCode": "0x34", 43 "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", 44 "PEBScounters": "0,1,2,3,4,5", 45 "SampleAfterValue": "200003", 46 "Speculative": "1", 47 "UMask": "0x10", 48 "Unit": "cpu_atom" 49 }, 50 { 51 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 52 "CollectPEBSRecord": "2", 53 "Counter": "0,1,2,3,4,5", 54 "EventCode": "0x34", 55 "EventName": "MEM_BOUND_STALLS.LOAD", 56 "PEBScounters": "0,1,2,3,4,5", 57 "SampleAfterValue": "200003", 58 "Speculative": "1", 59 "UMask": "0x7", 60 "Unit": "cpu_atom" 61 }, 62 { 63 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 64 "CollectPEBSRecord": "2", 65 "Counter": "0,1,2,3,4,5", 66 "EventCode": "0x34", 67 "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", 68 "PEBScounters": "0,1,2,3,4,5", 69 "SampleAfterValue": "200003", 70 "Speculative": "1", 71 "UMask": "0x4", 72 "Unit": "cpu_atom" 73 }, 74 { 75 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 76 "CollectPEBSRecord": "2", 77 "Counter": "0,1,2,3,4,5", 78 "EventCode": "0x34", 79 "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", 80 "PEBScounters": "0,1,2,3,4,5", 81 "SampleAfterValue": "200003", 82 "Speculative": "1", 83 "UMask": "0x1", 84 "Unit": "cpu_atom" 85 }, 86 { 87 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", 88 "CollectPEBSRecord": "2", 89 "Counter": "0,1,2,3,4,5", 90 "EventCode": "0x34", 91 "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", 92 "PEBScounters": "0,1,2,3,4,5", 93 "SampleAfterValue": "200003", 94 "Speculative": "1", 95 "UMask": "0x2", 96 "Unit": "cpu_atom" 97 }, 98 { 99 "BriefDescription": "Counts the number of load uops retired that hit in DRAM.", 100 "CollectPEBSRecord": "2", 101 "Counter": "0,1,2,3,4,5", 102 "Data_LA": "1", 103 "EventCode": "0xd1", 104 "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 105 "PEBS": "1", 106 "PEBScounters": "0,1,2,3,4,5", 107 "SampleAfterValue": "200003", 108 "UMask": "0x80", 109 "Unit": "cpu_atom" 110 }, 111 { 112 "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", 113 "CollectPEBSRecord": "2", 114 "Counter": "0,1,2,3,4,5", 115 "Data_LA": "1", 116 "EventCode": "0xd1", 117 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 118 "PEBS": "1", 119 "PEBScounters": "0,1,2,3,4,5", 120 "SampleAfterValue": "200003", 121 "UMask": "0x2", 122 "Unit": "cpu_atom" 123 }, 124 { 125 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 126 "CollectPEBSRecord": "2", 127 "Counter": "0,1,2,3,4,5", 128 "Data_LA": "1", 129 "EventCode": "0xd1", 130 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 131 "PEBS": "1", 132 "PEBScounters": "0,1,2,3,4,5", 133 "SampleAfterValue": "200003", 134 "UMask": "0x4", 135 "Unit": "cpu_atom" 136 }, 137 { 138 "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", 139 "CollectPEBSRecord": "2", 140 "Counter": "0,1,2,3,4,5", 141 "EventCode": "0x04", 142 "EventName": "MEM_SCHEDULER_BLOCK.ALL", 143 "PEBScounters": "0,1,2,3,4,5", 144 "SampleAfterValue": "20003", 145 "Speculative": "1", 146 "UMask": "0x7", 147 "Unit": "cpu_atom" 148 }, 149 { 150 "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", 151 "CollectPEBSRecord": "2", 152 "Counter": "0,1,2,3,4,5", 153 "EventCode": "0x04", 154 "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", 155 "PEBScounters": "0,1,2,3,4,5", 156 "SampleAfterValue": "20003", 157 "Speculative": "1", 158 "UMask": "0x2", 159 "Unit": "cpu_atom" 160 }, 161 { 162 "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", 163 "CollectPEBSRecord": "2", 164 "Counter": "0,1,2,3,4,5", 165 "EventCode": "0x04", 166 "EventName": "MEM_SCHEDULER_BLOCK.RSV", 167 "PEBScounters": "0,1,2,3,4,5", 168 "SampleAfterValue": "20003", 169 "Speculative": "1", 170 "UMask": "0x4", 171 "Unit": "cpu_atom" 172 }, 173 { 174 "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", 175 "CollectPEBSRecord": "2", 176 "Counter": "0,1,2,3,4,5", 177 "EventCode": "0x04", 178 "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", 179 "PEBScounters": "0,1,2,3,4,5", 180 "SampleAfterValue": "20003", 181 "Speculative": "1", 182 "UMask": "0x1", 183 "Unit": "cpu_atom" 184 }, 185 { 186 "BriefDescription": "Counts the number of load uops retired.", 187 "CollectPEBSRecord": "2", 188 "Counter": "0,1,2,3,4,5", 189 "Data_LA": "1", 190 "EventCode": "0xd0", 191 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 192 "PEBS": "1", 193 "PEBScounters": "0,1,2,3,4,5", 194 "SampleAfterValue": "200003", 195 "UMask": "0x81", 196 "Unit": "cpu_atom" 197 }, 198 { 199 "BriefDescription": "Counts the number of store uops retired.", 200 "CollectPEBSRecord": "2", 201 "Counter": "0,1,2,3,4,5", 202 "Data_LA": "1", 203 "EventCode": "0xd0", 204 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 205 "PEBS": "1", 206 "PEBScounters": "0,1,2,3,4,5", 207 "SampleAfterValue": "200003", 208 "UMask": "0x82", 209 "Unit": "cpu_atom" 210 }, 211 { 212 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 213 "CollectPEBSRecord": "3", 214 "Counter": "0,1,2,3,4,5", 215 "Data_LA": "1", 216 "EventCode": "0xd0", 217 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 218 "L1_Hit_Indication": "1", 219 "MSRIndex": "0x3F6", 220 "MSRValue": "0x80", 221 "PEBS": "2", 222 "PEBScounters": "0,1,2,3,4,5", 223 "SampleAfterValue": "1000003", 224 "TakenAlone": "1", 225 "UMask": "0x5", 226 "Unit": "cpu_atom" 227 }, 228 { 229 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 230 "CollectPEBSRecord": "3", 231 "Counter": "0,1,2,3,4,5", 232 "Data_LA": "1", 233 "EventCode": "0xd0", 234 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 235 "L1_Hit_Indication": "1", 236 "MSRIndex": "0x3F6", 237 "MSRValue": "0x10", 238 "PEBS": "2", 239 "PEBScounters": "0,1,2,3,4,5", 240 "SampleAfterValue": "1000003", 241 "TakenAlone": "1", 242 "UMask": "0x5", 243 "Unit": "cpu_atom" 244 }, 245 { 246 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 247 "CollectPEBSRecord": "3", 248 "Counter": "0,1,2,3,4,5", 249 "Data_LA": "1", 250 "EventCode": "0xd0", 251 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", 252 "L1_Hit_Indication": "1", 253 "MSRIndex": "0x3F6", 254 "MSRValue": "0x100", 255 "PEBS": "2", 256 "PEBScounters": "0,1,2,3,4,5", 257 "SampleAfterValue": "1000003", 258 "TakenAlone": "1", 259 "UMask": "0x5", 260 "Unit": "cpu_atom" 261 }, 262 { 263 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 264 "CollectPEBSRecord": "3", 265 "Counter": "0,1,2,3,4,5", 266 "Data_LA": "1", 267 "EventCode": "0xd0", 268 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", 269 "L1_Hit_Indication": "1", 270 "MSRIndex": "0x3F6", 271 "MSRValue": "0x20", 272 "PEBS": "2", 273 "PEBScounters": "0,1,2,3,4,5", 274 "SampleAfterValue": "1000003", 275 "TakenAlone": "1", 276 "UMask": "0x5", 277 "Unit": "cpu_atom" 278 }, 279 { 280 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 281 "CollectPEBSRecord": "3", 282 "Counter": "0,1,2,3,4,5", 283 "Data_LA": "1", 284 "EventCode": "0xd0", 285 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", 286 "L1_Hit_Indication": "1", 287 "MSRIndex": "0x3F6", 288 "MSRValue": "0x4", 289 "PEBS": "2", 290 "PEBScounters": "0,1,2,3,4,5", 291 "SampleAfterValue": "1000003", 292 "TakenAlone": "1", 293 "UMask": "0x5", 294 "Unit": "cpu_atom" 295 }, 296 { 297 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 298 "CollectPEBSRecord": "3", 299 "Counter": "0,1,2,3,4,5", 300 "Data_LA": "1", 301 "EventCode": "0xd0", 302 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", 303 "L1_Hit_Indication": "1", 304 "MSRIndex": "0x3F6", 305 "MSRValue": "0x200", 306 "PEBS": "2", 307 "PEBScounters": "0,1,2,3,4,5", 308 "SampleAfterValue": "1000003", 309 "TakenAlone": "1", 310 "UMask": "0x5", 311 "Unit": "cpu_atom" 312 }, 313 { 314 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 315 "CollectPEBSRecord": "3", 316 "Counter": "0,1,2,3,4,5", 317 "Data_LA": "1", 318 "EventCode": "0xd0", 319 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", 320 "L1_Hit_Indication": "1", 321 "MSRIndex": "0x3F6", 322 "MSRValue": "0x40", 323 "PEBS": "2", 324 "PEBScounters": "0,1,2,3,4,5", 325 "SampleAfterValue": "1000003", 326 "TakenAlone": "1", 327 "UMask": "0x5", 328 "Unit": "cpu_atom" 329 }, 330 { 331 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 332 "CollectPEBSRecord": "3", 333 "Counter": "0,1,2,3,4,5", 334 "Data_LA": "1", 335 "EventCode": "0xd0", 336 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", 337 "L1_Hit_Indication": "1", 338 "MSRIndex": "0x3F6", 339 "MSRValue": "0x8", 340 "PEBS": "2", 341 "PEBScounters": "0,1,2,3,4,5", 342 "SampleAfterValue": "1000003", 343 "TakenAlone": "1", 344 "UMask": "0x5", 345 "Unit": "cpu_atom" 346 }, 347 { 348 "BriefDescription": "Counts the number of retired split load uops.", 349 "CollectPEBSRecord": "2", 350 "Counter": "0,1,2,3,4,5", 351 "Data_LA": "1", 352 "EventCode": "0xd0", 353 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 354 "PEBS": "1", 355 "PEBScounters": "0,1,2,3,4,5", 356 "SampleAfterValue": "200003", 357 "UMask": "0x41", 358 "Unit": "cpu_atom" 359 }, 360 { 361 "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", 362 "CollectPEBSRecord": "3", 363 "Counter": "0,1,2,3,4,5", 364 "Data_LA": "1", 365 "EventCode": "0xd0", 366 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", 367 "L1_Hit_Indication": "1", 368 "PEBS": "2", 369 "PEBScounters": "0,1,2,3,4,5", 370 "SampleAfterValue": "1000003", 371 "UMask": "0x6", 372 "Unit": "cpu_atom" 373 }, 374 { 375 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 376 "Counter": "0,1,2,3,4,5", 377 "EventCode": "0xB7", 378 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0x10003C0002", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1", 383 "Unit": "cpu_atom" 384 }, 385 { 386 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", 387 "CollectPEBSRecord": "2", 388 "Counter": "0,1,2,3,4,5", 389 "EventCode": "0x71", 390 "EventName": "TOPDOWN_FE_BOUND.ICACHE", 391 "PEBScounters": "0,1,2,3,4,5", 392 "SampleAfterValue": "1000003", 393 "Speculative": "1", 394 "UMask": "0x20", 395 "Unit": "cpu_atom" 396 }, 397 { 398 "BriefDescription": "L1D.HWPF_MISS", 399 "CollectPEBSRecord": "2", 400 "Counter": "0,1,2,3", 401 "EventCode": "0x51", 402 "EventName": "L1D.HWPF_MISS", 403 "PEBScounters": "0,1,2,3", 404 "SampleAfterValue": "1000003", 405 "Speculative": "1", 406 "UMask": "0x20", 407 "Unit": "cpu_core" 408 }, 409 { 410 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 411 "CollectPEBSRecord": "2", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x51", 414 "EventName": "L1D.REPLACEMENT", 415 "PEBScounters": "0,1,2,3", 416 "SampleAfterValue": "100003", 417 "Speculative": "1", 418 "UMask": "0x1", 419 "Unit": "cpu_core" 420 }, 421 { 422 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 423 "CollectPEBSRecord": "2", 424 "Counter": "0,1,2,3", 425 "EventCode": "0x48", 426 "EventName": "L1D_PEND_MISS.FB_FULL", 427 "PEBScounters": "0,1,2,3", 428 "SampleAfterValue": "1000003", 429 "Speculative": "1", 430 "UMask": "0x2", 431 "Unit": "cpu_core" 432 }, 433 { 434 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", 435 "CollectPEBSRecord": "2", 436 "Counter": "0,1,2,3", 437 "CounterMask": "1", 438 "EdgeDetect": "1", 439 "EventCode": "0x48", 440 "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", 441 "PEBScounters": "0,1,2,3", 442 "SampleAfterValue": "1000003", 443 "Speculative": "1", 444 "UMask": "0x2", 445 "Unit": "cpu_core" 446 }, 447 { 448 "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", 449 "CollectPEBSRecord": "2", 450 "Counter": "0,1,2,3", 451 "EventCode": "0x48", 452 "EventName": "L1D_PEND_MISS.L2_STALL", 453 "PEBScounters": "0,1,2,3", 454 "SampleAfterValue": "1000003", 455 "Speculative": "1", 456 "UMask": "0x4", 457 "Unit": "cpu_core" 458 }, 459 { 460 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 461 "CollectPEBSRecord": "2", 462 "Counter": "0,1,2,3", 463 "EventCode": "0x48", 464 "EventName": "L1D_PEND_MISS.L2_STALLS", 465 "PEBScounters": "0,1,2,3", 466 "SampleAfterValue": "1000003", 467 "Speculative": "1", 468 "UMask": "0x4", 469 "Unit": "cpu_core" 470 }, 471 { 472 "BriefDescription": "Number of L1D misses that are outstanding", 473 "CollectPEBSRecord": "2", 474 "Counter": "0,1,2,3", 475 "EventCode": "0x48", 476 "EventName": "L1D_PEND_MISS.PENDING", 477 "PEBScounters": "0,1,2,3", 478 "SampleAfterValue": "1000003", 479 "Speculative": "1", 480 "UMask": "0x1", 481 "Unit": "cpu_core" 482 }, 483 { 484 "BriefDescription": "Cycles with L1D load Misses outstanding.", 485 "CollectPEBSRecord": "2", 486 "Counter": "0,1,2,3", 487 "CounterMask": "1", 488 "EventCode": "0x48", 489 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 490 "PEBScounters": "0,1,2,3", 491 "SampleAfterValue": "1000003", 492 "Speculative": "1", 493 "UMask": "0x1", 494 "Unit": "cpu_core" 495 }, 496 { 497 "BriefDescription": "L2 cache lines filling L2", 498 "CollectPEBSRecord": "2", 499 "Counter": "0,1,2,3", 500 "EventCode": "0x25", 501 "EventName": "L2_LINES_IN.ALL", 502 "PEBScounters": "0,1,2,3", 503 "SampleAfterValue": "100003", 504 "Speculative": "1", 505 "UMask": "0x1f", 506 "Unit": "cpu_core" 507 }, 508 { 509 "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 510 "CollectPEBSRecord": "2", 511 "Counter": "0,1,2,3", 512 "EventCode": "0x26", 513 "EventName": "L2_LINES_OUT.USELESS_HWPF", 514 "PEBScounters": "0,1,2,3", 515 "SampleAfterValue": "200003", 516 "Speculative": "1", 517 "UMask": "0x4", 518 "Unit": "cpu_core" 519 }, 520 { 521 "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]", 522 "CollectPEBSRecord": "2", 523 "Counter": "0,1,2,3", 524 "EventCode": "0x24", 525 "EventName": "L2_REQUEST.ALL", 526 "PEBScounters": "0,1,2,3", 527 "SampleAfterValue": "200003", 528 "Speculative": "1", 529 "UMask": "0xff", 530 "Unit": "cpu_core" 531 }, 532 { 533 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", 534 "CollectPEBSRecord": "2", 535 "Counter": "0,1,2,3", 536 "EventCode": "0x24", 537 "EventName": "L2_REQUEST.MISS", 538 "PEBScounters": "0,1,2,3", 539 "SampleAfterValue": "200003", 540 "Speculative": "1", 541 "UMask": "0x3f", 542 "Unit": "cpu_core" 543 }, 544 { 545 "BriefDescription": "L2 code requests", 546 "CollectPEBSRecord": "2", 547 "Counter": "0,1,2,3", 548 "EventCode": "0x24", 549 "EventName": "L2_RQSTS.ALL_CODE_RD", 550 "PEBScounters": "0,1,2,3", 551 "SampleAfterValue": "200003", 552 "Speculative": "1", 553 "UMask": "0xe4", 554 "Unit": "cpu_core" 555 }, 556 { 557 "BriefDescription": "Demand Data Read access L2 cache", 558 "CollectPEBSRecord": "2", 559 "Counter": "0,1,2,3", 560 "EventCode": "0x24", 561 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 562 "PEBScounters": "0,1,2,3", 563 "SampleAfterValue": "200003", 564 "Speculative": "1", 565 "UMask": "0xe1", 566 "Unit": "cpu_core" 567 }, 568 { 569 "BriefDescription": "Demand requests that miss L2 cache", 570 "CollectPEBSRecord": "2", 571 "Counter": "0,1,2,3", 572 "EventCode": "0x24", 573 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 574 "PEBScounters": "0,1,2,3", 575 "SampleAfterValue": "200003", 576 "Speculative": "1", 577 "UMask": "0x27", 578 "Unit": "cpu_core" 579 }, 580 { 581 "BriefDescription": "L2_RQSTS.ALL_HWPF", 582 "CollectPEBSRecord": "2", 583 "Counter": "0,1,2,3", 584 "EventCode": "0x24", 585 "EventName": "L2_RQSTS.ALL_HWPF", 586 "PEBScounters": "0,1,2,3", 587 "SampleAfterValue": "200003", 588 "Speculative": "1", 589 "UMask": "0xf0", 590 "Unit": "cpu_core" 591 }, 592 { 593 "BriefDescription": "RFO requests to L2 cache.", 594 "CollectPEBSRecord": "2", 595 "Counter": "0,1,2,3", 596 "EventCode": "0x24", 597 "EventName": "L2_RQSTS.ALL_RFO", 598 "PEBScounters": "0,1,2,3", 599 "SampleAfterValue": "200003", 600 "Speculative": "1", 601 "UMask": "0xe2", 602 "Unit": "cpu_core" 603 }, 604 { 605 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 606 "CollectPEBSRecord": "2", 607 "Counter": "0,1,2,3", 608 "EventCode": "0x24", 609 "EventName": "L2_RQSTS.CODE_RD_HIT", 610 "PEBScounters": "0,1,2,3", 611 "SampleAfterValue": "200003", 612 "Speculative": "1", 613 "UMask": "0xc4", 614 "Unit": "cpu_core" 615 }, 616 { 617 "BriefDescription": "L2 cache misses when fetching instructions", 618 "CollectPEBSRecord": "2", 619 "Counter": "0,1,2,3", 620 "EventCode": "0x24", 621 "EventName": "L2_RQSTS.CODE_RD_MISS", 622 "PEBScounters": "0,1,2,3", 623 "SampleAfterValue": "200003", 624 "Speculative": "1", 625 "UMask": "0x24", 626 "Unit": "cpu_core" 627 }, 628 { 629 "BriefDescription": "Demand Data Read requests that hit L2 cache", 630 "CollectPEBSRecord": "2", 631 "Counter": "0,1,2,3", 632 "EventCode": "0x24", 633 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 634 "PEBScounters": "0,1,2,3", 635 "SampleAfterValue": "200003", 636 "Speculative": "1", 637 "UMask": "0xc1", 638 "Unit": "cpu_core" 639 }, 640 { 641 "BriefDescription": "Demand Data Read miss L2 cache", 642 "CollectPEBSRecord": "2", 643 "Counter": "0,1,2,3", 644 "EventCode": "0x24", 645 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 646 "PEBScounters": "0,1,2,3", 647 "SampleAfterValue": "200003", 648 "Speculative": "1", 649 "UMask": "0x21", 650 "Unit": "cpu_core" 651 }, 652 { 653 "BriefDescription": "L2_RQSTS.HWPF_MISS", 654 "CollectPEBSRecord": "2", 655 "Counter": "0,1,2,3", 656 "EventCode": "0x24", 657 "EventName": "L2_RQSTS.HWPF_MISS", 658 "PEBScounters": "0,1,2,3", 659 "SampleAfterValue": "200003", 660 "Speculative": "1", 661 "UMask": "0x30", 662 "Unit": "cpu_core" 663 }, 664 { 665 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", 666 "CollectPEBSRecord": "2", 667 "Counter": "0,1,2,3", 668 "EventCode": "0x24", 669 "EventName": "L2_RQSTS.MISS", 670 "PEBScounters": "0,1,2,3", 671 "SampleAfterValue": "200003", 672 "Speculative": "1", 673 "UMask": "0x3f", 674 "Unit": "cpu_core" 675 }, 676 { 677 "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]", 678 "CollectPEBSRecord": "2", 679 "Counter": "0,1,2,3", 680 "EventCode": "0x24", 681 "EventName": "L2_RQSTS.REFERENCES", 682 "PEBScounters": "0,1,2,3", 683 "SampleAfterValue": "200003", 684 "Speculative": "1", 685 "UMask": "0xff", 686 "Unit": "cpu_core" 687 }, 688 { 689 "BriefDescription": "RFO requests that hit L2 cache.", 690 "CollectPEBSRecord": "2", 691 "Counter": "0,1,2,3", 692 "EventCode": "0x24", 693 "EventName": "L2_RQSTS.RFO_HIT", 694 "PEBScounters": "0,1,2,3", 695 "SampleAfterValue": "200003", 696 "Speculative": "1", 697 "UMask": "0xc2", 698 "Unit": "cpu_core" 699 }, 700 { 701 "BriefDescription": "RFO requests that miss L2 cache", 702 "CollectPEBSRecord": "2", 703 "Counter": "0,1,2,3", 704 "EventCode": "0x24", 705 "EventName": "L2_RQSTS.RFO_MISS", 706 "PEBScounters": "0,1,2,3", 707 "SampleAfterValue": "200003", 708 "Speculative": "1", 709 "UMask": "0x22", 710 "Unit": "cpu_core" 711 }, 712 { 713 "BriefDescription": "SW prefetch requests that hit L2 cache.", 714 "CollectPEBSRecord": "2", 715 "Counter": "0,1,2,3", 716 "EventCode": "0x24", 717 "EventName": "L2_RQSTS.SWPF_HIT", 718 "PEBScounters": "0,1,2,3", 719 "SampleAfterValue": "200003", 720 "Speculative": "1", 721 "UMask": "0xc8", 722 "Unit": "cpu_core" 723 }, 724 { 725 "BriefDescription": "SW prefetch requests that miss L2 cache.", 726 "CollectPEBSRecord": "2", 727 "Counter": "0,1,2,3", 728 "EventCode": "0x24", 729 "EventName": "L2_RQSTS.SWPF_MISS", 730 "PEBScounters": "0,1,2,3", 731 "SampleAfterValue": "200003", 732 "Speculative": "1", 733 "UMask": "0x28", 734 "Unit": "cpu_core" 735 }, 736 { 737 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 738 "CollectPEBSRecord": "2", 739 "Counter": "0,1,2,3,4,5,6,7", 740 "EventCode": "0x2e", 741 "EventName": "LONGEST_LAT_CACHE.MISS", 742 "PEBScounters": "0,1,2,3,4,5,6,7", 743 "SampleAfterValue": "100003", 744 "Speculative": "1", 745 "UMask": "0x41", 746 "Unit": "cpu_core" 747 }, 748 { 749 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 750 "CollectPEBSRecord": "2", 751 "Counter": "0,1,2,3,4,5,6,7", 752 "EventCode": "0x2e", 753 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 754 "PEBScounters": "0,1,2,3,4,5,6,7", 755 "SampleAfterValue": "100003", 756 "Speculative": "1", 757 "UMask": "0x4f", 758 "Unit": "cpu_core" 759 }, 760 { 761 "BriefDescription": "Retired load instructions.", 762 "CollectPEBSRecord": "2", 763 "Counter": "0,1,2,3", 764 "Data_LA": "1", 765 "EventCode": "0xd0", 766 "EventName": "MEM_INST_RETIRED.ALL_LOADS", 767 "PEBS": "1", 768 "PEBScounters": "0,1,2,3", 769 "SampleAfterValue": "1000003", 770 "UMask": "0x81", 771 "Unit": "cpu_core" 772 }, 773 { 774 "BriefDescription": "Retired store instructions.", 775 "CollectPEBSRecord": "2", 776 "Counter": "0,1,2,3", 777 "Data_LA": "1", 778 "EventCode": "0xd0", 779 "EventName": "MEM_INST_RETIRED.ALL_STORES", 780 "L1_Hit_Indication": "1", 781 "PEBS": "1", 782 "PEBScounters": "0,1,2,3", 783 "SampleAfterValue": "1000003", 784 "UMask": "0x82", 785 "Unit": "cpu_core" 786 }, 787 { 788 "BriefDescription": "All retired memory instructions.", 789 "CollectPEBSRecord": "2", 790 "Counter": "0,1,2,3", 791 "Data_LA": "1", 792 "EventCode": "0xd0", 793 "EventName": "MEM_INST_RETIRED.ANY", 794 "L1_Hit_Indication": "1", 795 "PEBS": "1", 796 "PEBScounters": "0,1,2,3", 797 "SampleAfterValue": "1000003", 798 "UMask": "0x83", 799 "Unit": "cpu_core" 800 }, 801 { 802 "BriefDescription": "Retired load instructions with locked access.", 803 "CollectPEBSRecord": "2", 804 "Counter": "0,1,2,3", 805 "Data_LA": "1", 806 "EventCode": "0xd0", 807 "EventName": "MEM_INST_RETIRED.LOCK_LOADS", 808 "PEBS": "1", 809 "PEBScounters": "0,1,2,3", 810 "SampleAfterValue": "100007", 811 "UMask": "0x21", 812 "Unit": "cpu_core" 813 }, 814 { 815 "BriefDescription": "Retired load instructions that split across a cacheline boundary.", 816 "CollectPEBSRecord": "2", 817 "Counter": "0,1,2,3", 818 "Data_LA": "1", 819 "EventCode": "0xd0", 820 "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", 821 "PEBS": "1", 822 "PEBScounters": "0,1,2,3", 823 "SampleAfterValue": "100003", 824 "UMask": "0x41", 825 "Unit": "cpu_core" 826 }, 827 { 828 "BriefDescription": "Retired store instructions that split across a cacheline boundary.", 829 "CollectPEBSRecord": "2", 830 "Counter": "0,1,2,3", 831 "Data_LA": "1", 832 "EventCode": "0xd0", 833 "EventName": "MEM_INST_RETIRED.SPLIT_STORES", 834 "L1_Hit_Indication": "1", 835 "PEBS": "1", 836 "PEBScounters": "0,1,2,3", 837 "SampleAfterValue": "100003", 838 "UMask": "0x42", 839 "Unit": "cpu_core" 840 }, 841 { 842 "BriefDescription": "Retired load instructions that miss the STLB.", 843 "CollectPEBSRecord": "2", 844 "Counter": "0,1,2,3", 845 "Data_LA": "1", 846 "EventCode": "0xd0", 847 "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", 848 "PEBS": "1", 849 "PEBScounters": "0,1,2,3", 850 "SampleAfterValue": "100003", 851 "UMask": "0x11", 852 "Unit": "cpu_core" 853 }, 854 { 855 "BriefDescription": "Retired store instructions that miss the STLB.", 856 "CollectPEBSRecord": "2", 857 "Counter": "0,1,2,3", 858 "Data_LA": "1", 859 "EventCode": "0xd0", 860 "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", 861 "L1_Hit_Indication": "1", 862 "PEBS": "1", 863 "PEBScounters": "0,1,2,3", 864 "SampleAfterValue": "100003", 865 "UMask": "0x12", 866 "Unit": "cpu_core" 867 }, 868 { 869 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 870 "CollectPEBSRecord": "2", 871 "Counter": "0,1,2,3", 872 "EventCode": "0x43", 873 "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", 874 "PEBScounters": "0,1,2,3", 875 "SampleAfterValue": "1000003", 876 "Speculative": "1", 877 "UMask": "0xfd", 878 "Unit": "cpu_core" 879 }, 880 { 881 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 882 "CollectPEBSRecord": "2", 883 "Counter": "0,1,2,3", 884 "Data_LA": "1", 885 "EventCode": "0xd2", 886 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", 887 "PEBS": "1", 888 "PEBScounters": "0,1,2,3", 889 "SampleAfterValue": "20011", 890 "UMask": "0x4", 891 "Unit": "cpu_core" 892 }, 893 { 894 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 895 "CollectPEBSRecord": "2", 896 "Counter": "0,1,2,3", 897 "Data_LA": "1", 898 "EventCode": "0xd2", 899 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 900 "PEBS": "1", 901 "PEBScounters": "0,1,2,3", 902 "SampleAfterValue": "20011", 903 "UMask": "0x2", 904 "Unit": "cpu_core" 905 }, 906 { 907 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 908 "CollectPEBSRecord": "2", 909 "Counter": "0,1,2,3", 910 "Data_LA": "1", 911 "EventCode": "0xd2", 912 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 913 "PEBS": "1", 914 "PEBScounters": "0,1,2,3", 915 "SampleAfterValue": "20011", 916 "UMask": "0x4", 917 "Unit": "cpu_core" 918 }, 919 { 920 "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 921 "CollectPEBSRecord": "2", 922 "Counter": "0,1,2,3", 923 "Data_LA": "1", 924 "EventCode": "0xd2", 925 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 926 "PEBS": "1", 927 "PEBScounters": "0,1,2,3", 928 "SampleAfterValue": "20011", 929 "UMask": "0x1", 930 "Unit": "cpu_core" 931 }, 932 { 933 "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", 934 "CollectPEBSRecord": "2", 935 "Counter": "0,1,2,3", 936 "Data_LA": "1", 937 "EventCode": "0xd2", 938 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 939 "PEBS": "1", 940 "PEBScounters": "0,1,2,3", 941 "SampleAfterValue": "100003", 942 "UMask": "0x8", 943 "Unit": "cpu_core" 944 }, 945 { 946 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 947 "CollectPEBSRecord": "2", 948 "Counter": "0,1,2,3", 949 "Data_LA": "1", 950 "EventCode": "0xd2", 951 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", 952 "PEBS": "1", 953 "PEBScounters": "0,1,2,3", 954 "SampleAfterValue": "20011", 955 "UMask": "0x2", 956 "Unit": "cpu_core" 957 }, 958 { 959 "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", 960 "Counter": "0,1,2,3", 961 "Data_LA": "1", 962 "EventCode": "0xd3", 963 "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", 964 "PEBScounters": "0,1,2,3", 965 "SampleAfterValue": "100007", 966 "UMask": "0x1", 967 "Unit": "cpu_core" 968 }, 969 { 970 "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", 971 "CollectPEBSRecord": "2", 972 "Counter": "0,1,2,3", 973 "Data_LA": "1", 974 "EventCode": "0xd4", 975 "EventName": "MEM_LOAD_MISC_RETIRED.UC", 976 "PEBS": "1", 977 "PEBScounters": "0,1,2,3", 978 "SampleAfterValue": "100007", 979 "UMask": "0x4", 980 "Unit": "cpu_core" 981 }, 982 { 983 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 984 "CollectPEBSRecord": "2", 985 "Counter": "0,1,2,3", 986 "Data_LA": "1", 987 "EventCode": "0xd1", 988 "EventName": "MEM_LOAD_RETIRED.FB_HIT", 989 "PEBS": "1", 990 "PEBScounters": "0,1,2,3", 991 "SampleAfterValue": "100007", 992 "UMask": "0x40", 993 "Unit": "cpu_core" 994 }, 995 { 996 "BriefDescription": "Retired load instructions with L1 cache hits as data sources", 997 "CollectPEBSRecord": "2", 998 "Counter": "0,1,2,3", 999 "Data_LA": "1", 1000 "EventCode": "0xd1", 1001 "EventName": "MEM_LOAD_RETIRED.L1_HIT", 1002 "PEBS": "1", 1003 "PEBScounters": "0,1,2,3", 1004 "SampleAfterValue": "1000003", 1005 "UMask": "0x1", 1006 "Unit": "cpu_core" 1007 }, 1008 { 1009 "BriefDescription": "Retired load instructions missed L1 cache as data sources", 1010 "CollectPEBSRecord": "2", 1011 "Counter": "0,1,2,3", 1012 "Data_LA": "1", 1013 "EventCode": "0xd1", 1014 "EventName": "MEM_LOAD_RETIRED.L1_MISS", 1015 "PEBS": "1", 1016 "PEBScounters": "0,1,2,3", 1017 "SampleAfterValue": "200003", 1018 "UMask": "0x8", 1019 "Unit": "cpu_core" 1020 }, 1021 { 1022 "BriefDescription": "Retired load instructions with L2 cache hits as data sources", 1023 "CollectPEBSRecord": "2", 1024 "Counter": "0,1,2,3", 1025 "Data_LA": "1", 1026 "EventCode": "0xd1", 1027 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 1028 "PEBS": "1", 1029 "PEBScounters": "0,1,2,3", 1030 "SampleAfterValue": "200003", 1031 "UMask": "0x2", 1032 "Unit": "cpu_core" 1033 }, 1034 { 1035 "BriefDescription": "Retired load instructions missed L2 cache as data sources", 1036 "CollectPEBSRecord": "2", 1037 "Counter": "0,1,2,3", 1038 "Data_LA": "1", 1039 "EventCode": "0xd1", 1040 "EventName": "MEM_LOAD_RETIRED.L2_MISS", 1041 "PEBS": "1", 1042 "PEBScounters": "0,1,2,3", 1043 "SampleAfterValue": "100021", 1044 "UMask": "0x10", 1045 "Unit": "cpu_core" 1046 }, 1047 { 1048 "BriefDescription": "Retired load instructions with L3 cache hits as data sources", 1049 "CollectPEBSRecord": "2", 1050 "Counter": "0,1,2,3", 1051 "Data_LA": "1", 1052 "EventCode": "0xd1", 1053 "EventName": "MEM_LOAD_RETIRED.L3_HIT", 1054 "PEBS": "1", 1055 "PEBScounters": "0,1,2,3", 1056 "SampleAfterValue": "100021", 1057 "UMask": "0x4", 1058 "Unit": "cpu_core" 1059 }, 1060 { 1061 "BriefDescription": "Retired load instructions missed L3 cache as data sources", 1062 "CollectPEBSRecord": "2", 1063 "Counter": "0,1,2,3", 1064 "Data_LA": "1", 1065 "EventCode": "0xd1", 1066 "EventName": "MEM_LOAD_RETIRED.L3_MISS", 1067 "PEBS": "1", 1068 "PEBScounters": "0,1,2,3", 1069 "SampleAfterValue": "50021", 1070 "UMask": "0x20", 1071 "Unit": "cpu_core" 1072 }, 1073 { 1074 "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", 1075 "CollectPEBSRecord": "2", 1076 "Counter": "0,1,2,3", 1077 "EventCode": "0x44", 1078 "EventName": "MEM_STORE_RETIRED.L2_HIT", 1079 "PEBScounters": "0,1,2,3", 1080 "SampleAfterValue": "200003", 1081 "UMask": "0x1", 1082 "Unit": "cpu_core" 1083 }, 1084 { 1085 "BriefDescription": "Retired memory uops for any access", 1086 "Counter": "0,1,2,3,4,5,6,7", 1087 "EventCode": "0xe5", 1088 "EventName": "MEM_UOP_RETIRED.ANY", 1089 "PEBScounters": "0,1,2,3,4,5,6,7", 1090 "SampleAfterValue": "1000003", 1091 "UMask": "0x3", 1092 "Unit": "cpu_core" 1093 }, 1094 { 1095 "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 1096 "Counter": "0,1,2,3,4,5,6,7", 1097 "EventCode": "0x2A,0x2B", 1098 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 1099 "MSRIndex": "0x1a6,0x1a7", 1100 "MSRValue": "0x10003C0001", 1101 "SampleAfterValue": "100003", 1102 "UMask": "0x1", 1103 "Unit": "cpu_core" 1104 }, 1105 { 1106 "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1107 "Counter": "0,1,2,3,4,5,6,7", 1108 "EventCode": "0x2A,0x2B", 1109 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1110 "MSRIndex": "0x1a6,0x1a7", 1111 "MSRValue": "0x8003C0001", 1112 "SampleAfterValue": "100003", 1113 "UMask": "0x1", 1114 "Unit": "cpu_core" 1115 }, 1116 { 1117 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 1118 "Counter": "0,1,2,3,4,5,6,7", 1119 "EventCode": "0x2A,0x2B", 1120 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 1121 "MSRIndex": "0x1a6,0x1a7", 1122 "MSRValue": "0x10003C0002", 1123 "SampleAfterValue": "100003", 1124 "UMask": "0x1", 1125 "Unit": "cpu_core" 1126 }, 1127 { 1128 "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", 1129 "CollectPEBSRecord": "2", 1130 "Counter": "0,1,2,3", 1131 "EventCode": "0x21", 1132 "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", 1133 "PEBScounters": "0,1,2,3", 1134 "SampleAfterValue": "100003", 1135 "Speculative": "1", 1136 "UMask": "0x80", 1137 "Unit": "cpu_core" 1138 }, 1139 { 1140 "BriefDescription": "Demand and prefetch data reads", 1141 "CollectPEBSRecord": "2", 1142 "Counter": "0,1,2,3", 1143 "EventCode": "0x21", 1144 "EventName": "OFFCORE_REQUESTS.DATA_RD", 1145 "PEBScounters": "0,1,2,3", 1146 "SampleAfterValue": "100003", 1147 "Speculative": "1", 1148 "UMask": "0x8", 1149 "Unit": "cpu_core" 1150 }, 1151 { 1152 "BriefDescription": "Demand Data Read requests sent to uncore", 1153 "CollectPEBSRecord": "2", 1154 "Counter": "0,1,2,3", 1155 "EventCode": "0x21", 1156 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 1157 "PEBScounters": "0,1,2,3", 1158 "SampleAfterValue": "100003", 1159 "Speculative": "1", 1160 "UMask": "0x1", 1161 "Unit": "cpu_core" 1162 }, 1163 { 1164 "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1165 "CollectPEBSRecord": "2", 1166 "Counter": "0,1,2,3", 1167 "Errata": "ADL038", 1168 "EventCode": "0x20", 1169 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 1170 "PEBScounters": "0,1,2,3", 1171 "SampleAfterValue": "1000003", 1172 "Speculative": "1", 1173 "UMask": "0x8", 1174 "Unit": "cpu_core" 1175 }, 1176 { 1177 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1178 "CollectPEBSRecord": "2", 1179 "Counter": "0,1,2,3", 1180 "CounterMask": "1", 1181 "Errata": "ADL038", 1182 "EventCode": "0x20", 1183 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1184 "PEBScounters": "0,1,2,3", 1185 "SampleAfterValue": "1000003", 1186 "Speculative": "1", 1187 "UMask": "0x8", 1188 "Unit": "cpu_core" 1189 }, 1190 { 1191 "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", 1192 "CollectPEBSRecord": "2", 1193 "Counter": "0,1,2,3", 1194 "CounterMask": "1", 1195 "EventCode": "0x20", 1196 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 1197 "PEBScounters": "0,1,2,3", 1198 "SampleAfterValue": "1000003", 1199 "Speculative": "1", 1200 "UMask": "0x4", 1201 "Unit": "cpu_core" 1202 }, 1203 { 1204 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1205 "CollectPEBSRecord": "2", 1206 "Counter": "0,1,2,3", 1207 "Errata": "ADL038", 1208 "EventCode": "0x20", 1209 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1210 "PEBScounters": "0,1,2,3", 1211 "SampleAfterValue": "1000003", 1212 "Speculative": "1", 1213 "UMask": "0x8", 1214 "Unit": "cpu_core" 1215 }, 1216 { 1217 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 1218 "CollectPEBSRecord": "2", 1219 "Counter": "0,1,2,3", 1220 "EventCode": "0x40", 1221 "EventName": "SW_PREFETCH_ACCESS.NTA", 1222 "PEBScounters": "0,1,2,3", 1223 "SampleAfterValue": "100003", 1224 "Speculative": "1", 1225 "UMask": "0x1", 1226 "Unit": "cpu_core" 1227 }, 1228 { 1229 "BriefDescription": "Number of PREFETCHW instructions executed.", 1230 "CollectPEBSRecord": "2", 1231 "Counter": "0,1,2,3", 1232 "EventCode": "0x40", 1233 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 1234 "PEBScounters": "0,1,2,3", 1235 "SampleAfterValue": "100003", 1236 "Speculative": "1", 1237 "UMask": "0x8", 1238 "Unit": "cpu_core" 1239 }, 1240 { 1241 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 1242 "CollectPEBSRecord": "2", 1243 "Counter": "0,1,2,3", 1244 "EventCode": "0x40", 1245 "EventName": "SW_PREFETCH_ACCESS.T0", 1246 "PEBScounters": "0,1,2,3", 1247 "SampleAfterValue": "100003", 1248 "Speculative": "1", 1249 "UMask": "0x2", 1250 "Unit": "cpu_core" 1251 }, 1252 { 1253 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 1254 "CollectPEBSRecord": "2", 1255 "Counter": "0,1,2,3", 1256 "EventCode": "0x40", 1257 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 1258 "PEBScounters": "0,1,2,3", 1259 "SampleAfterValue": "100003", 1260 "Speculative": "1", 1261 "UMask": "0x4", 1262 "Unit": "cpu_core" 1263 } 1264] 1265