xref: /openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/cache.json (revision a95ab294)

[
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x38",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.LOAD",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x7",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.ALL",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "20003",
        "Speculative": "1",
        "UMask": "0x7",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "20003",
        "Speculative": "1",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.RSV",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "20003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "20003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "UMask": "0x81",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of store uops retired.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "UMask": "0x82",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
        "L1_Hit_Indication": "1",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "TakenAlone": "1",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired split load uops.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "200003",
        "UMask": "0x41",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
        "CollectPEBSRecord": "3",
        "Counter": "0,1,2,3,4,5",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
        "L1_Hit_Indication": "1",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "UMask": "0x6",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x71",
        "EventName": "TOPDOWN_FE_BOUND.ICACHE",
        "PEBScounters": "0,1,2,3,4,5",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "L1D.HWPF_MISS",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.HWPF_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALL",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALLS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.ALL",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.ALL",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x3f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 code requests",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xe4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read access L2 cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xe1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand requests that miss L2 cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x27",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2_RQSTS.ALL_HWPF",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_HWPF",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xf0",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests to L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_RFO",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xe2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xc4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache misses when fetching instructions",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x24",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xc1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read miss L2 cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x21",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2_RQSTS.HWPF_MISS",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.HWPF_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x30",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x3f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.REFERENCES",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests that hit L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_HIT",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xc2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests that miss L2 cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x22",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "SW prefetch requests that hit L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_HIT",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0xc8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "SW prefetch requests that miss L2 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "Speculative": "1",
        "UMask": "0x28",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x4f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "UMask": "0x81",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_STORES",
        "L1_Hit_Indication": "1",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "UMask": "0x82",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All retired memory instructions.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ANY",
        "L1_Hit_Indication": "1",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "UMask": "0x83",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with locked access.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100007",
        "UMask": "0x21",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
        "L1_Hit_Indication": "1",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0x42",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that miss the STLB.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0x11",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that miss the STLB.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
        "L1_Hit_Indication": "1",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0x12",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x43",
        "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0xfd",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "20011",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "20011",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "20011",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "20011",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "20011",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100007",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd4",
        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100007",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100007",
        "UMask": "0x40",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100021",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100021",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
        "PEBS": "1",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "50021",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x44",
        "EventName": "MEM_STORE_RETIRED.L2_HIT",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired memory uops for any access",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xe5",
        "EventName": "MEM_UOP_RETIRED.ANY",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "SampleAfterValue": "1000003",
        "UMask": "0x3",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x8003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x80",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand and prefetch data reads",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DATA_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Errata": "ADL038",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "Errata": "ADL038",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "Errata": "ADL038",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x4",
        "Unit": "cpu_core"
    }
]