1f9900dd0SZhengjun Xing[ 2f9900dd0SZhengjun Xing { 3*a80de066SIan Rogers "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 4*a80de066SIan Rogers "CollectPEBSRecord": "2", 5*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 6*a80de066SIan Rogers "EventCode": "0x2e", 7*a80de066SIan Rogers "EventName": "LONGEST_LAT_CACHE.MISS", 8*a80de066SIan Rogers "PEBScounters": "0,1,2,3,4,5", 9*a80de066SIan Rogers "SampleAfterValue": "200003", 10*a80de066SIan Rogers "Speculative": "1", 11*a80de066SIan Rogers "UMask": "0x41", 12*a80de066SIan Rogers "Unit": "cpu_atom" 13*a80de066SIan Rogers }, 14*a80de066SIan Rogers { 15*a80de066SIan Rogers "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 16*a80de066SIan Rogers "CollectPEBSRecord": "2", 17*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 18*a80de066SIan Rogers "EventCode": "0x2e", 19*a80de066SIan Rogers "EventName": "LONGEST_LAT_CACHE.REFERENCE", 20*a80de066SIan Rogers "PEBScounters": "0,1,2,3,4,5", 21*a80de066SIan Rogers "SampleAfterValue": "200003", 22*a80de066SIan Rogers "Speculative": "1", 23*a80de066SIan Rogers "UMask": "0x4f", 24*a80de066SIan Rogers "Unit": "cpu_atom" 25*a80de066SIan Rogers }, 26*a80de066SIan Rogers { 275fa2481cSZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 28f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 29f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 30f9900dd0SZhengjun Xing "EventCode": "0x34", 31f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.IFETCH", 32f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 33f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 345fa2481cSZhengjun Xing "Speculative": "1", 35f9900dd0SZhengjun Xing "UMask": "0x38", 36f9900dd0SZhengjun Xing "Unit": "cpu_atom" 37f9900dd0SZhengjun Xing }, 38f9900dd0SZhengjun Xing { 395fa2481cSZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 40f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 41f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 42f9900dd0SZhengjun Xing "EventCode": "0x34", 43f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", 44f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 45f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 465fa2481cSZhengjun Xing "Speculative": "1", 47f9900dd0SZhengjun Xing "UMask": "0x20", 48f9900dd0SZhengjun Xing "Unit": "cpu_atom" 49f9900dd0SZhengjun Xing }, 50f9900dd0SZhengjun Xing { 515fa2481cSZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 52f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 53f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 54f9900dd0SZhengjun Xing "EventCode": "0x34", 55f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", 56f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 57f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 585fa2481cSZhengjun Xing "Speculative": "1", 59f9900dd0SZhengjun Xing "UMask": "0x8", 60f9900dd0SZhengjun Xing "Unit": "cpu_atom" 61f9900dd0SZhengjun Xing }, 62f9900dd0SZhengjun Xing { 635fa2481cSZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", 64f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 65f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 66f9900dd0SZhengjun Xing "EventCode": "0x34", 67f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", 68f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 69f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 705fa2481cSZhengjun Xing "Speculative": "1", 71f9900dd0SZhengjun Xing "UMask": "0x10", 72f9900dd0SZhengjun Xing "Unit": "cpu_atom" 73f9900dd0SZhengjun Xing }, 74f9900dd0SZhengjun Xing { 75f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 76f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 77f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 78f9900dd0SZhengjun Xing "EventCode": "0x34", 79f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.LOAD", 80f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 81f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 825fa2481cSZhengjun Xing "Speculative": "1", 83f9900dd0SZhengjun Xing "UMask": "0x7", 84f9900dd0SZhengjun Xing "Unit": "cpu_atom" 85f9900dd0SZhengjun Xing }, 86f9900dd0SZhengjun Xing { 87f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 88f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 89f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 90f9900dd0SZhengjun Xing "EventCode": "0x34", 91f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", 92f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 93f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 945fa2481cSZhengjun Xing "Speculative": "1", 95f9900dd0SZhengjun Xing "UMask": "0x4", 96f9900dd0SZhengjun Xing "Unit": "cpu_atom" 97f9900dd0SZhengjun Xing }, 98f9900dd0SZhengjun Xing { 99f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 100f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 101f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 102f9900dd0SZhengjun Xing "EventCode": "0x34", 103f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", 104f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 105f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 1065fa2481cSZhengjun Xing "Speculative": "1", 107f9900dd0SZhengjun Xing "UMask": "0x1", 108f9900dd0SZhengjun Xing "Unit": "cpu_atom" 109f9900dd0SZhengjun Xing }, 110f9900dd0SZhengjun Xing { 111f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", 112f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 113f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 114f9900dd0SZhengjun Xing "EventCode": "0x34", 115f9900dd0SZhengjun Xing "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", 116f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 117f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 1185fa2481cSZhengjun Xing "Speculative": "1", 119f9900dd0SZhengjun Xing "UMask": "0x2", 120f9900dd0SZhengjun Xing "Unit": "cpu_atom" 121f9900dd0SZhengjun Xing }, 122f9900dd0SZhengjun Xing { 1235fa2481cSZhengjun Xing "BriefDescription": "Counts the number of load uops retired that hit in DRAM.", 124f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 125f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 126f9900dd0SZhengjun Xing "Data_LA": "1", 127f9900dd0SZhengjun Xing "EventCode": "0xd1", 128f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 129f9900dd0SZhengjun Xing "PEBS": "1", 130f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 131f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 132f9900dd0SZhengjun Xing "UMask": "0x80", 133f9900dd0SZhengjun Xing "Unit": "cpu_atom" 134f9900dd0SZhengjun Xing }, 135f9900dd0SZhengjun Xing { 1365fa2481cSZhengjun Xing "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", 137f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 138f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 139f9900dd0SZhengjun Xing "Data_LA": "1", 140f9900dd0SZhengjun Xing "EventCode": "0xd1", 141f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 142f9900dd0SZhengjun Xing "PEBS": "1", 143f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 144f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 145f9900dd0SZhengjun Xing "UMask": "0x2", 146f9900dd0SZhengjun Xing "Unit": "cpu_atom" 147f9900dd0SZhengjun Xing }, 148f9900dd0SZhengjun Xing { 1495fa2481cSZhengjun Xing "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 150f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 151f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 1525fa2481cSZhengjun Xing "Data_LA": "1", 153f9900dd0SZhengjun Xing "EventCode": "0xd1", 154f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 155f9900dd0SZhengjun Xing "PEBS": "1", 156f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 157f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 158f9900dd0SZhengjun Xing "UMask": "0x4", 159f9900dd0SZhengjun Xing "Unit": "cpu_atom" 160f9900dd0SZhengjun Xing }, 161f9900dd0SZhengjun Xing { 162f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", 163f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 164f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 165f9900dd0SZhengjun Xing "EventCode": "0x04", 166f9900dd0SZhengjun Xing "EventName": "MEM_SCHEDULER_BLOCK.ALL", 167f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 168f9900dd0SZhengjun Xing "SampleAfterValue": "20003", 1695fa2481cSZhengjun Xing "Speculative": "1", 170f9900dd0SZhengjun Xing "UMask": "0x7", 171f9900dd0SZhengjun Xing "Unit": "cpu_atom" 172f9900dd0SZhengjun Xing }, 173f9900dd0SZhengjun Xing { 174f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", 175f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 176f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 177f9900dd0SZhengjun Xing "EventCode": "0x04", 178f9900dd0SZhengjun Xing "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", 179f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 180f9900dd0SZhengjun Xing "SampleAfterValue": "20003", 1815fa2481cSZhengjun Xing "Speculative": "1", 182f9900dd0SZhengjun Xing "UMask": "0x2", 183f9900dd0SZhengjun Xing "Unit": "cpu_atom" 184f9900dd0SZhengjun Xing }, 185f9900dd0SZhengjun Xing { 186f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", 187f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 188f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 189f9900dd0SZhengjun Xing "EventCode": "0x04", 190f9900dd0SZhengjun Xing "EventName": "MEM_SCHEDULER_BLOCK.RSV", 191f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 192f9900dd0SZhengjun Xing "SampleAfterValue": "20003", 1935fa2481cSZhengjun Xing "Speculative": "1", 194f9900dd0SZhengjun Xing "UMask": "0x4", 195f9900dd0SZhengjun Xing "Unit": "cpu_atom" 196f9900dd0SZhengjun Xing }, 197f9900dd0SZhengjun Xing { 198f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", 199f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 200f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 201f9900dd0SZhengjun Xing "EventCode": "0x04", 202f9900dd0SZhengjun Xing "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", 203f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 204f9900dd0SZhengjun Xing "SampleAfterValue": "20003", 2055fa2481cSZhengjun Xing "Speculative": "1", 206f9900dd0SZhengjun Xing "UMask": "0x1", 207f9900dd0SZhengjun Xing "Unit": "cpu_atom" 208f9900dd0SZhengjun Xing }, 209f9900dd0SZhengjun Xing { 210f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of load uops retired.", 211f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 212f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 213f9900dd0SZhengjun Xing "Data_LA": "1", 214f9900dd0SZhengjun Xing "EventCode": "0xd0", 215f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 216f9900dd0SZhengjun Xing "PEBS": "1", 217f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 218f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 219f9900dd0SZhengjun Xing "UMask": "0x81", 220f9900dd0SZhengjun Xing "Unit": "cpu_atom" 221f9900dd0SZhengjun Xing }, 222f9900dd0SZhengjun Xing { 223f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of store uops retired.", 224f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 225f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 226f9900dd0SZhengjun Xing "Data_LA": "1", 227f9900dd0SZhengjun Xing "EventCode": "0xd0", 228f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 229f9900dd0SZhengjun Xing "PEBS": "1", 230f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 231f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 232f9900dd0SZhengjun Xing "UMask": "0x82", 233f9900dd0SZhengjun Xing "Unit": "cpu_atom" 234f9900dd0SZhengjun Xing }, 235f9900dd0SZhengjun Xing { 236f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 237*a80de066SIan Rogers "CollectPEBSRecord": "2", 238*a80de066SIan Rogers "Counter": "0,1", 239f9900dd0SZhengjun Xing "Data_LA": "1", 240f9900dd0SZhengjun Xing "EventCode": "0xd0", 241f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 2425fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 243f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 244f9900dd0SZhengjun Xing "MSRValue": "0x80", 245f9900dd0SZhengjun Xing "PEBS": "2", 246*a80de066SIan Rogers "PEBScounters": "0,1", 247f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 248f9900dd0SZhengjun Xing "TakenAlone": "1", 249f9900dd0SZhengjun Xing "UMask": "0x5", 250f9900dd0SZhengjun Xing "Unit": "cpu_atom" 251f9900dd0SZhengjun Xing }, 252f9900dd0SZhengjun Xing { 253f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 254*a80de066SIan Rogers "CollectPEBSRecord": "2", 255*a80de066SIan Rogers "Counter": "0,1", 256f9900dd0SZhengjun Xing "Data_LA": "1", 257f9900dd0SZhengjun Xing "EventCode": "0xd0", 258f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 2595fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 260f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 261f9900dd0SZhengjun Xing "MSRValue": "0x10", 262f9900dd0SZhengjun Xing "PEBS": "2", 263*a80de066SIan Rogers "PEBScounters": "0,1", 264f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 265f9900dd0SZhengjun Xing "TakenAlone": "1", 266f9900dd0SZhengjun Xing "UMask": "0x5", 267f9900dd0SZhengjun Xing "Unit": "cpu_atom" 268f9900dd0SZhengjun Xing }, 269f9900dd0SZhengjun Xing { 270f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 271*a80de066SIan Rogers "CollectPEBSRecord": "2", 272*a80de066SIan Rogers "Counter": "0,1", 273f9900dd0SZhengjun Xing "Data_LA": "1", 274f9900dd0SZhengjun Xing "EventCode": "0xd0", 275f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", 2765fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 277f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 278f9900dd0SZhengjun Xing "MSRValue": "0x100", 279f9900dd0SZhengjun Xing "PEBS": "2", 280*a80de066SIan Rogers "PEBScounters": "0,1", 281f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 282f9900dd0SZhengjun Xing "TakenAlone": "1", 283f9900dd0SZhengjun Xing "UMask": "0x5", 284f9900dd0SZhengjun Xing "Unit": "cpu_atom" 285f9900dd0SZhengjun Xing }, 286f9900dd0SZhengjun Xing { 287f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 288*a80de066SIan Rogers "CollectPEBSRecord": "2", 289*a80de066SIan Rogers "Counter": "0,1", 290f9900dd0SZhengjun Xing "Data_LA": "1", 291f9900dd0SZhengjun Xing "EventCode": "0xd0", 292f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", 2935fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 294f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 295f9900dd0SZhengjun Xing "MSRValue": "0x20", 296f9900dd0SZhengjun Xing "PEBS": "2", 297*a80de066SIan Rogers "PEBScounters": "0,1", 298f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 299f9900dd0SZhengjun Xing "TakenAlone": "1", 300f9900dd0SZhengjun Xing "UMask": "0x5", 301f9900dd0SZhengjun Xing "Unit": "cpu_atom" 302f9900dd0SZhengjun Xing }, 303f9900dd0SZhengjun Xing { 304f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 305*a80de066SIan Rogers "CollectPEBSRecord": "2", 306*a80de066SIan Rogers "Counter": "0,1", 307f9900dd0SZhengjun Xing "Data_LA": "1", 308f9900dd0SZhengjun Xing "EventCode": "0xd0", 309f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", 3105fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 311f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 312f9900dd0SZhengjun Xing "MSRValue": "0x4", 313f9900dd0SZhengjun Xing "PEBS": "2", 314*a80de066SIan Rogers "PEBScounters": "0,1", 315f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 316f9900dd0SZhengjun Xing "TakenAlone": "1", 317f9900dd0SZhengjun Xing "UMask": "0x5", 318f9900dd0SZhengjun Xing "Unit": "cpu_atom" 319f9900dd0SZhengjun Xing }, 320f9900dd0SZhengjun Xing { 321f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 322*a80de066SIan Rogers "CollectPEBSRecord": "2", 323*a80de066SIan Rogers "Counter": "0,1", 324f9900dd0SZhengjun Xing "Data_LA": "1", 325f9900dd0SZhengjun Xing "EventCode": "0xd0", 326f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", 3275fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 328f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 329f9900dd0SZhengjun Xing "MSRValue": "0x200", 330f9900dd0SZhengjun Xing "PEBS": "2", 331*a80de066SIan Rogers "PEBScounters": "0,1", 332f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 333f9900dd0SZhengjun Xing "TakenAlone": "1", 334f9900dd0SZhengjun Xing "UMask": "0x5", 335f9900dd0SZhengjun Xing "Unit": "cpu_atom" 336f9900dd0SZhengjun Xing }, 337f9900dd0SZhengjun Xing { 338f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 339*a80de066SIan Rogers "CollectPEBSRecord": "2", 340*a80de066SIan Rogers "Counter": "0,1", 341f9900dd0SZhengjun Xing "Data_LA": "1", 342f9900dd0SZhengjun Xing "EventCode": "0xd0", 343f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", 3445fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 345f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 346f9900dd0SZhengjun Xing "MSRValue": "0x40", 347f9900dd0SZhengjun Xing "PEBS": "2", 348*a80de066SIan Rogers "PEBScounters": "0,1", 349f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 350f9900dd0SZhengjun Xing "TakenAlone": "1", 351f9900dd0SZhengjun Xing "UMask": "0x5", 352f9900dd0SZhengjun Xing "Unit": "cpu_atom" 353f9900dd0SZhengjun Xing }, 354f9900dd0SZhengjun Xing { 355f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", 356*a80de066SIan Rogers "CollectPEBSRecord": "2", 357*a80de066SIan Rogers "Counter": "0,1", 358f9900dd0SZhengjun Xing "Data_LA": "1", 359f9900dd0SZhengjun Xing "EventCode": "0xd0", 360f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", 3615fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 362f9900dd0SZhengjun Xing "MSRIndex": "0x3F6", 363f9900dd0SZhengjun Xing "MSRValue": "0x8", 364f9900dd0SZhengjun Xing "PEBS": "2", 365*a80de066SIan Rogers "PEBScounters": "0,1", 366f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 367f9900dd0SZhengjun Xing "TakenAlone": "1", 368f9900dd0SZhengjun Xing "UMask": "0x5", 369f9900dd0SZhengjun Xing "Unit": "cpu_atom" 370f9900dd0SZhengjun Xing }, 371f9900dd0SZhengjun Xing { 3725fa2481cSZhengjun Xing "BriefDescription": "Counts the number of retired split load uops.", 373f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 374f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 375f9900dd0SZhengjun Xing "Data_LA": "1", 376f9900dd0SZhengjun Xing "EventCode": "0xd0", 377f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 378f9900dd0SZhengjun Xing "PEBS": "1", 379f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 380f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 381f9900dd0SZhengjun Xing "UMask": "0x41", 382f9900dd0SZhengjun Xing "Unit": "cpu_atom" 383f9900dd0SZhengjun Xing }, 384f9900dd0SZhengjun Xing { 385f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", 386*a80de066SIan Rogers "CollectPEBSRecord": "2", 387f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 3885fa2481cSZhengjun Xing "Data_LA": "1", 389f9900dd0SZhengjun Xing "EventCode": "0xd0", 390f9900dd0SZhengjun Xing "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", 3915fa2481cSZhengjun Xing "L1_Hit_Indication": "1", 3925fa2481cSZhengjun Xing "PEBS": "2", 393f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 394f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 395f9900dd0SZhengjun Xing "UMask": "0x6", 396f9900dd0SZhengjun Xing "Unit": "cpu_atom" 397f9900dd0SZhengjun Xing }, 398f9900dd0SZhengjun Xing { 399*a80de066SIan Rogers "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.", 400*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 401*a80de066SIan Rogers "EventCode": "0xB7", 402*a80de066SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", 403*a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 404*a80de066SIan Rogers "MSRValue": "0x3F803C0001", 405*a80de066SIan Rogers "SampleAfterValue": "100003", 406*a80de066SIan Rogers "UMask": "0x1", 407*a80de066SIan Rogers "Unit": "cpu_atom" 408*a80de066SIan Rogers }, 409*a80de066SIan Rogers { 410*a80de066SIan Rogers "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 411*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 412*a80de066SIan Rogers "EventCode": "0xB7", 413*a80de066SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 414*a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 415*a80de066SIan Rogers "MSRValue": "0x10003C0001", 416*a80de066SIan Rogers "SampleAfterValue": "100003", 417*a80de066SIan Rogers "UMask": "0x1", 418*a80de066SIan Rogers "Unit": "cpu_atom" 419*a80de066SIan Rogers }, 420*a80de066SIan Rogers { 421*a80de066SIan Rogers "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 422*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 423*a80de066SIan Rogers "EventCode": "0xB7", 424*a80de066SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", 425*a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 426*a80de066SIan Rogers "MSRValue": "0x4003C0001", 427*a80de066SIan Rogers "SampleAfterValue": "100003", 428*a80de066SIan Rogers "UMask": "0x1", 429*a80de066SIan Rogers "Unit": "cpu_atom" 430*a80de066SIan Rogers }, 431*a80de066SIan Rogers { 432*a80de066SIan Rogers "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 433*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 434*a80de066SIan Rogers "EventCode": "0xB7", 435*a80de066SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 436*a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 437*a80de066SIan Rogers "MSRValue": "0x8003C0001", 438*a80de066SIan Rogers "SampleAfterValue": "100003", 439*a80de066SIan Rogers "UMask": "0x1", 440*a80de066SIan Rogers "Unit": "cpu_atom" 441*a80de066SIan Rogers }, 442*a80de066SIan Rogers { 443*a80de066SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", 444*a80de066SIan Rogers "Counter": "0,1,2,3,4,5", 445*a80de066SIan Rogers "EventCode": "0xB7", 446*a80de066SIan Rogers "EventName": "OCR.DEMAND_RFO.L3_HIT", 447*a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 448*a80de066SIan Rogers "MSRValue": "0x3F803C0002", 449*a80de066SIan Rogers "SampleAfterValue": "100003", 450*a80de066SIan Rogers "UMask": "0x1", 451*a80de066SIan Rogers "Unit": "cpu_atom" 452*a80de066SIan Rogers }, 453*a80de066SIan Rogers { 454f9900dd0SZhengjun Xing "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 4555fa2481cSZhengjun Xing "Counter": "0,1,2,3,4,5", 456f9900dd0SZhengjun Xing "EventCode": "0xB7", 457f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 458f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 459f9900dd0SZhengjun Xing "MSRValue": "0x10003C0002", 460f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 461f9900dd0SZhengjun Xing "UMask": "0x1", 462f9900dd0SZhengjun Xing "Unit": "cpu_atom" 463f9900dd0SZhengjun Xing }, 464f9900dd0SZhengjun Xing { 465f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", 466f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 467f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5", 468f9900dd0SZhengjun Xing "EventCode": "0x71", 469f9900dd0SZhengjun Xing "EventName": "TOPDOWN_FE_BOUND.ICACHE", 470f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5", 471f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 4725fa2481cSZhengjun Xing "Speculative": "1", 473f9900dd0SZhengjun Xing "UMask": "0x20", 474f9900dd0SZhengjun Xing "Unit": "cpu_atom" 475f9900dd0SZhengjun Xing }, 476f9900dd0SZhengjun Xing { 4775fa2481cSZhengjun Xing "BriefDescription": "L1D.HWPF_MISS", 4785fa2481cSZhengjun Xing "CollectPEBSRecord": "2", 4795fa2481cSZhengjun Xing "Counter": "0,1,2,3", 4805fa2481cSZhengjun Xing "EventCode": "0x51", 4815fa2481cSZhengjun Xing "EventName": "L1D.HWPF_MISS", 4825fa2481cSZhengjun Xing "PEBScounters": "0,1,2,3", 4835fa2481cSZhengjun Xing "SampleAfterValue": "1000003", 4845fa2481cSZhengjun Xing "Speculative": "1", 4855fa2481cSZhengjun Xing "UMask": "0x20", 4865fa2481cSZhengjun Xing "Unit": "cpu_core" 4875fa2481cSZhengjun Xing }, 4885fa2481cSZhengjun Xing { 489f9900dd0SZhengjun Xing "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 490f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 491f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 492f9900dd0SZhengjun Xing "EventCode": "0x51", 493f9900dd0SZhengjun Xing "EventName": "L1D.REPLACEMENT", 494f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 495f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 4965fa2481cSZhengjun Xing "Speculative": "1", 497f9900dd0SZhengjun Xing "UMask": "0x1", 498f9900dd0SZhengjun Xing "Unit": "cpu_core" 499f9900dd0SZhengjun Xing }, 500f9900dd0SZhengjun Xing { 501f9900dd0SZhengjun Xing "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 502f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 503f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 504f9900dd0SZhengjun Xing "EventCode": "0x48", 505f9900dd0SZhengjun Xing "EventName": "L1D_PEND_MISS.FB_FULL", 506f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 507f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 5085fa2481cSZhengjun Xing "Speculative": "1", 509f9900dd0SZhengjun Xing "UMask": "0x2", 510f9900dd0SZhengjun Xing "Unit": "cpu_core" 511f9900dd0SZhengjun Xing }, 512f9900dd0SZhengjun Xing { 513f9900dd0SZhengjun Xing "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", 514f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 515f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 516f9900dd0SZhengjun Xing "CounterMask": "1", 517f9900dd0SZhengjun Xing "EdgeDetect": "1", 518f9900dd0SZhengjun Xing "EventCode": "0x48", 519f9900dd0SZhengjun Xing "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", 520f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 521f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 5225fa2481cSZhengjun Xing "Speculative": "1", 523f9900dd0SZhengjun Xing "UMask": "0x2", 524f9900dd0SZhengjun Xing "Unit": "cpu_core" 525f9900dd0SZhengjun Xing }, 526f9900dd0SZhengjun Xing { 527f9900dd0SZhengjun Xing "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", 528f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 529f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 530f9900dd0SZhengjun Xing "EventCode": "0x48", 531f9900dd0SZhengjun Xing "EventName": "L1D_PEND_MISS.L2_STALL", 532f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 533f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 5345fa2481cSZhengjun Xing "Speculative": "1", 535f9900dd0SZhengjun Xing "UMask": "0x4", 536f9900dd0SZhengjun Xing "Unit": "cpu_core" 537f9900dd0SZhengjun Xing }, 538f9900dd0SZhengjun Xing { 539f9900dd0SZhengjun Xing "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 540f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 541f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 542f9900dd0SZhengjun Xing "EventCode": "0x48", 543f9900dd0SZhengjun Xing "EventName": "L1D_PEND_MISS.L2_STALLS", 544f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 545f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 5465fa2481cSZhengjun Xing "Speculative": "1", 547f9900dd0SZhengjun Xing "UMask": "0x4", 548f9900dd0SZhengjun Xing "Unit": "cpu_core" 549f9900dd0SZhengjun Xing }, 550f9900dd0SZhengjun Xing { 551f9900dd0SZhengjun Xing "BriefDescription": "Number of L1D misses that are outstanding", 552f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 553f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 554f9900dd0SZhengjun Xing "EventCode": "0x48", 555f9900dd0SZhengjun Xing "EventName": "L1D_PEND_MISS.PENDING", 556f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 557f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 5585fa2481cSZhengjun Xing "Speculative": "1", 559f9900dd0SZhengjun Xing "UMask": "0x1", 560f9900dd0SZhengjun Xing "Unit": "cpu_core" 561f9900dd0SZhengjun Xing }, 562f9900dd0SZhengjun Xing { 563f9900dd0SZhengjun Xing "BriefDescription": "Cycles with L1D load Misses outstanding.", 564f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 565f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 566f9900dd0SZhengjun Xing "CounterMask": "1", 567f9900dd0SZhengjun Xing "EventCode": "0x48", 568f9900dd0SZhengjun Xing "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 569f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 570f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 5715fa2481cSZhengjun Xing "Speculative": "1", 572f9900dd0SZhengjun Xing "UMask": "0x1", 573f9900dd0SZhengjun Xing "Unit": "cpu_core" 574f9900dd0SZhengjun Xing }, 575f9900dd0SZhengjun Xing { 576f9900dd0SZhengjun Xing "BriefDescription": "L2 cache lines filling L2", 577f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 578f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 579f9900dd0SZhengjun Xing "EventCode": "0x25", 580f9900dd0SZhengjun Xing "EventName": "L2_LINES_IN.ALL", 581f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 582f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 5835fa2481cSZhengjun Xing "Speculative": "1", 584f9900dd0SZhengjun Xing "UMask": "0x1f", 585f9900dd0SZhengjun Xing "Unit": "cpu_core" 586f9900dd0SZhengjun Xing }, 587f9900dd0SZhengjun Xing { 588a95ab294SIan Rogers "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 589a95ab294SIan Rogers "CollectPEBSRecord": "2", 590a95ab294SIan Rogers "Counter": "0,1,2,3", 591a95ab294SIan Rogers "EventCode": "0x26", 592a95ab294SIan Rogers "EventName": "L2_LINES_OUT.USELESS_HWPF", 593a95ab294SIan Rogers "PEBScounters": "0,1,2,3", 594a95ab294SIan Rogers "SampleAfterValue": "200003", 595a95ab294SIan Rogers "Speculative": "1", 596a95ab294SIan Rogers "UMask": "0x4", 597a95ab294SIan Rogers "Unit": "cpu_core" 598a95ab294SIan Rogers }, 599a95ab294SIan Rogers { 6005fa2481cSZhengjun Xing "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]", 601f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 602f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 603f9900dd0SZhengjun Xing "EventCode": "0x24", 604f9900dd0SZhengjun Xing "EventName": "L2_REQUEST.ALL", 605f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 606f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6075fa2481cSZhengjun Xing "Speculative": "1", 608f9900dd0SZhengjun Xing "UMask": "0xff", 609f9900dd0SZhengjun Xing "Unit": "cpu_core" 610f9900dd0SZhengjun Xing }, 611f9900dd0SZhengjun Xing { 612f9900dd0SZhengjun Xing "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", 613f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 614f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 615f9900dd0SZhengjun Xing "EventCode": "0x24", 616f9900dd0SZhengjun Xing "EventName": "L2_REQUEST.MISS", 617f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 618f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6195fa2481cSZhengjun Xing "Speculative": "1", 620f9900dd0SZhengjun Xing "UMask": "0x3f", 621f9900dd0SZhengjun Xing "Unit": "cpu_core" 622f9900dd0SZhengjun Xing }, 623f9900dd0SZhengjun Xing { 624f9900dd0SZhengjun Xing "BriefDescription": "L2 code requests", 625f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 626f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 627f9900dd0SZhengjun Xing "EventCode": "0x24", 628f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.ALL_CODE_RD", 629f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 630f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6315fa2481cSZhengjun Xing "Speculative": "1", 632f9900dd0SZhengjun Xing "UMask": "0xe4", 633f9900dd0SZhengjun Xing "Unit": "cpu_core" 634f9900dd0SZhengjun Xing }, 635f9900dd0SZhengjun Xing { 6365fa2481cSZhengjun Xing "BriefDescription": "Demand Data Read access L2 cache", 637f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 638f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 639f9900dd0SZhengjun Xing "EventCode": "0x24", 640f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 641f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 642f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6435fa2481cSZhengjun Xing "Speculative": "1", 644f9900dd0SZhengjun Xing "UMask": "0xe1", 645f9900dd0SZhengjun Xing "Unit": "cpu_core" 646f9900dd0SZhengjun Xing }, 647f9900dd0SZhengjun Xing { 648f9900dd0SZhengjun Xing "BriefDescription": "Demand requests that miss L2 cache", 649f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 650f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 651f9900dd0SZhengjun Xing "EventCode": "0x24", 652f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 653f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 654f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6555fa2481cSZhengjun Xing "Speculative": "1", 656f9900dd0SZhengjun Xing "UMask": "0x27", 657f9900dd0SZhengjun Xing "Unit": "cpu_core" 658f9900dd0SZhengjun Xing }, 659f9900dd0SZhengjun Xing { 6605fa2481cSZhengjun Xing "BriefDescription": "L2_RQSTS.ALL_HWPF", 6615fa2481cSZhengjun Xing "CollectPEBSRecord": "2", 6625fa2481cSZhengjun Xing "Counter": "0,1,2,3", 6635fa2481cSZhengjun Xing "EventCode": "0x24", 6645fa2481cSZhengjun Xing "EventName": "L2_RQSTS.ALL_HWPF", 6655fa2481cSZhengjun Xing "PEBScounters": "0,1,2,3", 6665fa2481cSZhengjun Xing "SampleAfterValue": "200003", 6675fa2481cSZhengjun Xing "Speculative": "1", 6685fa2481cSZhengjun Xing "UMask": "0xf0", 6695fa2481cSZhengjun Xing "Unit": "cpu_core" 6705fa2481cSZhengjun Xing }, 6715fa2481cSZhengjun Xing { 672f9900dd0SZhengjun Xing "BriefDescription": "RFO requests to L2 cache.", 673f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 674f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 675f9900dd0SZhengjun Xing "EventCode": "0x24", 676f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.ALL_RFO", 677f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 678f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6795fa2481cSZhengjun Xing "Speculative": "1", 680f9900dd0SZhengjun Xing "UMask": "0xe2", 681f9900dd0SZhengjun Xing "Unit": "cpu_core" 682f9900dd0SZhengjun Xing }, 683f9900dd0SZhengjun Xing { 684f9900dd0SZhengjun Xing "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 685f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 686f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 687f9900dd0SZhengjun Xing "EventCode": "0x24", 688f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.CODE_RD_HIT", 689f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 690f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 6915fa2481cSZhengjun Xing "Speculative": "1", 692f9900dd0SZhengjun Xing "UMask": "0xc4", 693f9900dd0SZhengjun Xing "Unit": "cpu_core" 694f9900dd0SZhengjun Xing }, 695f9900dd0SZhengjun Xing { 696f9900dd0SZhengjun Xing "BriefDescription": "L2 cache misses when fetching instructions", 697f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 698f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 699f9900dd0SZhengjun Xing "EventCode": "0x24", 700f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.CODE_RD_MISS", 701f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 702f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7035fa2481cSZhengjun Xing "Speculative": "1", 704f9900dd0SZhengjun Xing "UMask": "0x24", 705f9900dd0SZhengjun Xing "Unit": "cpu_core" 706f9900dd0SZhengjun Xing }, 707f9900dd0SZhengjun Xing { 708f9900dd0SZhengjun Xing "BriefDescription": "Demand Data Read requests that hit L2 cache", 709f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 710f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 711f9900dd0SZhengjun Xing "EventCode": "0x24", 712f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 713f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 714f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7155fa2481cSZhengjun Xing "Speculative": "1", 716f9900dd0SZhengjun Xing "UMask": "0xc1", 717f9900dd0SZhengjun Xing "Unit": "cpu_core" 718f9900dd0SZhengjun Xing }, 719f9900dd0SZhengjun Xing { 7205fa2481cSZhengjun Xing "BriefDescription": "Demand Data Read miss L2 cache", 721f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 722f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 723f9900dd0SZhengjun Xing "EventCode": "0x24", 724f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 725f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 726f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7275fa2481cSZhengjun Xing "Speculative": "1", 728f9900dd0SZhengjun Xing "UMask": "0x21", 729f9900dd0SZhengjun Xing "Unit": "cpu_core" 730f9900dd0SZhengjun Xing }, 731f9900dd0SZhengjun Xing { 7325fa2481cSZhengjun Xing "BriefDescription": "L2_RQSTS.HWPF_MISS", 7335fa2481cSZhengjun Xing "CollectPEBSRecord": "2", 7345fa2481cSZhengjun Xing "Counter": "0,1,2,3", 7355fa2481cSZhengjun Xing "EventCode": "0x24", 7365fa2481cSZhengjun Xing "EventName": "L2_RQSTS.HWPF_MISS", 7375fa2481cSZhengjun Xing "PEBScounters": "0,1,2,3", 7385fa2481cSZhengjun Xing "SampleAfterValue": "200003", 7395fa2481cSZhengjun Xing "Speculative": "1", 7405fa2481cSZhengjun Xing "UMask": "0x30", 7415fa2481cSZhengjun Xing "Unit": "cpu_core" 7425fa2481cSZhengjun Xing }, 7435fa2481cSZhengjun Xing { 744f9900dd0SZhengjun Xing "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", 745f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 746f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 747f9900dd0SZhengjun Xing "EventCode": "0x24", 748f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.MISS", 749f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 750f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7515fa2481cSZhengjun Xing "Speculative": "1", 752f9900dd0SZhengjun Xing "UMask": "0x3f", 753f9900dd0SZhengjun Xing "Unit": "cpu_core" 754f9900dd0SZhengjun Xing }, 755f9900dd0SZhengjun Xing { 7565fa2481cSZhengjun Xing "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]", 757f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 758f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 759f9900dd0SZhengjun Xing "EventCode": "0x24", 760f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.REFERENCES", 761f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 762f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7635fa2481cSZhengjun Xing "Speculative": "1", 764f9900dd0SZhengjun Xing "UMask": "0xff", 765f9900dd0SZhengjun Xing "Unit": "cpu_core" 766f9900dd0SZhengjun Xing }, 767f9900dd0SZhengjun Xing { 768f9900dd0SZhengjun Xing "BriefDescription": "RFO requests that hit L2 cache.", 769f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 770f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 771f9900dd0SZhengjun Xing "EventCode": "0x24", 772f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.RFO_HIT", 773f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 774f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7755fa2481cSZhengjun Xing "Speculative": "1", 776f9900dd0SZhengjun Xing "UMask": "0xc2", 777f9900dd0SZhengjun Xing "Unit": "cpu_core" 778f9900dd0SZhengjun Xing }, 779f9900dd0SZhengjun Xing { 780f9900dd0SZhengjun Xing "BriefDescription": "RFO requests that miss L2 cache", 781f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 782f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 783f9900dd0SZhengjun Xing "EventCode": "0x24", 784f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.RFO_MISS", 785f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 786f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7875fa2481cSZhengjun Xing "Speculative": "1", 788f9900dd0SZhengjun Xing "UMask": "0x22", 789f9900dd0SZhengjun Xing "Unit": "cpu_core" 790f9900dd0SZhengjun Xing }, 791f9900dd0SZhengjun Xing { 792f9900dd0SZhengjun Xing "BriefDescription": "SW prefetch requests that hit L2 cache.", 793f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 794f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 795f9900dd0SZhengjun Xing "EventCode": "0x24", 796f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.SWPF_HIT", 797f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 798f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 7995fa2481cSZhengjun Xing "Speculative": "1", 800f9900dd0SZhengjun Xing "UMask": "0xc8", 801f9900dd0SZhengjun Xing "Unit": "cpu_core" 802f9900dd0SZhengjun Xing }, 803f9900dd0SZhengjun Xing { 804f9900dd0SZhengjun Xing "BriefDescription": "SW prefetch requests that miss L2 cache.", 805f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 806f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 807f9900dd0SZhengjun Xing "EventCode": "0x24", 808f9900dd0SZhengjun Xing "EventName": "L2_RQSTS.SWPF_MISS", 809f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 810f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 8115fa2481cSZhengjun Xing "Speculative": "1", 812f9900dd0SZhengjun Xing "UMask": "0x28", 813f9900dd0SZhengjun Xing "Unit": "cpu_core" 814f9900dd0SZhengjun Xing }, 815f9900dd0SZhengjun Xing { 816a95ab294SIan Rogers "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 817f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 818f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 819f9900dd0SZhengjun Xing "EventCode": "0x2e", 820f9900dd0SZhengjun Xing "EventName": "LONGEST_LAT_CACHE.MISS", 821f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 822f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 8235fa2481cSZhengjun Xing "Speculative": "1", 824f9900dd0SZhengjun Xing "UMask": "0x41", 825f9900dd0SZhengjun Xing "Unit": "cpu_core" 826f9900dd0SZhengjun Xing }, 827f9900dd0SZhengjun Xing { 828a95ab294SIan Rogers "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 829a95ab294SIan Rogers "CollectPEBSRecord": "2", 830a95ab294SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 831a95ab294SIan Rogers "EventCode": "0x2e", 832a95ab294SIan Rogers "EventName": "LONGEST_LAT_CACHE.REFERENCE", 833a95ab294SIan Rogers "PEBScounters": "0,1,2,3,4,5,6,7", 834a95ab294SIan Rogers "SampleAfterValue": "100003", 835a95ab294SIan Rogers "Speculative": "1", 836a95ab294SIan Rogers "UMask": "0x4f", 837a95ab294SIan Rogers "Unit": "cpu_core" 838a95ab294SIan Rogers }, 839a95ab294SIan Rogers { 840a95ab294SIan Rogers "BriefDescription": "Retired load instructions.", 841f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 842f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 843f9900dd0SZhengjun Xing "Data_LA": "1", 844f9900dd0SZhengjun Xing "EventCode": "0xd0", 845f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.ALL_LOADS", 846f9900dd0SZhengjun Xing "PEBS": "1", 847f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 848f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 849f9900dd0SZhengjun Xing "UMask": "0x81", 850f9900dd0SZhengjun Xing "Unit": "cpu_core" 851f9900dd0SZhengjun Xing }, 852f9900dd0SZhengjun Xing { 853a95ab294SIan Rogers "BriefDescription": "Retired store instructions.", 854f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 855f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 856f9900dd0SZhengjun Xing "Data_LA": "1", 857f9900dd0SZhengjun Xing "EventCode": "0xd0", 858f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.ALL_STORES", 859f9900dd0SZhengjun Xing "L1_Hit_Indication": "1", 860f9900dd0SZhengjun Xing "PEBS": "1", 861f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 862f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 863f9900dd0SZhengjun Xing "UMask": "0x82", 864f9900dd0SZhengjun Xing "Unit": "cpu_core" 865f9900dd0SZhengjun Xing }, 866f9900dd0SZhengjun Xing { 867f9900dd0SZhengjun Xing "BriefDescription": "All retired memory instructions.", 868f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 869f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 870f9900dd0SZhengjun Xing "Data_LA": "1", 871f9900dd0SZhengjun Xing "EventCode": "0xd0", 872f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.ANY", 873f9900dd0SZhengjun Xing "L1_Hit_Indication": "1", 874f9900dd0SZhengjun Xing "PEBS": "1", 875f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 876f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 877f9900dd0SZhengjun Xing "UMask": "0x83", 878f9900dd0SZhengjun Xing "Unit": "cpu_core" 879f9900dd0SZhengjun Xing }, 880f9900dd0SZhengjun Xing { 881f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions with locked access.", 882f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 883f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 884f9900dd0SZhengjun Xing "Data_LA": "1", 885f9900dd0SZhengjun Xing "EventCode": "0xd0", 886f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.LOCK_LOADS", 887f9900dd0SZhengjun Xing "PEBS": "1", 888f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 889f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 890f9900dd0SZhengjun Xing "UMask": "0x21", 891f9900dd0SZhengjun Xing "Unit": "cpu_core" 892f9900dd0SZhengjun Xing }, 893f9900dd0SZhengjun Xing { 894f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions that split across a cacheline boundary.", 895f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 896f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 897f9900dd0SZhengjun Xing "Data_LA": "1", 898f9900dd0SZhengjun Xing "EventCode": "0xd0", 899f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", 900f9900dd0SZhengjun Xing "PEBS": "1", 901f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 902f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 903f9900dd0SZhengjun Xing "UMask": "0x41", 904f9900dd0SZhengjun Xing "Unit": "cpu_core" 905f9900dd0SZhengjun Xing }, 906f9900dd0SZhengjun Xing { 907f9900dd0SZhengjun Xing "BriefDescription": "Retired store instructions that split across a cacheline boundary.", 908f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 909f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 910f9900dd0SZhengjun Xing "Data_LA": "1", 911f9900dd0SZhengjun Xing "EventCode": "0xd0", 912f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.SPLIT_STORES", 913f9900dd0SZhengjun Xing "L1_Hit_Indication": "1", 914f9900dd0SZhengjun Xing "PEBS": "1", 915f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 916f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 917f9900dd0SZhengjun Xing "UMask": "0x42", 918f9900dd0SZhengjun Xing "Unit": "cpu_core" 919f9900dd0SZhengjun Xing }, 920f9900dd0SZhengjun Xing { 921f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions that miss the STLB.", 922f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 923f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 924f9900dd0SZhengjun Xing "Data_LA": "1", 925f9900dd0SZhengjun Xing "EventCode": "0xd0", 926f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", 927f9900dd0SZhengjun Xing "PEBS": "1", 928f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 929f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 930f9900dd0SZhengjun Xing "UMask": "0x11", 931f9900dd0SZhengjun Xing "Unit": "cpu_core" 932f9900dd0SZhengjun Xing }, 933f9900dd0SZhengjun Xing { 934f9900dd0SZhengjun Xing "BriefDescription": "Retired store instructions that miss the STLB.", 935f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 936f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 937f9900dd0SZhengjun Xing "Data_LA": "1", 938f9900dd0SZhengjun Xing "EventCode": "0xd0", 939f9900dd0SZhengjun Xing "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", 940f9900dd0SZhengjun Xing "L1_Hit_Indication": "1", 941f9900dd0SZhengjun Xing "PEBS": "1", 942f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 943f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 944f9900dd0SZhengjun Xing "UMask": "0x12", 945f9900dd0SZhengjun Xing "Unit": "cpu_core" 946f9900dd0SZhengjun Xing }, 947f9900dd0SZhengjun Xing { 948f9900dd0SZhengjun Xing "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 949f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 950f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 951f9900dd0SZhengjun Xing "EventCode": "0x43", 952f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", 953f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 954f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 9555fa2481cSZhengjun Xing "Speculative": "1", 956f9900dd0SZhengjun Xing "UMask": "0xfd", 957f9900dd0SZhengjun Xing "Unit": "cpu_core" 958f9900dd0SZhengjun Xing }, 959f9900dd0SZhengjun Xing { 960f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 961f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 962f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 963f9900dd0SZhengjun Xing "Data_LA": "1", 964f9900dd0SZhengjun Xing "EventCode": "0xd2", 965f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", 966f9900dd0SZhengjun Xing "PEBS": "1", 967f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 968f9900dd0SZhengjun Xing "SampleAfterValue": "20011", 969f9900dd0SZhengjun Xing "UMask": "0x4", 970f9900dd0SZhengjun Xing "Unit": "cpu_core" 971f9900dd0SZhengjun Xing }, 972f9900dd0SZhengjun Xing { 973f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 974f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 975f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 976f9900dd0SZhengjun Xing "Data_LA": "1", 977f9900dd0SZhengjun Xing "EventCode": "0xd2", 978f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 979f9900dd0SZhengjun Xing "PEBS": "1", 980f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 981f9900dd0SZhengjun Xing "SampleAfterValue": "20011", 982f9900dd0SZhengjun Xing "UMask": "0x2", 983f9900dd0SZhengjun Xing "Unit": "cpu_core" 984f9900dd0SZhengjun Xing }, 985f9900dd0SZhengjun Xing { 986f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 987f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 988f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 989f9900dd0SZhengjun Xing "Data_LA": "1", 990f9900dd0SZhengjun Xing "EventCode": "0xd2", 991f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 992f9900dd0SZhengjun Xing "PEBS": "1", 993f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 994f9900dd0SZhengjun Xing "SampleAfterValue": "20011", 995f9900dd0SZhengjun Xing "UMask": "0x4", 996f9900dd0SZhengjun Xing "Unit": "cpu_core" 997f9900dd0SZhengjun Xing }, 998f9900dd0SZhengjun Xing { 999f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 1000f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1001f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1002f9900dd0SZhengjun Xing "Data_LA": "1", 1003f9900dd0SZhengjun Xing "EventCode": "0xd2", 1004f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 1005f9900dd0SZhengjun Xing "PEBS": "1", 1006f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1007f9900dd0SZhengjun Xing "SampleAfterValue": "20011", 1008f9900dd0SZhengjun Xing "UMask": "0x1", 1009f9900dd0SZhengjun Xing "Unit": "cpu_core" 1010f9900dd0SZhengjun Xing }, 1011f9900dd0SZhengjun Xing { 1012f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", 1013f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1014f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1015f9900dd0SZhengjun Xing "Data_LA": "1", 1016f9900dd0SZhengjun Xing "EventCode": "0xd2", 1017f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 1018f9900dd0SZhengjun Xing "PEBS": "1", 1019f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1020f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 1021f9900dd0SZhengjun Xing "UMask": "0x8", 1022f9900dd0SZhengjun Xing "Unit": "cpu_core" 1023f9900dd0SZhengjun Xing }, 1024f9900dd0SZhengjun Xing { 1025f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 1026f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1027f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1028f9900dd0SZhengjun Xing "Data_LA": "1", 1029f9900dd0SZhengjun Xing "EventCode": "0xd2", 1030f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", 1031f9900dd0SZhengjun Xing "PEBS": "1", 1032f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1033f9900dd0SZhengjun Xing "SampleAfterValue": "20011", 1034f9900dd0SZhengjun Xing "UMask": "0x2", 1035f9900dd0SZhengjun Xing "Unit": "cpu_core" 1036f9900dd0SZhengjun Xing }, 1037f9900dd0SZhengjun Xing { 1038f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", 1039f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1040f9900dd0SZhengjun Xing "Data_LA": "1", 1041f9900dd0SZhengjun Xing "EventCode": "0xd3", 1042f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", 1043f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1044f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 1045f9900dd0SZhengjun Xing "UMask": "0x1", 1046f9900dd0SZhengjun Xing "Unit": "cpu_core" 1047f9900dd0SZhengjun Xing }, 1048f9900dd0SZhengjun Xing { 1049f9900dd0SZhengjun Xing "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", 1050f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1051f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1052f9900dd0SZhengjun Xing "Data_LA": "1", 1053f9900dd0SZhengjun Xing "EventCode": "0xd4", 1054f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_MISC_RETIRED.UC", 1055f9900dd0SZhengjun Xing "PEBS": "1", 1056f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1057f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 1058f9900dd0SZhengjun Xing "UMask": "0x4", 1059f9900dd0SZhengjun Xing "Unit": "cpu_core" 1060f9900dd0SZhengjun Xing }, 1061f9900dd0SZhengjun Xing { 1062f9900dd0SZhengjun Xing "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 1063f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1064f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1065f9900dd0SZhengjun Xing "Data_LA": "1", 1066f9900dd0SZhengjun Xing "EventCode": "0xd1", 1067f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.FB_HIT", 1068f9900dd0SZhengjun Xing "PEBS": "1", 1069f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1070f9900dd0SZhengjun Xing "SampleAfterValue": "100007", 1071f9900dd0SZhengjun Xing "UMask": "0x40", 1072f9900dd0SZhengjun Xing "Unit": "cpu_core" 1073f9900dd0SZhengjun Xing }, 1074f9900dd0SZhengjun Xing { 1075f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions with L1 cache hits as data sources", 1076f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1077f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1078f9900dd0SZhengjun Xing "Data_LA": "1", 1079f9900dd0SZhengjun Xing "EventCode": "0xd1", 1080f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.L1_HIT", 1081f9900dd0SZhengjun Xing "PEBS": "1", 1082f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1083f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 1084f9900dd0SZhengjun Xing "UMask": "0x1", 1085f9900dd0SZhengjun Xing "Unit": "cpu_core" 1086f9900dd0SZhengjun Xing }, 1087f9900dd0SZhengjun Xing { 1088f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions missed L1 cache as data sources", 1089f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1090f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1091f9900dd0SZhengjun Xing "Data_LA": "1", 1092f9900dd0SZhengjun Xing "EventCode": "0xd1", 1093f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.L1_MISS", 1094f9900dd0SZhengjun Xing "PEBS": "1", 1095f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1096f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 1097f9900dd0SZhengjun Xing "UMask": "0x8", 1098f9900dd0SZhengjun Xing "Unit": "cpu_core" 1099f9900dd0SZhengjun Xing }, 1100f9900dd0SZhengjun Xing { 1101f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions with L2 cache hits as data sources", 1102f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1103f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1104f9900dd0SZhengjun Xing "Data_LA": "1", 1105f9900dd0SZhengjun Xing "EventCode": "0xd1", 1106f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.L2_HIT", 1107f9900dd0SZhengjun Xing "PEBS": "1", 1108f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1109f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 1110f9900dd0SZhengjun Xing "UMask": "0x2", 1111f9900dd0SZhengjun Xing "Unit": "cpu_core" 1112f9900dd0SZhengjun Xing }, 1113f9900dd0SZhengjun Xing { 1114f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions missed L2 cache as data sources", 1115f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1116f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1117f9900dd0SZhengjun Xing "Data_LA": "1", 1118f9900dd0SZhengjun Xing "EventCode": "0xd1", 1119f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.L2_MISS", 1120f9900dd0SZhengjun Xing "PEBS": "1", 1121f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1122f9900dd0SZhengjun Xing "SampleAfterValue": "100021", 1123f9900dd0SZhengjun Xing "UMask": "0x10", 1124f9900dd0SZhengjun Xing "Unit": "cpu_core" 1125f9900dd0SZhengjun Xing }, 1126f9900dd0SZhengjun Xing { 1127f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions with L3 cache hits as data sources", 1128f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1129f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1130f9900dd0SZhengjun Xing "Data_LA": "1", 1131f9900dd0SZhengjun Xing "EventCode": "0xd1", 1132f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.L3_HIT", 1133f9900dd0SZhengjun Xing "PEBS": "1", 1134f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1135f9900dd0SZhengjun Xing "SampleAfterValue": "100021", 1136f9900dd0SZhengjun Xing "UMask": "0x4", 1137f9900dd0SZhengjun Xing "Unit": "cpu_core" 1138f9900dd0SZhengjun Xing }, 1139f9900dd0SZhengjun Xing { 1140f9900dd0SZhengjun Xing "BriefDescription": "Retired load instructions missed L3 cache as data sources", 1141f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1142f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1143f9900dd0SZhengjun Xing "Data_LA": "1", 1144f9900dd0SZhengjun Xing "EventCode": "0xd1", 1145f9900dd0SZhengjun Xing "EventName": "MEM_LOAD_RETIRED.L3_MISS", 1146f9900dd0SZhengjun Xing "PEBS": "1", 1147f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1148f9900dd0SZhengjun Xing "SampleAfterValue": "50021", 1149f9900dd0SZhengjun Xing "UMask": "0x20", 1150f9900dd0SZhengjun Xing "Unit": "cpu_core" 1151f9900dd0SZhengjun Xing }, 1152f9900dd0SZhengjun Xing { 11535fa2481cSZhengjun Xing "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", 1154f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1155f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1156f9900dd0SZhengjun Xing "EventCode": "0x44", 1157f9900dd0SZhengjun Xing "EventName": "MEM_STORE_RETIRED.L2_HIT", 1158f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1159f9900dd0SZhengjun Xing "SampleAfterValue": "200003", 1160f9900dd0SZhengjun Xing "UMask": "0x1", 1161f9900dd0SZhengjun Xing "Unit": "cpu_core" 1162f9900dd0SZhengjun Xing }, 1163f9900dd0SZhengjun Xing { 1164f9900dd0SZhengjun Xing "BriefDescription": "Retired memory uops for any access", 1165f9900dd0SZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 1166f9900dd0SZhengjun Xing "EventCode": "0xe5", 1167f9900dd0SZhengjun Xing "EventName": "MEM_UOP_RETIRED.ANY", 1168f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3,4,5,6,7", 1169f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 1170f9900dd0SZhengjun Xing "UMask": "0x3", 1171f9900dd0SZhengjun Xing "Unit": "cpu_core" 1172f9900dd0SZhengjun Xing }, 1173f9900dd0SZhengjun Xing { 1174f9900dd0SZhengjun Xing "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 11755fa2481cSZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 1176f9900dd0SZhengjun Xing "EventCode": "0x2A,0x2B", 1177f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 1178f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 1179f9900dd0SZhengjun Xing "MSRValue": "0x10003C0001", 1180f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 1181f9900dd0SZhengjun Xing "UMask": "0x1", 1182f9900dd0SZhengjun Xing "Unit": "cpu_core" 1183f9900dd0SZhengjun Xing }, 1184f9900dd0SZhengjun Xing { 11855fa2481cSZhengjun Xing "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 11865fa2481cSZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 1187f9900dd0SZhengjun Xing "EventCode": "0x2A,0x2B", 1188f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1189f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 1190f9900dd0SZhengjun Xing "MSRValue": "0x8003C0001", 1191f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 1192f9900dd0SZhengjun Xing "UMask": "0x1", 1193f9900dd0SZhengjun Xing "Unit": "cpu_core" 1194f9900dd0SZhengjun Xing }, 1195f9900dd0SZhengjun Xing { 1196f9900dd0SZhengjun Xing "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 11975fa2481cSZhengjun Xing "Counter": "0,1,2,3,4,5,6,7", 1198f9900dd0SZhengjun Xing "EventCode": "0x2A,0x2B", 1199f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 1200f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 1201f9900dd0SZhengjun Xing "MSRValue": "0x10003C0002", 1202f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 1203f9900dd0SZhengjun Xing "UMask": "0x1", 1204f9900dd0SZhengjun Xing "Unit": "cpu_core" 1205f9900dd0SZhengjun Xing }, 1206f9900dd0SZhengjun Xing { 12075fa2481cSZhengjun Xing "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", 1208f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1209f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1210f9900dd0SZhengjun Xing "EventCode": "0x21", 1211f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", 1212f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1213f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 12145fa2481cSZhengjun Xing "Speculative": "1", 1215f9900dd0SZhengjun Xing "UMask": "0x80", 1216f9900dd0SZhengjun Xing "Unit": "cpu_core" 1217f9900dd0SZhengjun Xing }, 1218f9900dd0SZhengjun Xing { 1219f9900dd0SZhengjun Xing "BriefDescription": "Demand and prefetch data reads", 1220f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1221f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1222f9900dd0SZhengjun Xing "EventCode": "0x21", 1223f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS.DATA_RD", 1224f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1225f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 12265fa2481cSZhengjun Xing "Speculative": "1", 1227f9900dd0SZhengjun Xing "UMask": "0x8", 1228f9900dd0SZhengjun Xing "Unit": "cpu_core" 1229f9900dd0SZhengjun Xing }, 1230f9900dd0SZhengjun Xing { 1231f9900dd0SZhengjun Xing "BriefDescription": "Demand Data Read requests sent to uncore", 1232f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1233f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1234f9900dd0SZhengjun Xing "EventCode": "0x21", 1235f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 1236f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1237f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 12385fa2481cSZhengjun Xing "Speculative": "1", 1239f9900dd0SZhengjun Xing "UMask": "0x1", 1240f9900dd0SZhengjun Xing "Unit": "cpu_core" 1241f9900dd0SZhengjun Xing }, 1242f9900dd0SZhengjun Xing { 1243f9900dd0SZhengjun Xing "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1244f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1245f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1246a95ab294SIan Rogers "Errata": "ADL038", 1247f9900dd0SZhengjun Xing "EventCode": "0x20", 1248f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 1249f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1250f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 12515fa2481cSZhengjun Xing "Speculative": "1", 1252f9900dd0SZhengjun Xing "UMask": "0x8", 1253f9900dd0SZhengjun Xing "Unit": "cpu_core" 1254f9900dd0SZhengjun Xing }, 1255f9900dd0SZhengjun Xing { 12565fa2481cSZhengjun Xing "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1257f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1258f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1259f9900dd0SZhengjun Xing "CounterMask": "1", 1260a95ab294SIan Rogers "Errata": "ADL038", 1261f9900dd0SZhengjun Xing "EventCode": "0x20", 1262f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 1263f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1264f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 12655fa2481cSZhengjun Xing "Speculative": "1", 1266f9900dd0SZhengjun Xing "UMask": "0x8", 1267f9900dd0SZhengjun Xing "Unit": "cpu_core" 1268f9900dd0SZhengjun Xing }, 1269f9900dd0SZhengjun Xing { 1270f9900dd0SZhengjun Xing "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", 1271f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1272f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1273f9900dd0SZhengjun Xing "CounterMask": "1", 1274f9900dd0SZhengjun Xing "EventCode": "0x20", 1275f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 1276f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1277f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 12785fa2481cSZhengjun Xing "Speculative": "1", 1279f9900dd0SZhengjun Xing "UMask": "0x4", 1280f9900dd0SZhengjun Xing "Unit": "cpu_core" 1281f9900dd0SZhengjun Xing }, 1282f9900dd0SZhengjun Xing { 12835fa2481cSZhengjun Xing "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1284f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1285f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1286a95ab294SIan Rogers "Errata": "ADL038", 1287f9900dd0SZhengjun Xing "EventCode": "0x20", 1288f9900dd0SZhengjun Xing "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", 1289f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1290f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 12915fa2481cSZhengjun Xing "Speculative": "1", 1292f9900dd0SZhengjun Xing "UMask": "0x8", 1293f9900dd0SZhengjun Xing "Unit": "cpu_core" 1294f9900dd0SZhengjun Xing }, 1295f9900dd0SZhengjun Xing { 1296f9900dd0SZhengjun Xing "BriefDescription": "Number of PREFETCHNTA instructions executed.", 1297f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1298f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1299f9900dd0SZhengjun Xing "EventCode": "0x40", 1300f9900dd0SZhengjun Xing "EventName": "SW_PREFETCH_ACCESS.NTA", 1301f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1302f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 13035fa2481cSZhengjun Xing "Speculative": "1", 1304f9900dd0SZhengjun Xing "UMask": "0x1", 1305f9900dd0SZhengjun Xing "Unit": "cpu_core" 1306f9900dd0SZhengjun Xing }, 1307f9900dd0SZhengjun Xing { 1308f9900dd0SZhengjun Xing "BriefDescription": "Number of PREFETCHW instructions executed.", 1309f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1310f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1311f9900dd0SZhengjun Xing "EventCode": "0x40", 1312f9900dd0SZhengjun Xing "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 1313f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1314f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 13155fa2481cSZhengjun Xing "Speculative": "1", 1316f9900dd0SZhengjun Xing "UMask": "0x8", 1317f9900dd0SZhengjun Xing "Unit": "cpu_core" 1318f9900dd0SZhengjun Xing }, 1319f9900dd0SZhengjun Xing { 1320f9900dd0SZhengjun Xing "BriefDescription": "Number of PREFETCHT0 instructions executed.", 1321f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1322f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1323f9900dd0SZhengjun Xing "EventCode": "0x40", 1324f9900dd0SZhengjun Xing "EventName": "SW_PREFETCH_ACCESS.T0", 1325f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1326f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 13275fa2481cSZhengjun Xing "Speculative": "1", 1328f9900dd0SZhengjun Xing "UMask": "0x2", 1329f9900dd0SZhengjun Xing "Unit": "cpu_core" 1330f9900dd0SZhengjun Xing }, 1331f9900dd0SZhengjun Xing { 1332f9900dd0SZhengjun Xing "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 1333f9900dd0SZhengjun Xing "CollectPEBSRecord": "2", 1334f9900dd0SZhengjun Xing "Counter": "0,1,2,3", 1335f9900dd0SZhengjun Xing "EventCode": "0x40", 1336f9900dd0SZhengjun Xing "EventName": "SW_PREFETCH_ACCESS.T1_T2", 1337f9900dd0SZhengjun Xing "PEBScounters": "0,1,2,3", 1338f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 13395fa2481cSZhengjun Xing "Speculative": "1", 1340f9900dd0SZhengjun Xing "UMask": "0x4", 1341f9900dd0SZhengjun Xing "Unit": "cpu_core" 1342f9900dd0SZhengjun Xing } 1343f9900dd0SZhengjun Xing] 1344