17f76b311SThomas Richter[ 27f76b311SThomas Richter { 37f76b311SThomas Richter "Unit": "CPU-M-CF", 47f76b311SThomas Richter "EventCode": "128", 57f76b311SThomas Richter "EventName": "L1D_RO_EXCL_WRITES", 67f76b311SThomas Richter "BriefDescription": "L1D Read-only Exclusive Writes", 77f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." 87f76b311SThomas Richter }, 97f76b311SThomas Richter { 107f76b311SThomas Richter "Unit": "CPU-M-CF", 117f76b311SThomas Richter "EventCode": "129", 127f76b311SThomas Richter "EventName": "DTLB2_WRITES", 137f76b311SThomas Richter "BriefDescription": "DTLB2 Writes", 147f76b311SThomas Richter "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines." 157f76b311SThomas Richter }, 167f76b311SThomas Richter { 177f76b311SThomas Richter "Unit": "CPU-M-CF", 187f76b311SThomas Richter "EventCode": "130", 197f76b311SThomas Richter "EventName": "DTLB2_MISSES", 207f76b311SThomas Richter "BriefDescription": "DTLB2 Misses", 217f76b311SThomas Richter "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines." 227f76b311SThomas Richter }, 237f76b311SThomas Richter { 247f76b311SThomas Richter "Unit": "CPU-M-CF", 257f76b311SThomas Richter "EventCode": "131", 267f76b311SThomas Richter "EventName": "CRSTE_1MB_WRITES", 277f76b311SThomas Richter "BriefDescription": "One Megabyte CRSTE writes", 287f76b311SThomas Richter "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page." 297f76b311SThomas Richter }, 307f76b311SThomas Richter { 317f76b311SThomas Richter "Unit": "CPU-M-CF", 327f76b311SThomas Richter "EventCode": "132", 337f76b311SThomas Richter "EventName": "DTLB2_GPAGE_WRITES", 347f76b311SThomas Richter "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 357f76b311SThomas Richter "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." 367f76b311SThomas Richter }, 377f76b311SThomas Richter { 387f76b311SThomas Richter "Unit": "CPU-M-CF", 397f76b311SThomas Richter "EventCode": "134", 407f76b311SThomas Richter "EventName": "ITLB2_WRITES", 417f76b311SThomas Richter "BriefDescription": "ITLB2 Writes", 427f76b311SThomas Richter "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines." 437f76b311SThomas Richter }, 447f76b311SThomas Richter { 457f76b311SThomas Richter "Unit": "CPU-M-CF", 467f76b311SThomas Richter "EventCode": "135", 477f76b311SThomas Richter "EventName": "ITLB2_MISSES", 487f76b311SThomas Richter "BriefDescription": "ITLB2 Misses", 497f76b311SThomas Richter "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines." 507f76b311SThomas Richter }, 517f76b311SThomas Richter { 527f76b311SThomas Richter "Unit": "CPU-M-CF", 537f76b311SThomas Richter "EventCode": "137", 547f76b311SThomas Richter "EventName": "TLB2_PTE_WRITES", 557f76b311SThomas Richter "BriefDescription": "TLB2 Page Table Entry Writes", 567f76b311SThomas Richter "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." 577f76b311SThomas Richter }, 587f76b311SThomas Richter { 597f76b311SThomas Richter "Unit": "CPU-M-CF", 607f76b311SThomas Richter "EventCode": "138", 617f76b311SThomas Richter "EventName": "TLB2_CRSTE_WRITES", 627f76b311SThomas Richter "BriefDescription": "TLB2 Combined Region and Segment Entry Writes", 637f76b311SThomas Richter "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." 647f76b311SThomas Richter }, 657f76b311SThomas Richter { 667f76b311SThomas Richter "Unit": "CPU-M-CF", 677f76b311SThomas Richter "EventCode": "139", 687f76b311SThomas Richter "EventName": "TLB2_ENGINES_BUSY", 697f76b311SThomas Richter "BriefDescription": "TLB2 Engines Busy", 707f76b311SThomas Richter "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." 717f76b311SThomas Richter }, 727f76b311SThomas Richter { 737f76b311SThomas Richter "Unit": "CPU-M-CF", 747f76b311SThomas Richter "EventCode": "140", 757f76b311SThomas Richter "EventName": "TX_C_TEND", 767f76b311SThomas Richter "BriefDescription": "Completed TEND instructions in constrained TX mode", 777f76b311SThomas Richter "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." 787f76b311SThomas Richter }, 797f76b311SThomas Richter { 807f76b311SThomas Richter "Unit": "CPU-M-CF", 817f76b311SThomas Richter "EventCode": "141", 827f76b311SThomas Richter "EventName": "TX_NC_TEND", 837f76b311SThomas Richter "BriefDescription": "Completed TEND instructions in non-constrained TX mode", 847f76b311SThomas Richter "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." 857f76b311SThomas Richter }, 867f76b311SThomas Richter { 877f76b311SThomas Richter "Unit": "CPU-M-CF", 887f76b311SThomas Richter "EventCode": "143", 897f76b311SThomas Richter "EventName": "L1C_TLB2_MISSES", 907f76b311SThomas Richter "BriefDescription": "L1C TLB2 Misses", 917f76b311SThomas Richter "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." 927f76b311SThomas Richter }, 937f76b311SThomas Richter { 947f76b311SThomas Richter "Unit": "CPU-M-CF", 957f76b311SThomas Richter "EventCode": "145", 967f76b311SThomas Richter "EventName": "DCW_REQ", 977f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache", 98*eb2feb68SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache." 997f76b311SThomas Richter }, 1007f76b311SThomas Richter { 1017f76b311SThomas Richter "Unit": "CPU-M-CF", 1027f76b311SThomas Richter "EventCode": "146", 1037f76b311SThomas Richter "EventName": "DCW_REQ_IV", 1047f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention", 105*eb2feb68SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention." 1067f76b311SThomas Richter }, 1077f76b311SThomas Richter { 1087f76b311SThomas Richter "Unit": "CPU-M-CF", 1097f76b311SThomas Richter "EventCode": "147", 1107f76b311SThomas Richter "EventName": "DCW_REQ_CHIP_HIT", 1117f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", 112*eb2feb68SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 1137f76b311SThomas Richter }, 1147f76b311SThomas Richter { 1157f76b311SThomas Richter "Unit": "CPU-M-CF", 1167f76b311SThomas Richter "EventCode": "148", 1177f76b311SThomas Richter "EventName": "DCW_REQ_DRAWER_HIT", 1187f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", 119*eb2feb68SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." 1207f76b311SThomas Richter }, 1217f76b311SThomas Richter { 1227f76b311SThomas Richter "Unit": "CPU-M-CF", 1237f76b311SThomas Richter "EventCode": "149", 1247f76b311SThomas Richter "EventName": "DCW_ON_CHIP", 1257f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache", 1267f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." 1277f76b311SThomas Richter }, 1287f76b311SThomas Richter { 1297f76b311SThomas Richter "Unit": "CPU-M-CF", 1307f76b311SThomas Richter "EventCode": "150", 1317f76b311SThomas Richter "EventName": "DCW_ON_CHIP_IV", 1327f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Intervention", 1337f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention." 1347f76b311SThomas Richter }, 1357f76b311SThomas Richter { 1367f76b311SThomas Richter "Unit": "CPU-M-CF", 1377f76b311SThomas Richter "EventCode": "151", 1387f76b311SThomas Richter "EventName": "DCW_ON_CHIP_CHIP_HIT", 1397f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit", 1407f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 1417f76b311SThomas Richter }, 1427f76b311SThomas Richter { 1437f76b311SThomas Richter "Unit": "CPU-M-CF", 1447f76b311SThomas Richter "EventCode": "152", 1457f76b311SThomas Richter "EventName": "DCW_ON_CHIP_DRAWER_HIT", 1467f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit", 1477f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 1487f76b311SThomas Richter }, 1497f76b311SThomas Richter { 1507f76b311SThomas Richter "Unit": "CPU-M-CF", 1517f76b311SThomas Richter "EventCode": "153", 1527f76b311SThomas Richter "EventName": "DCW_ON_MODULE", 1537f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Cache", 1547f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache." 1557f76b311SThomas Richter }, 1567f76b311SThomas Richter { 1577f76b311SThomas Richter "Unit": "CPU-M-CF", 1587f76b311SThomas Richter "EventCode": "154", 1597f76b311SThomas Richter "EventName": "DCW_ON_DRAWER", 1607f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Cache", 1617f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache." 1627f76b311SThomas Richter }, 1637f76b311SThomas Richter { 1647f76b311SThomas Richter "Unit": "CPU-M-CF", 1657f76b311SThomas Richter "EventCode": "155", 1667f76b311SThomas Richter "EventName": "DCW_OFF_DRAWER", 1677f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Cache", 1687f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache." 1697f76b311SThomas Richter }, 1707f76b311SThomas Richter { 1717f76b311SThomas Richter "Unit": "CPU-M-CF", 1727f76b311SThomas Richter "EventCode": "156", 1737f76b311SThomas Richter "EventName": "DCW_ON_CHIP_MEMORY", 1747f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory", 1757f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." 1767f76b311SThomas Richter }, 1777f76b311SThomas Richter { 1787f76b311SThomas Richter "Unit": "CPU-M-CF", 1797f76b311SThomas Richter "EventCode": "157", 1807f76b311SThomas Richter "EventName": "DCW_ON_MODULE_MEMORY", 1817f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory", 1827f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory." 1837f76b311SThomas Richter }, 1847f76b311SThomas Richter { 1857f76b311SThomas Richter "Unit": "CPU-M-CF", 1867f76b311SThomas Richter "EventCode": "158", 1877f76b311SThomas Richter "EventName": "DCW_ON_DRAWER_MEMORY", 1887f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory", 1897f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." 1907f76b311SThomas Richter }, 1917f76b311SThomas Richter { 1927f76b311SThomas Richter "Unit": "CPU-M-CF", 1937f76b311SThomas Richter "EventCode": "159", 1947f76b311SThomas Richter "EventName": "DCW_OFF_DRAWER_MEMORY", 1957f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory", 1967f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." 1977f76b311SThomas Richter }, 1987f76b311SThomas Richter { 1997f76b311SThomas Richter "Unit": "CPU-M-CF", 2007f76b311SThomas Richter "EventCode": "160", 2017f76b311SThomas Richter "EventName": "IDCW_ON_MODULE_IV", 2027f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention", 2037f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention." 2047f76b311SThomas Richter }, 2057f76b311SThomas Richter { 2067f76b311SThomas Richter "Unit": "CPU-M-CF", 2077f76b311SThomas Richter "EventCode": "161", 2087f76b311SThomas Richter "EventName": "IDCW_ON_MODULE_CHIP_HIT", 2097f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit", 2107f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." 2117f76b311SThomas Richter }, 2127f76b311SThomas Richter { 2137f76b311SThomas Richter "Unit": "CPU-M-CF", 2147f76b311SThomas Richter "EventCode": "162", 2157f76b311SThomas Richter "EventName": "IDCW_ON_MODULE_DRAWER_HIT", 2167f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit", 2177f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 2187f76b311SThomas Richter }, 2197f76b311SThomas Richter { 2207f76b311SThomas Richter "Unit": "CPU-M-CF", 2217f76b311SThomas Richter "EventCode": "163", 2227f76b311SThomas Richter "EventName": "IDCW_ON_DRAWER_IV", 2237f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention", 2247f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention." 2257f76b311SThomas Richter }, 2267f76b311SThomas Richter { 2277f76b311SThomas Richter "Unit": "CPU-M-CF", 2287f76b311SThomas Richter "EventCode": "164", 2297f76b311SThomas Richter "EventName": "IDCW_ON_DRAWER_CHIP_HIT", 2307f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit", 2317f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." 2327f76b311SThomas Richter }, 2337f76b311SThomas Richter { 2347f76b311SThomas Richter "Unit": "CPU-M-CF", 2357f76b311SThomas Richter "EventCode": "165", 2367f76b311SThomas Richter "EventName": "IDCW_ON_DRAWER_DRAWER_HIT", 2377f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit", 2387f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 2397f76b311SThomas Richter }, 2407f76b311SThomas Richter { 2417f76b311SThomas Richter "Unit": "CPU-M-CF", 2427f76b311SThomas Richter "EventCode": "166", 2437f76b311SThomas Richter "EventName": "IDCW_OFF_DRAWER_IV", 2447f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention", 2457f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention." 2467f76b311SThomas Richter }, 2477f76b311SThomas Richter { 2487f76b311SThomas Richter "Unit": "CPU-M-CF", 2497f76b311SThomas Richter "EventCode": "167", 2507f76b311SThomas Richter "EventName": "IDCW_OFF_DRAWER_CHIP_HIT", 2517f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit", 2527f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." 2537f76b311SThomas Richter }, 2547f76b311SThomas Richter { 2557f76b311SThomas Richter "Unit": "CPU-M-CF", 2567f76b311SThomas Richter "EventCode": "168", 2577f76b311SThomas Richter "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT", 2587f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit", 2597f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 2607f76b311SThomas Richter }, 2617f76b311SThomas Richter { 2627f76b311SThomas Richter "Unit": "CPU-M-CF", 2637f76b311SThomas Richter "EventCode": "169", 2647f76b311SThomas Richter "EventName": "ICW_REQ", 2657f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache", 2667f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache." 2677f76b311SThomas Richter }, 2687f76b311SThomas Richter { 2697f76b311SThomas Richter "Unit": "CPU-M-CF", 2707f76b311SThomas Richter "EventCode": "170", 2717f76b311SThomas Richter "EventName": "ICW_REQ_IV", 2727f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Intervention", 2737f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention." 2747f76b311SThomas Richter }, 2757f76b311SThomas Richter { 2767f76b311SThomas Richter "Unit": "CPU-M-CF", 2777f76b311SThomas Richter "EventCode": "171", 2787f76b311SThomas Richter "EventName": "ICW_REQ_CHIP_HIT", 2797f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit", 2807f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit." 2817f76b311SThomas Richter }, 2827f76b311SThomas Richter { 2837f76b311SThomas Richter "Unit": "CPU-M-CF", 2847f76b311SThomas Richter "EventCode": "172", 2857f76b311SThomas Richter "EventName": "ICW_REQ_DRAWER_HIT", 2867f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit", 287*eb2feb68SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 2887f76b311SThomas Richter }, 2897f76b311SThomas Richter { 2907f76b311SThomas Richter "Unit": "CPU-M-CF", 2917f76b311SThomas Richter "EventCode": "173", 2927f76b311SThomas Richter "EventName": "ICW_ON_CHIP", 2937f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache", 2947f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." 2957f76b311SThomas Richter }, 2967f76b311SThomas Richter { 2977f76b311SThomas Richter "Unit": "CPU-M-CF", 2987f76b311SThomas Richter "EventCode": "174", 2997f76b311SThomas Richter "EventName": "ICW_ON_CHIP_IV", 3007f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention", 3017f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention." 3027f76b311SThomas Richter }, 3037f76b311SThomas Richter { 3047f76b311SThomas Richter "Unit": "CPU-M-CF", 3057f76b311SThomas Richter "EventCode": "175", 3067f76b311SThomas Richter "EventName": "ICW_ON_CHIP_CHIP_HIT", 3077f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit", 3087f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit." 3097f76b311SThomas Richter }, 3107f76b311SThomas Richter { 3117f76b311SThomas Richter "Unit": "CPU-M-CF", 3127f76b311SThomas Richter "EventCode": "176", 3137f76b311SThomas Richter "EventName": "ICW_ON_CHIP_DRAWER_HIT", 3147f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit", 3157f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit." 3167f76b311SThomas Richter }, 3177f76b311SThomas Richter { 3187f76b311SThomas Richter "Unit": "CPU-M-CF", 3197f76b311SThomas Richter "EventCode": "177", 3207f76b311SThomas Richter "EventName": "ICW_ON_MODULE", 3217f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Cache", 3227f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache." 3237f76b311SThomas Richter }, 3247f76b311SThomas Richter { 3257f76b311SThomas Richter "Unit": "CPU-M-CF", 3267f76b311SThomas Richter "EventCode": "178", 3277f76b311SThomas Richter "EventName": "ICW_ON_DRAWER", 3287f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Cache", 3297f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache." 3307f76b311SThomas Richter }, 3317f76b311SThomas Richter { 3327f76b311SThomas Richter "Unit": "CPU-M-CF", 3337f76b311SThomas Richter "EventCode": "179", 3347f76b311SThomas Richter "EventName": "ICW_OFF_DRAWER", 3357f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Cache", 3367f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache." 3377f76b311SThomas Richter }, 3387f76b311SThomas Richter { 3397f76b311SThomas Richter "Unit": "CPU-M-CF", 3407f76b311SThomas Richter "EventCode": "180", 3417f76b311SThomas Richter "EventName": "ICW_ON_CHIP_MEMORY", 3427f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory", 3437f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." 3447f76b311SThomas Richter }, 3457f76b311SThomas Richter { 3467f76b311SThomas Richter "Unit": "CPU-M-CF", 3477f76b311SThomas Richter "EventCode": "181", 3487f76b311SThomas Richter "EventName": "ICW_ON_MODULE_MEMORY", 3497f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory", 3507f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory." 3517f76b311SThomas Richter }, 3527f76b311SThomas Richter { 3537f76b311SThomas Richter "Unit": "CPU-M-CF", 3547f76b311SThomas Richter "EventCode": "182", 3557f76b311SThomas Richter "EventName": "ICW_ON_DRAWER_MEMORY", 3567f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory", 3577f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." 3587f76b311SThomas Richter }, 3597f76b311SThomas Richter { 3607f76b311SThomas Richter "Unit": "CPU-M-CF", 3617f76b311SThomas Richter "EventCode": "183", 3627f76b311SThomas Richter "EventName": "ICW_OFF_DRAWER_MEMORY", 3637f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory", 3647f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." 3657f76b311SThomas Richter }, 3667f76b311SThomas Richter { 3677f76b311SThomas Richter "Unit": "CPU-M-CF", 3687f76b311SThomas Richter "EventCode": "224", 3697f76b311SThomas Richter "EventName": "BCD_DFP_EXECUTION_SLOTS", 3707f76b311SThomas Richter "BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions", 3717f76b311SThomas Richter "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." 3727f76b311SThomas Richter }, 3737f76b311SThomas Richter { 3747f76b311SThomas Richter "Unit": "CPU-M-CF", 3757f76b311SThomas Richter "EventCode": "225", 3767f76b311SThomas Richter "EventName": "VX_BCD_EXECUTION_SLOTS", 3777f76b311SThomas Richter "BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions", 3787f76b311SThomas Richter "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG." 3797f76b311SThomas Richter }, 3807f76b311SThomas Richter { 3817f76b311SThomas Richter "Unit": "CPU-M-CF", 3827f76b311SThomas Richter "EventCode": "226", 3837f76b311SThomas Richter "EventName": "DECIMAL_INSTRUCTIONS", 3847f76b311SThomas Richter "BriefDescription": "Decimal instruction dispatched", 3857f76b311SThomas Richter "PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." 3867f76b311SThomas Richter }, 3877f76b311SThomas Richter { 3887f76b311SThomas Richter "Unit": "CPU-M-CF", 3897f76b311SThomas Richter "EventCode": "232", 3907f76b311SThomas Richter "EventName": "LAST_HOST_TRANSLATIONS", 3917f76b311SThomas Richter "BriefDescription": "Last host translation done", 3927f76b311SThomas Richter "PublicDescription": "Last Host Translation done" 3937f76b311SThomas Richter }, 3947f76b311SThomas Richter { 3957f76b311SThomas Richter "Unit": "CPU-M-CF", 3967f76b311SThomas Richter "EventCode": "244", 3977f76b311SThomas Richter "EventName": "TX_NC_TABORT", 3987f76b311SThomas Richter "BriefDescription": "Aborted transactions in unconstrained TX mode", 3997f76b311SThomas Richter "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." 4007f76b311SThomas Richter }, 4017f76b311SThomas Richter { 4027f76b311SThomas Richter "Unit": "CPU-M-CF", 4037f76b311SThomas Richter "EventCode": "245", 4047f76b311SThomas Richter "EventName": "TX_C_TABORT_NO_SPECIAL", 4057f76b311SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode", 4067f76b311SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." 4077f76b311SThomas Richter }, 4087f76b311SThomas Richter { 4097f76b311SThomas Richter "Unit": "CPU-M-CF", 4107f76b311SThomas Richter "EventCode": "246", 4117f76b311SThomas Richter "EventName": "TX_C_TABORT_SPECIAL", 4127f76b311SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", 4137f76b311SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." 4147f76b311SThomas Richter }, 4157f76b311SThomas Richter { 4167f76b311SThomas Richter "Unit": "CPU-M-CF", 4177f76b311SThomas Richter "EventCode": "248", 4187f76b311SThomas Richter "EventName": "DFLT_ACCESS", 4197f76b311SThomas Richter "BriefDescription": "Cycles CPU spent obtaining access to Deflate unit", 4207f76b311SThomas Richter "PublicDescription": "Cycles CPU spent obtaining access to Deflate unit" 4217f76b311SThomas Richter }, 4227f76b311SThomas Richter { 4237f76b311SThomas Richter "Unit": "CPU-M-CF", 4247f76b311SThomas Richter "EventCode": "253", 4257f76b311SThomas Richter "EventName": "DFLT_CYCLES", 4267f76b311SThomas Richter "BriefDescription": "Cycles CPU is using Deflate unit", 4277f76b311SThomas Richter "PublicDescription": "Cycles CPU is using Deflate unit" 4287f76b311SThomas Richter }, 4297f76b311SThomas Richter { 4307f76b311SThomas Richter "Unit": "CPU-M-CF", 4317f76b311SThomas Richter "EventCode": "256", 4327f76b311SThomas Richter "EventName": "SORTL", 4337f76b311SThomas Richter "BriefDescription": "Count SORTL instructions", 4347f76b311SThomas Richter "PublicDescription": "Increments by one for every SORT LISTS instruction executed." 4357f76b311SThomas Richter }, 4367f76b311SThomas Richter { 4377f76b311SThomas Richter "Unit": "CPU-M-CF", 4387f76b311SThomas Richter "EventCode": "265", 4397f76b311SThomas Richter "EventName": "DFLT_CC", 4407f76b311SThomas Richter "BriefDescription": "Increments DEFLATE CONVERSION CALL", 4417f76b311SThomas Richter "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed." 4427f76b311SThomas Richter }, 4437f76b311SThomas Richter { 4447f76b311SThomas Richter "Unit": "CPU-M-CF", 4457f76b311SThomas Richter "EventCode": "266", 4467f76b311SThomas Richter "EventName": "DFLT_CCFINISH", 4477f76b311SThomas Richter "BriefDescription": "Increments completed DEFLATE CONVERSION CALL", 4487f76b311SThomas Richter "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2." 4497f76b311SThomas Richter }, 4507f76b311SThomas Richter { 4517f76b311SThomas Richter "Unit": "CPU-M-CF", 4527f76b311SThomas Richter "EventCode": "267", 4537f76b311SThomas Richter "EventName": "NNPA_INVOCATIONS", 4547f76b311SThomas Richter "BriefDescription": "NNPA Total invocations", 4557f76b311SThomas Richter "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed." 4567f76b311SThomas Richter }, 4577f76b311SThomas Richter { 4587f76b311SThomas Richter "Unit": "CPU-M-CF", 4597f76b311SThomas Richter "EventCode": "268", 4607f76b311SThomas Richter "EventName": "NNPA_COMPLETIONS", 4617f76b311SThomas Richter "BriefDescription": "NNPA Total completions", 4627f76b311SThomas Richter "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2." 4637f76b311SThomas Richter }, 4647f76b311SThomas Richter { 4657f76b311SThomas Richter "Unit": "CPU-M-CF", 4667f76b311SThomas Richter "EventCode": "269", 4677f76b311SThomas Richter "EventName": "NNPA_WAIT_LOCK", 4687f76b311SThomas Richter "BriefDescription": "Cycles spent obtaining NNPA lock", 4697f76b311SThomas Richter "PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI." 4707f76b311SThomas Richter }, 4717f76b311SThomas Richter { 4727f76b311SThomas Richter "Unit": "CPU-M-CF", 4737f76b311SThomas Richter "EventCode": "270", 4747f76b311SThomas Richter "EventName": "NNPA_HOLD_LOCK", 4757f76b311SThomas Richter "BriefDescription": "Cycles spent holding NNPA lock", 4767f76b311SThomas Richter "PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI." 4777f76b311SThomas Richter }, 4787f76b311SThomas Richter { 4797f76b311SThomas Richter "Unit": "CPU-M-CF", 4807f76b311SThomas Richter "EventCode": "448", 4817f76b311SThomas Richter "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE", 4827f76b311SThomas Richter "BriefDescription": "Cycle count with one thread active", 4837f76b311SThomas Richter "PublicDescription": "Cycle count with one thread active" 4847f76b311SThomas Richter }, 4857f76b311SThomas Richter { 4867f76b311SThomas Richter "Unit": "CPU-M-CF", 4877f76b311SThomas Richter "EventCode": "449", 4887f76b311SThomas Richter "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE", 4897f76b311SThomas Richter "BriefDescription": "Cycle count with two threads active", 4907f76b311SThomas Richter "PublicDescription": "Cycle count with two threads active" 4917f76b311SThomas Richter } 4927f76b311SThomas Richter] 493