1*7f76b311SThomas Richter[ 2*7f76b311SThomas Richter { 3*7f76b311SThomas Richter "Unit": "CPU-M-CF", 4*7f76b311SThomas Richter "EventCode": "128", 5*7f76b311SThomas Richter "EventName": "L1D_RO_EXCL_WRITES", 6*7f76b311SThomas Richter "BriefDescription": "L1D Read-only Exclusive Writes", 7*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." 8*7f76b311SThomas Richter }, 9*7f76b311SThomas Richter { 10*7f76b311SThomas Richter "Unit": "CPU-M-CF", 11*7f76b311SThomas Richter "EventCode": "129", 12*7f76b311SThomas Richter "EventName": "DTLB2_WRITES", 13*7f76b311SThomas Richter "BriefDescription": "DTLB2 Writes", 14*7f76b311SThomas Richter "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines." 15*7f76b311SThomas Richter }, 16*7f76b311SThomas Richter { 17*7f76b311SThomas Richter "Unit": "CPU-M-CF", 18*7f76b311SThomas Richter "EventCode": "130", 19*7f76b311SThomas Richter "EventName": "DTLB2_MISSES", 20*7f76b311SThomas Richter "BriefDescription": "DTLB2 Misses", 21*7f76b311SThomas Richter "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines." 22*7f76b311SThomas Richter }, 23*7f76b311SThomas Richter { 24*7f76b311SThomas Richter "Unit": "CPU-M-CF", 25*7f76b311SThomas Richter "EventCode": "131", 26*7f76b311SThomas Richter "EventName": "CRSTE_1MB_WRITES", 27*7f76b311SThomas Richter "BriefDescription": "One Megabyte CRSTE writes", 28*7f76b311SThomas Richter "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page." 29*7f76b311SThomas Richter }, 30*7f76b311SThomas Richter { 31*7f76b311SThomas Richter "Unit": "CPU-M-CF", 32*7f76b311SThomas Richter "EventCode": "132", 33*7f76b311SThomas Richter "EventName": "DTLB2_GPAGE_WRITES", 34*7f76b311SThomas Richter "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 35*7f76b311SThomas Richter "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." 36*7f76b311SThomas Richter }, 37*7f76b311SThomas Richter { 38*7f76b311SThomas Richter "Unit": "CPU-M-CF", 39*7f76b311SThomas Richter "EventCode": "134", 40*7f76b311SThomas Richter "EventName": "ITLB2_WRITES", 41*7f76b311SThomas Richter "BriefDescription": "ITLB2 Writes", 42*7f76b311SThomas Richter "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines." 43*7f76b311SThomas Richter }, 44*7f76b311SThomas Richter { 45*7f76b311SThomas Richter "Unit": "CPU-M-CF", 46*7f76b311SThomas Richter "EventCode": "135", 47*7f76b311SThomas Richter "EventName": "ITLB2_MISSES", 48*7f76b311SThomas Richter "BriefDescription": "ITLB2 Misses", 49*7f76b311SThomas Richter "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines." 50*7f76b311SThomas Richter }, 51*7f76b311SThomas Richter { 52*7f76b311SThomas Richter "Unit": "CPU-M-CF", 53*7f76b311SThomas Richter "EventCode": "137", 54*7f76b311SThomas Richter "EventName": "TLB2_PTE_WRITES", 55*7f76b311SThomas Richter "BriefDescription": "TLB2 Page Table Entry Writes", 56*7f76b311SThomas Richter "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." 57*7f76b311SThomas Richter }, 58*7f76b311SThomas Richter { 59*7f76b311SThomas Richter "Unit": "CPU-M-CF", 60*7f76b311SThomas Richter "EventCode": "138", 61*7f76b311SThomas Richter "EventName": "TLB2_CRSTE_WRITES", 62*7f76b311SThomas Richter "BriefDescription": "TLB2 Combined Region and Segment Entry Writes", 63*7f76b311SThomas Richter "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." 64*7f76b311SThomas Richter }, 65*7f76b311SThomas Richter { 66*7f76b311SThomas Richter "Unit": "CPU-M-CF", 67*7f76b311SThomas Richter "EventCode": "139", 68*7f76b311SThomas Richter "EventName": "TLB2_ENGINES_BUSY", 69*7f76b311SThomas Richter "BriefDescription": "TLB2 Engines Busy", 70*7f76b311SThomas Richter "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." 71*7f76b311SThomas Richter }, 72*7f76b311SThomas Richter { 73*7f76b311SThomas Richter "Unit": "CPU-M-CF", 74*7f76b311SThomas Richter "EventCode": "140", 75*7f76b311SThomas Richter "EventName": "TX_C_TEND", 76*7f76b311SThomas Richter "BriefDescription": "Completed TEND instructions in constrained TX mode", 77*7f76b311SThomas Richter "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." 78*7f76b311SThomas Richter }, 79*7f76b311SThomas Richter { 80*7f76b311SThomas Richter "Unit": "CPU-M-CF", 81*7f76b311SThomas Richter "EventCode": "141", 82*7f76b311SThomas Richter "EventName": "TX_NC_TEND", 83*7f76b311SThomas Richter "BriefDescription": "Completed TEND instructions in non-constrained TX mode", 84*7f76b311SThomas Richter "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." 85*7f76b311SThomas Richter }, 86*7f76b311SThomas Richter { 87*7f76b311SThomas Richter "Unit": "CPU-M-CF", 88*7f76b311SThomas Richter "EventCode": "143", 89*7f76b311SThomas Richter "EventName": "L1C_TLB2_MISSES", 90*7f76b311SThomas Richter "BriefDescription": "L1C TLB2 Misses", 91*7f76b311SThomas Richter "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." 92*7f76b311SThomas Richter }, 93*7f76b311SThomas Richter { 94*7f76b311SThomas Richter "Unit": "CPU-M-CF", 95*7f76b311SThomas Richter "EventCode": "145", 96*7f76b311SThomas Richter "EventName": "DCW_REQ", 97*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache", 98*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache." 99*7f76b311SThomas Richter }, 100*7f76b311SThomas Richter { 101*7f76b311SThomas Richter "Unit": "CPU-M-CF", 102*7f76b311SThomas Richter "EventCode": "146", 103*7f76b311SThomas Richter "EventName": "DCW_REQ_IV", 104*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention", 105*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention." 106*7f76b311SThomas Richter }, 107*7f76b311SThomas Richter { 108*7f76b311SThomas Richter "Unit": "CPU-M-CF", 109*7f76b311SThomas Richter "EventCode": "147", 110*7f76b311SThomas Richter "EventName": "DCW_REQ_CHIP_HIT", 111*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", 112*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 113*7f76b311SThomas Richter }, 114*7f76b311SThomas Richter { 115*7f76b311SThomas Richter "Unit": "CPU-M-CF", 116*7f76b311SThomas Richter "EventCode": "148", 117*7f76b311SThomas Richter "EventName": "DCW_REQ_DRAWER_HIT", 118*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", 119*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." 120*7f76b311SThomas Richter }, 121*7f76b311SThomas Richter { 122*7f76b311SThomas Richter "Unit": "CPU-M-CF", 123*7f76b311SThomas Richter "EventCode": "149", 124*7f76b311SThomas Richter "EventName": "DCW_ON_CHIP", 125*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache", 126*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." 127*7f76b311SThomas Richter }, 128*7f76b311SThomas Richter { 129*7f76b311SThomas Richter "Unit": "CPU-M-CF", 130*7f76b311SThomas Richter "EventCode": "150", 131*7f76b311SThomas Richter "EventName": "DCW_ON_CHIP_IV", 132*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Intervention", 133*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention." 134*7f76b311SThomas Richter }, 135*7f76b311SThomas Richter { 136*7f76b311SThomas Richter "Unit": "CPU-M-CF", 137*7f76b311SThomas Richter "EventCode": "151", 138*7f76b311SThomas Richter "EventName": "DCW_ON_CHIP_CHIP_HIT", 139*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit", 140*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." 141*7f76b311SThomas Richter }, 142*7f76b311SThomas Richter { 143*7f76b311SThomas Richter "Unit": "CPU-M-CF", 144*7f76b311SThomas Richter "EventCode": "152", 145*7f76b311SThomas Richter "EventName": "DCW_ON_CHIP_DRAWER_HIT", 146*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit", 147*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 148*7f76b311SThomas Richter }, 149*7f76b311SThomas Richter { 150*7f76b311SThomas Richter "Unit": "CPU-M-CF", 151*7f76b311SThomas Richter "EventCode": "153", 152*7f76b311SThomas Richter "EventName": "DCW_ON_MODULE", 153*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Cache", 154*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache." 155*7f76b311SThomas Richter }, 156*7f76b311SThomas Richter { 157*7f76b311SThomas Richter "Unit": "CPU-M-CF", 158*7f76b311SThomas Richter "EventCode": "154", 159*7f76b311SThomas Richter "EventName": "DCW_ON_DRAWER", 160*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Cache", 161*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache." 162*7f76b311SThomas Richter }, 163*7f76b311SThomas Richter { 164*7f76b311SThomas Richter "Unit": "CPU-M-CF", 165*7f76b311SThomas Richter "EventCode": "155", 166*7f76b311SThomas Richter "EventName": "DCW_OFF_DRAWER", 167*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Cache", 168*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache." 169*7f76b311SThomas Richter }, 170*7f76b311SThomas Richter { 171*7f76b311SThomas Richter "Unit": "CPU-M-CF", 172*7f76b311SThomas Richter "EventCode": "156", 173*7f76b311SThomas Richter "EventName": "DCW_ON_CHIP_MEMORY", 174*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory", 175*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." 176*7f76b311SThomas Richter }, 177*7f76b311SThomas Richter { 178*7f76b311SThomas Richter "Unit": "CPU-M-CF", 179*7f76b311SThomas Richter "EventCode": "157", 180*7f76b311SThomas Richter "EventName": "DCW_ON_MODULE_MEMORY", 181*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory", 182*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory." 183*7f76b311SThomas Richter }, 184*7f76b311SThomas Richter { 185*7f76b311SThomas Richter "Unit": "CPU-M-CF", 186*7f76b311SThomas Richter "EventCode": "158", 187*7f76b311SThomas Richter "EventName": "DCW_ON_DRAWER_MEMORY", 188*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory", 189*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." 190*7f76b311SThomas Richter }, 191*7f76b311SThomas Richter { 192*7f76b311SThomas Richter "Unit": "CPU-M-CF", 193*7f76b311SThomas Richter "EventCode": "159", 194*7f76b311SThomas Richter "EventName": "DCW_OFF_DRAWER_MEMORY", 195*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory", 196*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." 197*7f76b311SThomas Richter }, 198*7f76b311SThomas Richter { 199*7f76b311SThomas Richter "Unit": "CPU-M-CF", 200*7f76b311SThomas Richter "EventCode": "160", 201*7f76b311SThomas Richter "EventName": "IDCW_ON_MODULE_IV", 202*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention", 203*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention." 204*7f76b311SThomas Richter }, 205*7f76b311SThomas Richter { 206*7f76b311SThomas Richter "Unit": "CPU-M-CF", 207*7f76b311SThomas Richter "EventCode": "161", 208*7f76b311SThomas Richter "EventName": "IDCW_ON_MODULE_CHIP_HIT", 209*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit", 210*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." 211*7f76b311SThomas Richter }, 212*7f76b311SThomas Richter { 213*7f76b311SThomas Richter "Unit": "CPU-M-CF", 214*7f76b311SThomas Richter "EventCode": "162", 215*7f76b311SThomas Richter "EventName": "IDCW_ON_MODULE_DRAWER_HIT", 216*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit", 217*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 218*7f76b311SThomas Richter }, 219*7f76b311SThomas Richter { 220*7f76b311SThomas Richter "Unit": "CPU-M-CF", 221*7f76b311SThomas Richter "EventCode": "163", 222*7f76b311SThomas Richter "EventName": "IDCW_ON_DRAWER_IV", 223*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention", 224*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention." 225*7f76b311SThomas Richter }, 226*7f76b311SThomas Richter { 227*7f76b311SThomas Richter "Unit": "CPU-M-CF", 228*7f76b311SThomas Richter "EventCode": "164", 229*7f76b311SThomas Richter "EventName": "IDCW_ON_DRAWER_CHIP_HIT", 230*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit", 231*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." 232*7f76b311SThomas Richter }, 233*7f76b311SThomas Richter { 234*7f76b311SThomas Richter "Unit": "CPU-M-CF", 235*7f76b311SThomas Richter "EventCode": "165", 236*7f76b311SThomas Richter "EventName": "IDCW_ON_DRAWER_DRAWER_HIT", 237*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit", 238*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 239*7f76b311SThomas Richter }, 240*7f76b311SThomas Richter { 241*7f76b311SThomas Richter "Unit": "CPU-M-CF", 242*7f76b311SThomas Richter "EventCode": "166", 243*7f76b311SThomas Richter "EventName": "IDCW_OFF_DRAWER_IV", 244*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention", 245*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention." 246*7f76b311SThomas Richter }, 247*7f76b311SThomas Richter { 248*7f76b311SThomas Richter "Unit": "CPU-M-CF", 249*7f76b311SThomas Richter "EventCode": "167", 250*7f76b311SThomas Richter "EventName": "IDCW_OFF_DRAWER_CHIP_HIT", 251*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit", 252*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." 253*7f76b311SThomas Richter }, 254*7f76b311SThomas Richter { 255*7f76b311SThomas Richter "Unit": "CPU-M-CF", 256*7f76b311SThomas Richter "EventCode": "168", 257*7f76b311SThomas Richter "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT", 258*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit", 259*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 260*7f76b311SThomas Richter }, 261*7f76b311SThomas Richter { 262*7f76b311SThomas Richter "Unit": "CPU-M-CF", 263*7f76b311SThomas Richter "EventCode": "169", 264*7f76b311SThomas Richter "EventName": "ICW_REQ", 265*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache", 266*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache." 267*7f76b311SThomas Richter }, 268*7f76b311SThomas Richter { 269*7f76b311SThomas Richter "Unit": "CPU-M-CF", 270*7f76b311SThomas Richter "EventCode": "170", 271*7f76b311SThomas Richter "EventName": "ICW_REQ_IV", 272*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Intervention", 273*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention." 274*7f76b311SThomas Richter }, 275*7f76b311SThomas Richter { 276*7f76b311SThomas Richter "Unit": "CPU-M-CF", 277*7f76b311SThomas Richter "EventCode": "171", 278*7f76b311SThomas Richter "EventName": "ICW_REQ_CHIP_HIT", 279*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit", 280*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit." 281*7f76b311SThomas Richter }, 282*7f76b311SThomas Richter { 283*7f76b311SThomas Richter "Unit": "CPU-M-CF", 284*7f76b311SThomas Richter "EventCode": "172", 285*7f76b311SThomas Richter "EventName": "ICW_REQ_DRAWER_HIT", 286*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit", 287*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." 288*7f76b311SThomas Richter }, 289*7f76b311SThomas Richter { 290*7f76b311SThomas Richter "Unit": "CPU-M-CF", 291*7f76b311SThomas Richter "EventCode": "173", 292*7f76b311SThomas Richter "EventName": "ICW_ON_CHIP", 293*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache", 294*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." 295*7f76b311SThomas Richter }, 296*7f76b311SThomas Richter { 297*7f76b311SThomas Richter "Unit": "CPU-M-CF", 298*7f76b311SThomas Richter "EventCode": "174", 299*7f76b311SThomas Richter "EventName": "ICW_ON_CHIP_IV", 300*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention", 301*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention." 302*7f76b311SThomas Richter }, 303*7f76b311SThomas Richter { 304*7f76b311SThomas Richter "Unit": "CPU-M-CF", 305*7f76b311SThomas Richter "EventCode": "175", 306*7f76b311SThomas Richter "EventName": "ICW_ON_CHIP_CHIP_HIT", 307*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit", 308*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit." 309*7f76b311SThomas Richter }, 310*7f76b311SThomas Richter { 311*7f76b311SThomas Richter "Unit": "CPU-M-CF", 312*7f76b311SThomas Richter "EventCode": "176", 313*7f76b311SThomas Richter "EventName": "ICW_ON_CHIP_DRAWER_HIT", 314*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit", 315*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit." 316*7f76b311SThomas Richter }, 317*7f76b311SThomas Richter { 318*7f76b311SThomas Richter "Unit": "CPU-M-CF", 319*7f76b311SThomas Richter "EventCode": "177", 320*7f76b311SThomas Richter "EventName": "ICW_ON_MODULE", 321*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Cache", 322*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache." 323*7f76b311SThomas Richter }, 324*7f76b311SThomas Richter { 325*7f76b311SThomas Richter "Unit": "CPU-M-CF", 326*7f76b311SThomas Richter "EventCode": "178", 327*7f76b311SThomas Richter "EventName": "ICW_ON_DRAWER", 328*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Cache", 329*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache." 330*7f76b311SThomas Richter }, 331*7f76b311SThomas Richter { 332*7f76b311SThomas Richter "Unit": "CPU-M-CF", 333*7f76b311SThomas Richter "EventCode": "179", 334*7f76b311SThomas Richter "EventName": "ICW_OFF_DRAWER", 335*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Cache", 336*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache." 337*7f76b311SThomas Richter }, 338*7f76b311SThomas Richter { 339*7f76b311SThomas Richter "Unit": "CPU-M-CF", 340*7f76b311SThomas Richter "EventCode": "180", 341*7f76b311SThomas Richter "EventName": "ICW_ON_CHIP_MEMORY", 342*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory", 343*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." 344*7f76b311SThomas Richter }, 345*7f76b311SThomas Richter { 346*7f76b311SThomas Richter "Unit": "CPU-M-CF", 347*7f76b311SThomas Richter "EventCode": "181", 348*7f76b311SThomas Richter "EventName": "ICW_ON_MODULE_MEMORY", 349*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory", 350*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory." 351*7f76b311SThomas Richter }, 352*7f76b311SThomas Richter { 353*7f76b311SThomas Richter "Unit": "CPU-M-CF", 354*7f76b311SThomas Richter "EventCode": "182", 355*7f76b311SThomas Richter "EventName": "ICW_ON_DRAWER_MEMORY", 356*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory", 357*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." 358*7f76b311SThomas Richter }, 359*7f76b311SThomas Richter { 360*7f76b311SThomas Richter "Unit": "CPU-M-CF", 361*7f76b311SThomas Richter "EventCode": "183", 362*7f76b311SThomas Richter "EventName": "ICW_OFF_DRAWER_MEMORY", 363*7f76b311SThomas Richter "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory", 364*7f76b311SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." 365*7f76b311SThomas Richter }, 366*7f76b311SThomas Richter { 367*7f76b311SThomas Richter "Unit": "CPU-M-CF", 368*7f76b311SThomas Richter "EventCode": "224", 369*7f76b311SThomas Richter "EventName": "BCD_DFP_EXECUTION_SLOTS", 370*7f76b311SThomas Richter "BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions", 371*7f76b311SThomas Richter "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." 372*7f76b311SThomas Richter }, 373*7f76b311SThomas Richter { 374*7f76b311SThomas Richter "Unit": "CPU-M-CF", 375*7f76b311SThomas Richter "EventCode": "225", 376*7f76b311SThomas Richter "EventName": "VX_BCD_EXECUTION_SLOTS", 377*7f76b311SThomas Richter "BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions", 378*7f76b311SThomas Richter "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG." 379*7f76b311SThomas Richter }, 380*7f76b311SThomas Richter { 381*7f76b311SThomas Richter "Unit": "CPU-M-CF", 382*7f76b311SThomas Richter "EventCode": "226", 383*7f76b311SThomas Richter "EventName": "DECIMAL_INSTRUCTIONS", 384*7f76b311SThomas Richter "BriefDescription": "Decimal instruction dispatched", 385*7f76b311SThomas Richter "PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." 386*7f76b311SThomas Richter }, 387*7f76b311SThomas Richter { 388*7f76b311SThomas Richter "Unit": "CPU-M-CF", 389*7f76b311SThomas Richter "EventCode": "232", 390*7f76b311SThomas Richter "EventName": "LAST_HOST_TRANSLATIONS", 391*7f76b311SThomas Richter "BriefDescription": "Last host translation done", 392*7f76b311SThomas Richter "PublicDescription": "Last Host Translation done" 393*7f76b311SThomas Richter }, 394*7f76b311SThomas Richter { 395*7f76b311SThomas Richter "Unit": "CPU-M-CF", 396*7f76b311SThomas Richter "EventCode": "244", 397*7f76b311SThomas Richter "EventName": "TX_NC_TABORT", 398*7f76b311SThomas Richter "BriefDescription": "Aborted transactions in unconstrained TX mode", 399*7f76b311SThomas Richter "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." 400*7f76b311SThomas Richter }, 401*7f76b311SThomas Richter { 402*7f76b311SThomas Richter "Unit": "CPU-M-CF", 403*7f76b311SThomas Richter "EventCode": "245", 404*7f76b311SThomas Richter "EventName": "TX_C_TABORT_NO_SPECIAL", 405*7f76b311SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode", 406*7f76b311SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." 407*7f76b311SThomas Richter }, 408*7f76b311SThomas Richter { 409*7f76b311SThomas Richter "Unit": "CPU-M-CF", 410*7f76b311SThomas Richter "EventCode": "246", 411*7f76b311SThomas Richter "EventName": "TX_C_TABORT_SPECIAL", 412*7f76b311SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", 413*7f76b311SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." 414*7f76b311SThomas Richter }, 415*7f76b311SThomas Richter { 416*7f76b311SThomas Richter "Unit": "CPU-M-CF", 417*7f76b311SThomas Richter "EventCode": "248", 418*7f76b311SThomas Richter "EventName": "DFLT_ACCESS", 419*7f76b311SThomas Richter "BriefDescription": "Cycles CPU spent obtaining access to Deflate unit", 420*7f76b311SThomas Richter "PublicDescription": "Cycles CPU spent obtaining access to Deflate unit" 421*7f76b311SThomas Richter }, 422*7f76b311SThomas Richter { 423*7f76b311SThomas Richter "Unit": "CPU-M-CF", 424*7f76b311SThomas Richter "EventCode": "253", 425*7f76b311SThomas Richter "EventName": "DFLT_CYCLES", 426*7f76b311SThomas Richter "BriefDescription": "Cycles CPU is using Deflate unit", 427*7f76b311SThomas Richter "PublicDescription": "Cycles CPU is using Deflate unit" 428*7f76b311SThomas Richter }, 429*7f76b311SThomas Richter { 430*7f76b311SThomas Richter "Unit": "CPU-M-CF", 431*7f76b311SThomas Richter "EventCode": "256", 432*7f76b311SThomas Richter "EventName": "SORTL", 433*7f76b311SThomas Richter "BriefDescription": "Count SORTL instructions", 434*7f76b311SThomas Richter "PublicDescription": "Increments by one for every SORT LISTS instruction executed." 435*7f76b311SThomas Richter }, 436*7f76b311SThomas Richter { 437*7f76b311SThomas Richter "Unit": "CPU-M-CF", 438*7f76b311SThomas Richter "EventCode": "265", 439*7f76b311SThomas Richter "EventName": "DFLT_CC", 440*7f76b311SThomas Richter "BriefDescription": "Increments DEFLATE CONVERSION CALL", 441*7f76b311SThomas Richter "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed." 442*7f76b311SThomas Richter }, 443*7f76b311SThomas Richter { 444*7f76b311SThomas Richter "Unit": "CPU-M-CF", 445*7f76b311SThomas Richter "EventCode": "266", 446*7f76b311SThomas Richter "EventName": "DFLT_CCFINISH", 447*7f76b311SThomas Richter "BriefDescription": "Increments completed DEFLATE CONVERSION CALL", 448*7f76b311SThomas Richter "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2." 449*7f76b311SThomas Richter }, 450*7f76b311SThomas Richter { 451*7f76b311SThomas Richter "Unit": "CPU-M-CF", 452*7f76b311SThomas Richter "EventCode": "267", 453*7f76b311SThomas Richter "EventName": "NNPA_INVOCATIONS", 454*7f76b311SThomas Richter "BriefDescription": "NNPA Total invocations", 455*7f76b311SThomas Richter "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed." 456*7f76b311SThomas Richter }, 457*7f76b311SThomas Richter { 458*7f76b311SThomas Richter "Unit": "CPU-M-CF", 459*7f76b311SThomas Richter "EventCode": "268", 460*7f76b311SThomas Richter "EventName": "NNPA_COMPLETIONS", 461*7f76b311SThomas Richter "BriefDescription": "NNPA Total completions", 462*7f76b311SThomas Richter "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2." 463*7f76b311SThomas Richter }, 464*7f76b311SThomas Richter { 465*7f76b311SThomas Richter "Unit": "CPU-M-CF", 466*7f76b311SThomas Richter "EventCode": "269", 467*7f76b311SThomas Richter "EventName": "NNPA_WAIT_LOCK", 468*7f76b311SThomas Richter "BriefDescription": "Cycles spent obtaining NNPA lock", 469*7f76b311SThomas Richter "PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI." 470*7f76b311SThomas Richter }, 471*7f76b311SThomas Richter { 472*7f76b311SThomas Richter "Unit": "CPU-M-CF", 473*7f76b311SThomas Richter "EventCode": "270", 474*7f76b311SThomas Richter "EventName": "NNPA_HOLD_LOCK", 475*7f76b311SThomas Richter "BriefDescription": "Cycles spent holding NNPA lock", 476*7f76b311SThomas Richter "PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI." 477*7f76b311SThomas Richter }, 478*7f76b311SThomas Richter { 479*7f76b311SThomas Richter "Unit": "CPU-M-CF", 480*7f76b311SThomas Richter "EventCode": "448", 481*7f76b311SThomas Richter "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE", 482*7f76b311SThomas Richter "BriefDescription": "Cycle count with one thread active", 483*7f76b311SThomas Richter "PublicDescription": "Cycle count with one thread active" 484*7f76b311SThomas Richter }, 485*7f76b311SThomas Richter { 486*7f76b311SThomas Richter "Unit": "CPU-M-CF", 487*7f76b311SThomas Richter "EventCode": "449", 488*7f76b311SThomas Richter "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE", 489*7f76b311SThomas Richter "BriefDescription": "Cycle count with two threads active", 490*7f76b311SThomas Richter "PublicDescription": "Cycle count with two threads active" 491*7f76b311SThomas Richter } 492*7f76b311SThomas Richter] 493