10d0e5eceSThomas Richter[ 20d0e5eceSThomas Richter { 30d0e5eceSThomas Richter "BriefDescription": "Transaction count", 40d0e5eceSThomas Richter "MetricName": "transaction", 50d0e5eceSThomas Richter "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" 674395567SThomas Richter }, 774395567SThomas Richter { 874395567SThomas Richter "BriefDescription": "Cycles per Instruction", 974395567SThomas Richter "MetricName": "cpi", 1074395567SThomas Richter "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" 1174395567SThomas Richter }, 1274395567SThomas Richter { 1374395567SThomas Richter "BriefDescription": "Problem State Instruction Ratio", 1474395567SThomas Richter "MetricName": "prbstate", 1574395567SThomas Richter "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" 1674395567SThomas Richter }, 1774395567SThomas Richter { 1874395567SThomas Richter "BriefDescription": "Level One Miss per 100 Instructions", 1974395567SThomas Richter "MetricName": "l1mp", 2074395567SThomas Richter "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" 21bdecfecaSThomas Richter }, 22bdecfecaSThomas Richter { 23bdecfecaSThomas Richter "BriefDescription": "Percentage sourced from Level 2 cache", 24bdecfecaSThomas Richter "MetricName": "l2p", 25bdecfecaSThomas Richter "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" 26bdecfecaSThomas Richter }, 27bdecfecaSThomas Richter { 28bdecfecaSThomas Richter "BriefDescription": "Percentage sourced from Level 3 on same chip cache", 29bdecfecaSThomas Richter "MetricName": "l3p", 30bdecfecaSThomas Richter "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" 31bdecfecaSThomas Richter }, 32bdecfecaSThomas Richter { 33bdecfecaSThomas Richter "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", 34bdecfecaSThomas Richter "MetricName": "l4lp", 35bdecfecaSThomas Richter "MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" 36bdecfecaSThomas Richter }, 37bdecfecaSThomas Richter { 38bdecfecaSThomas Richter "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", 39bdecfecaSThomas Richter "MetricName": "l4rp", 40bdecfecaSThomas Richter "MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" 41bdecfecaSThomas Richter }, 42bdecfecaSThomas Richter { 43bdecfecaSThomas Richter "BriefDescription": "Percentage sourced from memory", 44bdecfecaSThomas Richter "MetricName": "memp", 45bdecfecaSThomas Richter "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" 46*4c290d4fSThomas Richter }, 47*4c290d4fSThomas Richter { 48*4c290d4fSThomas Richter "BriefDescription": "Cycles per Instructions from Finite cache/memory", 49*4c290d4fSThomas Richter "MetricName": "finite_cpi", 50*4c290d4fSThomas Richter "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" 51*4c290d4fSThomas Richter }, 52*4c290d4fSThomas Richter { 53*4c290d4fSThomas Richter "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", 54*4c290d4fSThomas Richter "MetricName": "est_cpi", 55*4c290d4fSThomas Richter "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" 56*4c290d4fSThomas Richter }, 57*4c290d4fSThomas Richter { 58*4c290d4fSThomas Richter "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", 59*4c290d4fSThomas Richter "MetricName": "scpl1m", 60*4c290d4fSThomas Richter "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" 61*4c290d4fSThomas Richter }, 62*4c290d4fSThomas Richter { 63*4c290d4fSThomas Richter "BriefDescription": "Estimated TLB CPU percentage of Total CPU", 64*4c290d4fSThomas Richter "MetricName": "tlb_percent", 65*4c290d4fSThomas Richter "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" 66*4c290d4fSThomas Richter }, 67*4c290d4fSThomas Richter { 68*4c290d4fSThomas Richter "BriefDescription": "Estimated Cycles per TLB Miss", 69*4c290d4fSThomas Richter "MetricName": "tlb_miss", 70*4c290d4fSThomas Richter "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" 710d0e5eceSThomas Richter } 720d0e5eceSThomas Richter] 73