10d0e5eceSThomas Richter[
20d0e5eceSThomas Richter	{
30d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
40d0e5eceSThomas Richter		"EventCode": "0",
50d0e5eceSThomas Richter		"EventName": "CPU_CYCLES",
60d0e5eceSThomas Richter		"BriefDescription": "CPU Cycles",
70d0e5eceSThomas Richter		"PublicDescription": "Cycle Count"
80d0e5eceSThomas Richter	},
90d0e5eceSThomas Richter	{
100d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
110d0e5eceSThomas Richter		"EventCode": "1",
120d0e5eceSThomas Richter		"EventName": "INSTRUCTIONS",
130d0e5eceSThomas Richter		"BriefDescription": "Instructions",
140d0e5eceSThomas Richter		"PublicDescription": "Instruction Count"
150d0e5eceSThomas Richter	},
160d0e5eceSThomas Richter	{
170d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
180d0e5eceSThomas Richter		"EventCode": "2",
190d0e5eceSThomas Richter		"EventName": "L1I_DIR_WRITES",
200d0e5eceSThomas Richter		"BriefDescription": "L1I Directory Writes",
210d0e5eceSThomas Richter		"PublicDescription": "Level-1 I-Cache Directory Write Count"
220d0e5eceSThomas Richter	},
230d0e5eceSThomas Richter	{
240d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
250d0e5eceSThomas Richter		"EventCode": "3",
260d0e5eceSThomas Richter		"EventName": "L1I_PENALTY_CYCLES",
270d0e5eceSThomas Richter		"BriefDescription": "L1I Penalty Cycles",
280d0e5eceSThomas Richter		"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
290d0e5eceSThomas Richter	},
300d0e5eceSThomas Richter	{
310d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
320d0e5eceSThomas Richter		"EventCode": "4",
330d0e5eceSThomas Richter		"EventName": "L1D_DIR_WRITES",
340d0e5eceSThomas Richter		"BriefDescription": "L1D Directory Writes",
350d0e5eceSThomas Richter		"PublicDescription": "Level-1 D-Cache Directory Write Count"
360d0e5eceSThomas Richter	},
370d0e5eceSThomas Richter	{
380d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
390d0e5eceSThomas Richter		"EventCode": "5",
400d0e5eceSThomas Richter		"EventName": "L1D_PENALTY_CYCLES",
410d0e5eceSThomas Richter		"BriefDescription": "L1D Penalty Cycles",
420d0e5eceSThomas Richter		"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
430d0e5eceSThomas Richter	},
440d0e5eceSThomas Richter	{
450d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
460d0e5eceSThomas Richter		"EventCode": "32",
470d0e5eceSThomas Richter		"EventName": "PROBLEM_STATE_CPU_CYCLES",
480d0e5eceSThomas Richter		"BriefDescription": "Problem-State CPU Cycles",
490d0e5eceSThomas Richter		"PublicDescription": "Problem-State Cycle Count"
500d0e5eceSThomas Richter	},
510d0e5eceSThomas Richter	{
520d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
530d0e5eceSThomas Richter		"EventCode": "33",
540d0e5eceSThomas Richter		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
550d0e5eceSThomas Richter		"BriefDescription": "Problem-State Instructions",
560d0e5eceSThomas Richter		"PublicDescription": "Problem-State Instruction Count"
570d0e5eceSThomas Richter	},
580d0e5eceSThomas Richter]
59