1cfbb9be8SThomas Richter[ 2cfbb9be8SThomas Richter { 39bacbcedSThomas Richter "Unit": "CPU-M-CF", 4cfbb9be8SThomas Richter "EventCode": "128", 5cfbb9be8SThomas Richter "EventName": "L1I_L2_SOURCED_WRITES", 6cfbb9be8SThomas Richter "BriefDescription": "L1I L2 Sourced Writes", 7cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache" 8cfbb9be8SThomas Richter }, 9cfbb9be8SThomas Richter { 109bacbcedSThomas Richter "Unit": "CPU-M-CF", 11cfbb9be8SThomas Richter "EventCode": "129", 12cfbb9be8SThomas Richter "EventName": "L1D_L2_SOURCED_WRITES", 13cfbb9be8SThomas Richter "BriefDescription": "L1D L2 Sourced Writes", 14cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache" 15cfbb9be8SThomas Richter }, 16cfbb9be8SThomas Richter { 179bacbcedSThomas Richter "Unit": "CPU-M-CF", 18cfbb9be8SThomas Richter "EventCode": "130", 19cfbb9be8SThomas Richter "EventName": "L1I_L3_LOCAL_WRITES", 20cfbb9be8SThomas Richter "BriefDescription": "L1I L3 Local Writes", 21cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)" 22cfbb9be8SThomas Richter }, 23cfbb9be8SThomas Richter { 249bacbcedSThomas Richter "Unit": "CPU-M-CF", 25cfbb9be8SThomas Richter "EventCode": "131", 26cfbb9be8SThomas Richter "EventName": "L1D_L3_LOCAL_WRITES", 27cfbb9be8SThomas Richter "BriefDescription": "L1D L3 Local Writes", 28cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)" 29cfbb9be8SThomas Richter }, 30cfbb9be8SThomas Richter { 319bacbcedSThomas Richter "Unit": "CPU-M-CF", 32cfbb9be8SThomas Richter "EventCode": "132", 33cfbb9be8SThomas Richter "EventName": "L1I_L3_REMOTE_WRITES", 34cfbb9be8SThomas Richter "BriefDescription": "L1I L3 Remote Writes", 35cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)" 36cfbb9be8SThomas Richter }, 37cfbb9be8SThomas Richter { 389bacbcedSThomas Richter "Unit": "CPU-M-CF", 39cfbb9be8SThomas Richter "EventCode": "133", 40cfbb9be8SThomas Richter "EventName": "L1D_L3_REMOTE_WRITES", 41cfbb9be8SThomas Richter "BriefDescription": "L1D L3 Remote Writes", 42cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)" 43cfbb9be8SThomas Richter }, 44cfbb9be8SThomas Richter { 459bacbcedSThomas Richter "Unit": "CPU-M-CF", 46cfbb9be8SThomas Richter "EventCode": "134", 47cfbb9be8SThomas Richter "EventName": "L1D_LMEM_SOURCED_WRITES", 48cfbb9be8SThomas Richter "BriefDescription": "L1D Local Memory Sourced Writes", 49cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" 50cfbb9be8SThomas Richter }, 51cfbb9be8SThomas Richter { 529bacbcedSThomas Richter "Unit": "CPU-M-CF", 53cfbb9be8SThomas Richter "EventCode": "135", 54cfbb9be8SThomas Richter "EventName": "L1I_LMEM_SOURCED_WRITES", 55cfbb9be8SThomas Richter "BriefDescription": "L1I Local Memory Sourced Writes", 56cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)" 57cfbb9be8SThomas Richter }, 58cfbb9be8SThomas Richter { 599bacbcedSThomas Richter "Unit": "CPU-M-CF", 60cfbb9be8SThomas Richter "EventCode": "136", 61cfbb9be8SThomas Richter "EventName": "L1D_RO_EXCL_WRITES", 62cfbb9be8SThomas Richter "BriefDescription": "L1D Read-only Exclusive Writes", 63cfbb9be8SThomas Richter "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" 64cfbb9be8SThomas Richter }, 65cfbb9be8SThomas Richter { 669bacbcedSThomas Richter "Unit": "CPU-M-CF", 67cfbb9be8SThomas Richter "EventCode": "137", 68cfbb9be8SThomas Richter "EventName": "L1I_CACHELINE_INVALIDATES", 69cfbb9be8SThomas Richter "BriefDescription": "L1I Cacheline Invalidates", 70cfbb9be8SThomas Richter "PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache" 71cfbb9be8SThomas Richter }, 72cfbb9be8SThomas Richter { 739bacbcedSThomas Richter "Unit": "CPU-M-CF", 74cfbb9be8SThomas Richter "EventCode": "138", 75cfbb9be8SThomas Richter "EventName": "ITLB1_WRITES", 76cfbb9be8SThomas Richter "BriefDescription": "ITLB1 Writes", 77cfbb9be8SThomas Richter "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer" 78cfbb9be8SThomas Richter }, 79cfbb9be8SThomas Richter { 809bacbcedSThomas Richter "Unit": "CPU-M-CF", 81cfbb9be8SThomas Richter "EventCode": "139", 82cfbb9be8SThomas Richter "EventName": "DTLB1_WRITES", 83cfbb9be8SThomas Richter "BriefDescription": "DTLB1 Writes", 84cfbb9be8SThomas Richter "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" 85cfbb9be8SThomas Richter }, 86cfbb9be8SThomas Richter { 879bacbcedSThomas Richter "Unit": "CPU-M-CF", 88cfbb9be8SThomas Richter "EventCode": "140", 89cfbb9be8SThomas Richter "EventName": "TLB2_PTE_WRITES", 90cfbb9be8SThomas Richter "BriefDescription": "TLB2 PTE Writes", 91cfbb9be8SThomas Richter "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" 92cfbb9be8SThomas Richter }, 93cfbb9be8SThomas Richter { 949bacbcedSThomas Richter "Unit": "CPU-M-CF", 95cfbb9be8SThomas Richter "EventCode": "141", 96cfbb9be8SThomas Richter "EventName": "TLB2_CRSTE_WRITES", 97cfbb9be8SThomas Richter "BriefDescription": "TLB2 CRSTE Writes", 98cfbb9be8SThomas Richter "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" 99cfbb9be8SThomas Richter }, 100cfbb9be8SThomas Richter { 1019bacbcedSThomas Richter "Unit": "CPU-M-CF", 102cfbb9be8SThomas Richter "EventCode": "142", 103cfbb9be8SThomas Richter "EventName": "TLB2_CRSTE_HPAGE_WRITES", 104cfbb9be8SThomas Richter "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", 105cfbb9be8SThomas Richter "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" 106cfbb9be8SThomas Richter }, 107cfbb9be8SThomas Richter { 1089bacbcedSThomas Richter "Unit": "CPU-M-CF", 109cfbb9be8SThomas Richter "EventCode": "145", 110cfbb9be8SThomas Richter "EventName": "ITLB1_MISSES", 111cfbb9be8SThomas Richter "BriefDescription": "ITLB1 Misses", 112cfbb9be8SThomas Richter "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress" 113cfbb9be8SThomas Richter }, 114cfbb9be8SThomas Richter { 1159bacbcedSThomas Richter "Unit": "CPU-M-CF", 116cfbb9be8SThomas Richter "EventCode": "146", 117cfbb9be8SThomas Richter "EventName": "DTLB1_MISSES", 118cfbb9be8SThomas Richter "BriefDescription": "DTLB1 Misses", 119cfbb9be8SThomas Richter "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress" 120cfbb9be8SThomas Richter }, 121cfbb9be8SThomas Richter { 1229bacbcedSThomas Richter "Unit": "CPU-M-CF", 123cfbb9be8SThomas Richter "EventCode": "147", 124cfbb9be8SThomas Richter "EventName": "L2C_STORES_SENT", 125cfbb9be8SThomas Richter "BriefDescription": "L2C Stores Sent", 126cfbb9be8SThomas Richter "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache" 127cfbb9be8SThomas Richter }, 128cfbb9be8SThomas Richter] 129