1826db0f1SSukadev Bhattiprolu[ 2826db0f1SSukadev Bhattiprolu {, 33c22ba52SSukadev Bhattiprolu "EventCode": "0x3084", 43c22ba52SSukadev Bhattiprolu "EventName": "PM_ISU1_ISS_HOLD_ALL", 53c22ba52SSukadev Bhattiprolu "BriefDescription": "All ISU rejects" 6826db0f1SSukadev Bhattiprolu }, 7826db0f1SSukadev Bhattiprolu {, 83c22ba52SSukadev Bhattiprolu "EventCode": "0xF880", 93c22ba52SSukadev Bhattiprolu "EventName": "PM_SNOOP_TLBIE", 103c22ba52SSukadev Bhattiprolu "BriefDescription": "TLBIE snoop" 11826db0f1SSukadev Bhattiprolu }, 12826db0f1SSukadev Bhattiprolu {, 133c22ba52SSukadev Bhattiprolu "EventCode": "0x4088", 143c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_DEMAND_REQ", 153c22ba52SSukadev Bhattiprolu "BriefDescription": "Demand Instruction fetch request" 16826db0f1SSukadev Bhattiprolu }, 17826db0f1SSukadev Bhattiprolu {, 183c22ba52SSukadev Bhattiprolu "EventCode": "0x20A4", 193c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_TRESUME", 203c22ba52SSukadev Bhattiprolu "BriefDescription": "TM resume instruction completed" 21826db0f1SSukadev Bhattiprolu }, 22826db0f1SSukadev Bhattiprolu {, 23826db0f1SSukadev Bhattiprolu "EventCode": "0x40008", 24826db0f1SSukadev Bhattiprolu "EventName": "PM_SRQ_EMPTY_CYC", 253c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice" 26826db0f1SSukadev Bhattiprolu }, 27826db0f1SSukadev Bhattiprolu {, 283c22ba52SSukadev Bhattiprolu "EventCode": "0x20064", 293c22ba52SSukadev Bhattiprolu "EventName": "PM_IERAT_RELOAD_4K", 303c22ba52SSukadev Bhattiprolu "BriefDescription": "IERAT reloaded (after a miss) for 4K pages" 31826db0f1SSukadev Bhattiprolu }, 32826db0f1SSukadev Bhattiprolu {, 333c22ba52SSukadev Bhattiprolu "EventCode": "0x260B4", 343c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P2_LCO_RTY", 353c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)" 36826db0f1SSukadev Bhattiprolu }, 37826db0f1SSukadev Bhattiprolu {, 383c22ba52SSukadev Bhattiprolu "EventCode": "0x20006", 393c22ba52SSukadev Bhattiprolu "EventName": "PM_DISP_HELD_ISSQ_FULL", 403c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue" 41826db0f1SSukadev Bhattiprolu }, 42826db0f1SSukadev Bhattiprolu {, 433c22ba52SSukadev Bhattiprolu "EventCode": "0x201E4", 443c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3MISS", 453c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load" 46826db0f1SSukadev Bhattiprolu }, 47826db0f1SSukadev Bhattiprolu {, 48826db0f1SSukadev Bhattiprolu "EventCode": "0x4E044", 493c22ba52SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_L31_ECO_MOD", 503c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 51826db0f1SSukadev Bhattiprolu }, 52826db0f1SSukadev Bhattiprolu {, 533c22ba52SSukadev Bhattiprolu "EventCode": "0x40B8", 543c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_MPRED_TAKEN_CR", 553c22ba52SSukadev Bhattiprolu "BriefDescription": "A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction)." 56826db0f1SSukadev Bhattiprolu }, 57826db0f1SSukadev Bhattiprolu {, 583c22ba52SSukadev Bhattiprolu "EventCode": "0xF8AC", 593c22ba52SSukadev Bhattiprolu "EventName": "PM_DC_DEALLOC_NO_CONF", 603c22ba52SSukadev Bhattiprolu "BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)" 61826db0f1SSukadev Bhattiprolu }, 62826db0f1SSukadev Bhattiprolu {, 633c22ba52SSukadev Bhattiprolu "EventCode": "0xD090", 643c22ba52SSukadev Bhattiprolu "EventName": "PM_LS0_DC_COLLISIONS", 653c22ba52SSukadev Bhattiprolu "BriefDescription": "Read-write data cache collisions" 66826db0f1SSukadev Bhattiprolu }, 67826db0f1SSukadev Bhattiprolu {, 683c22ba52SSukadev Bhattiprolu "EventCode": "0x40BC", 693c22ba52SSukadev Bhattiprolu "EventName": "PM_THRD_PRIO_0_1_CYC", 703c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles thread running at priority level 0 or 1" 71826db0f1SSukadev Bhattiprolu }, 72826db0f1SSukadev Bhattiprolu {, 739749adc3SSukadev Bhattiprolu "EventCode": "0x4C054", 749749adc3SSukadev Bhattiprolu "EventName": "PM_DERAT_MISS_16G_1G", 759749adc3SSukadev Bhattiprolu "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode)" 769749adc3SSukadev Bhattiprolu }, 779749adc3SSukadev Bhattiprolu {, 783c22ba52SSukadev Bhattiprolu "EventCode": "0x2084", 793c22ba52SSukadev Bhattiprolu "EventName": "PM_FLUSH_HB_RESTORE_CYC", 803c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery" 81826db0f1SSukadev Bhattiprolu }, 82826db0f1SSukadev Bhattiprolu {, 83826db0f1SSukadev Bhattiprolu "EventCode": "0x4F054", 84826db0f1SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_MISS", 853c22ba52SSukadev Bhattiprolu "BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cache." 86826db0f1SSukadev Bhattiprolu }, 87826db0f1SSukadev Bhattiprolu {, 88e795dd42SSukadev Bhattiprolu "EventCode": "0x26882", 89e795dd42SSukadev Bhattiprolu "EventName": "PM_L2_DC_INV", 90e795dd42SSukadev Bhattiprolu "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 91e795dd42SSukadev Bhattiprolu }, 92e795dd42SSukadev Bhattiprolu {, 933c22ba52SSukadev Bhattiprolu "EventCode": "0x24048", 943c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_FROM_LMEM", 953c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)" 963c22ba52SSukadev Bhattiprolu }, 973c22ba52SSukadev Bhattiprolu {, 983c22ba52SSukadev Bhattiprolu "EventCode": "0xD8B4", 993c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_LRQ_S0_VALID_CYC", 1003c22ba52SSukadev Bhattiprolu "BriefDescription": "Slot 0 of LRQ valid" 1013c22ba52SSukadev Bhattiprolu }, 1023c22ba52SSukadev Bhattiprolu {, 1033c22ba52SSukadev Bhattiprolu "EventCode": "0x2E052", 1043c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_PASSED", 1053c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of TM transactions that passed" 1063c22ba52SSukadev Bhattiprolu }, 1073c22ba52SSukadev Bhattiprolu {, 1083c22ba52SSukadev Bhattiprolu "EventCode": "0xF088", 1093c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_STORE_REJECT", 1103c22ba52SSukadev Bhattiprolu "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" 1113c22ba52SSukadev Bhattiprolu }, 1123c22ba52SSukadev Bhattiprolu {, 1133c22ba52SSukadev Bhattiprolu "EventCode": "0x360B2", 1143c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_GRP_GUESS_WRONG_LOW", 1159749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS" 1163c22ba52SSukadev Bhattiprolu }, 1173c22ba52SSukadev Bhattiprolu {, 1183c22ba52SSukadev Bhattiprolu "EventCode": "0x168A6", 1193c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_CAM_OVERFLOW", 1209749adc3SSukadev Bhattiprolu "BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory" 1213c22ba52SSukadev Bhattiprolu }, 1223c22ba52SSukadev Bhattiprolu {, 1233c22ba52SSukadev Bhattiprolu "EventCode": "0xE8B0", 1243c22ba52SSukadev Bhattiprolu "EventName": "PM_TEND_PEND_CYC", 1253c22ba52SSukadev Bhattiprolu "BriefDescription": "TEND latency per thread" 1263c22ba52SSukadev Bhattiprolu }, 1273c22ba52SSukadev Bhattiprolu {, 1283c22ba52SSukadev Bhattiprolu "EventCode": "0x4884", 1293c22ba52SSukadev Bhattiprolu "EventName": "PM_IBUF_FULL_CYC", 1303c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles No room in ibuff" 1313c22ba52SSukadev Bhattiprolu }, 1323c22ba52SSukadev Bhattiprolu {, 1333c22ba52SSukadev Bhattiprolu "EventCode": "0xD08C", 1343c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_LDMX_FIN", 135e795dd42SSukadev Bhattiprolu "BriefDescription": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])." 1363c22ba52SSukadev Bhattiprolu }, 1373c22ba52SSukadev Bhattiprolu {, 1383c22ba52SSukadev Bhattiprolu "EventCode": "0x300F8", 1393c22ba52SSukadev Bhattiprolu "EventName": "PM_TB_BIT_TRANS", 1403c22ba52SSukadev Bhattiprolu "BriefDescription": "timebase event" 1413c22ba52SSukadev Bhattiprolu }, 1423c22ba52SSukadev Bhattiprolu {, 1433c22ba52SSukadev Bhattiprolu "EventCode": "0x3C040", 1443c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", 1453c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load" 1463c22ba52SSukadev Bhattiprolu }, 1473c22ba52SSukadev Bhattiprolu {, 1483c22ba52SSukadev Bhattiprolu "EventCode": "0xE0BC", 1493c22ba52SSukadev Bhattiprolu "EventName": "PM_LS0_PTE_TABLEWALK_CYC", 1503c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles when a tablewalk is pending on this thread on table 0" 1513c22ba52SSukadev Bhattiprolu }, 1523c22ba52SSukadev Bhattiprolu {, 1533c22ba52SSukadev Bhattiprolu "EventCode": "0x3884", 1543c22ba52SSukadev Bhattiprolu "EventName": "PM_ISU3_ISS_HOLD_ALL", 1553c22ba52SSukadev Bhattiprolu "BriefDescription": "All ISU rejects" 1563c22ba52SSukadev Bhattiprolu }, 1573c22ba52SSukadev Bhattiprolu {, 1583c22ba52SSukadev Bhattiprolu "EventCode": "0x468A0", 1593c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF_OFF_CHIP_MEM", 1603c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF from Off chip memory" 1613c22ba52SSukadev Bhattiprolu }, 1623c22ba52SSukadev Bhattiprolu {, 1633c22ba52SSukadev Bhattiprolu "EventCode": "0x268AA", 1643c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_LCO_DATA", 1653c22ba52SSukadev Bhattiprolu "BriefDescription": "LCO sent with data port 1" 1663c22ba52SSukadev Bhattiprolu }, 1673c22ba52SSukadev Bhattiprolu {, 1683c22ba52SSukadev Bhattiprolu "EventCode": "0xE894", 1693c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU1_TM_L1_HIT", 1703c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm hit in L1" 1713c22ba52SSukadev Bhattiprolu }, 1723c22ba52SSukadev Bhattiprolu {, 1733c22ba52SSukadev Bhattiprolu "EventCode": "0x5888", 1743c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_INVALIDATE", 1753c22ba52SSukadev Bhattiprolu "BriefDescription": "Ic line invalidated" 1763c22ba52SSukadev Bhattiprolu }, 1773c22ba52SSukadev Bhattiprolu {, 1783c22ba52SSukadev Bhattiprolu "EventCode": "0x2890", 1793c22ba52SSukadev Bhattiprolu "EventName": "PM_DISP_CLB_HELD_TLBIE", 1803c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch Hold: Due to TLBIE" 1813c22ba52SSukadev Bhattiprolu }, 1823c22ba52SSukadev Bhattiprolu {, 1833c22ba52SSukadev Bhattiprolu "EventCode": "0x1001C", 1843c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_THRD", 1853c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion Stalled because the thread was blocked" 1863c22ba52SSukadev Bhattiprolu }, 1873c22ba52SSukadev Bhattiprolu {, 1883c22ba52SSukadev Bhattiprolu "EventCode": "0x368A6", 1893c22ba52SSukadev Bhattiprolu "EventName": "PM_SNP_TM_HIT_T", 1909749adc3SSukadev Bhattiprolu "BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified)" 1913c22ba52SSukadev Bhattiprolu }, 1923c22ba52SSukadev Bhattiprolu {, 1933c22ba52SSukadev Bhattiprolu "EventCode": "0x3001A", 1943c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_TABLEWALK_CYC", 1953c22ba52SSukadev Bhattiprolu "BriefDescription": "Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches." 1963c22ba52SSukadev Bhattiprolu }, 1973c22ba52SSukadev Bhattiprolu {, 1983c22ba52SSukadev Bhattiprolu "EventCode": "0xD894", 1993c22ba52SSukadev Bhattiprolu "EventName": "PM_LS3_DC_COLLISIONS", 2003c22ba52SSukadev Bhattiprolu "BriefDescription": "Read-write data cache collisions" 2013c22ba52SSukadev Bhattiprolu }, 2023c22ba52SSukadev Bhattiprolu {, 2033c22ba52SSukadev Bhattiprolu "EventCode": "0x35158", 2043c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC", 2053c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load" 2063c22ba52SSukadev Bhattiprolu }, 2073c22ba52SSukadev Bhattiprolu {, 2089749adc3SSukadev Bhattiprolu "EventCode": "0xF0B4", 2099749adc3SSukadev Bhattiprolu "EventName": "PM_DC_PREF_CONS_ALLOC", 2109749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase" 2119749adc3SSukadev Bhattiprolu }, 2129749adc3SSukadev Bhattiprolu {, 2133c22ba52SSukadev Bhattiprolu "EventCode": "0xF894", 2143c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_L1_CAM_CANCEL", 2153c22ba52SSukadev Bhattiprolu "BriefDescription": "ls3 l1 tm cam cancel" 2163c22ba52SSukadev Bhattiprolu }, 2173c22ba52SSukadev Bhattiprolu {, 2183c22ba52SSukadev Bhattiprolu "EventCode": "0x2888", 2193c22ba52SSukadev Bhattiprolu "EventName": "PM_FLUSH_DISP_TLBIE", 2203c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch Flush: TLBIE" 2213c22ba52SSukadev Bhattiprolu }, 2223c22ba52SSukadev Bhattiprolu {, 2233c22ba52SSukadev Bhattiprolu "EventCode": "0x4E11E", 2243c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DMEM_CYC", 2253c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load" 2263c22ba52SSukadev Bhattiprolu }, 2273c22ba52SSukadev Bhattiprolu {, 2283c22ba52SSukadev Bhattiprolu "EventCode": "0x14156", 2293c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_CYC", 2303c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load" 2313c22ba52SSukadev Bhattiprolu }, 2323c22ba52SSukadev Bhattiprolu {, 2333c22ba52SSukadev Bhattiprolu "EventCode": "0x468A6", 2343c22ba52SSukadev Bhattiprolu "EventName": "PM_RD_CLEARING_SC", 2359749adc3SSukadev Bhattiprolu "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated" 2369749adc3SSukadev Bhattiprolu }, 2379749adc3SSukadev Bhattiprolu {, 2389749adc3SSukadev Bhattiprolu "EventCode": "0xD0B0", 2399749adc3SSukadev Bhattiprolu "EventName": "PM_HWSYNC", 240123a039dSMichael Petlan "BriefDescription": "A hwsync instruction was decoded and transferred" 2413c22ba52SSukadev Bhattiprolu }, 2423c22ba52SSukadev Bhattiprolu {, 2433c22ba52SSukadev Bhattiprolu "EventCode": "0x168B0", 2443c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_NODE_PUMP", 2453c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests" 2463c22ba52SSukadev Bhattiprolu }, 2473c22ba52SSukadev Bhattiprolu {, 2483c22ba52SSukadev Bhattiprolu "EventCode": "0xD0BC", 2493c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_1_LRQF_FULL_CYC", 2503c22ba52SSukadev Bhattiprolu "BriefDescription": "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ" 2513c22ba52SSukadev Bhattiprolu }, 2523c22ba52SSukadev Bhattiprolu {, 2533c22ba52SSukadev Bhattiprolu "EventCode": "0x2D148", 2543c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", 2553c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load" 2563c22ba52SSukadev Bhattiprolu }, 2573c22ba52SSukadev Bhattiprolu {, 258e795dd42SSukadev Bhattiprolu "EventCode": "0x468AE", 259e795dd42SSukadev Bhattiprolu "EventName": "PM_L3_P3_CO_RTY", 260e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted" 261e795dd42SSukadev Bhattiprolu }, 262e795dd42SSukadev Bhattiprolu {, 2633c22ba52SSukadev Bhattiprolu "EventCode": "0x460A8", 2643c22ba52SSukadev Bhattiprolu "EventName": "PM_SN_HIT", 2653c22ba52SSukadev Bhattiprolu "BriefDescription": "Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1" 2663c22ba52SSukadev Bhattiprolu }, 2673c22ba52SSukadev Bhattiprolu {, 2683c22ba52SSukadev Bhattiprolu "EventCode": "0x360AA", 2693c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_CO_MEM", 2703c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO to memory port 0 with or without data" 2713c22ba52SSukadev Bhattiprolu }, 2723c22ba52SSukadev Bhattiprolu {, 2733c22ba52SSukadev Bhattiprolu "EventCode": "0xF0A4", 2743c22ba52SSukadev Bhattiprolu "EventName": "PM_DC_PREF_HW_ALLOC", 2753c22ba52SSukadev Bhattiprolu "BriefDescription": "Prefetch stream allocated by the hardware prefetch mechanism" 2763c22ba52SSukadev Bhattiprolu }, 2773c22ba52SSukadev Bhattiprolu {, 2789749adc3SSukadev Bhattiprolu "EventCode": "0xF0BC", 2799749adc3SSukadev Bhattiprolu "EventName": "PM_LS2_UNALIGNED_ST", 2809749adc3SSukadev Bhattiprolu "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 2819749adc3SSukadev Bhattiprolu }, 2829749adc3SSukadev Bhattiprolu {, 2833c22ba52SSukadev Bhattiprolu "EventCode": "0xD0AC", 2843c22ba52SSukadev Bhattiprolu "EventName": "PM_SRQ_SYNC_CYC", 2853c22ba52SSukadev Bhattiprolu "BriefDescription": "A sync is in the S2Q (edge detect to count)" 286826db0f1SSukadev Bhattiprolu }, 287826db0f1SSukadev Bhattiprolu {, 288826db0f1SSukadev Bhattiprolu "EventCode": "0x401E6", 289826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_INST_FROM_L3MISS", 2903c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet" 291826db0f1SSukadev Bhattiprolu }, 292826db0f1SSukadev Bhattiprolu {, 2939749adc3SSukadev Bhattiprolu "EventCode": "0x58A8", 2949749adc3SSukadev Bhattiprolu "EventName": "PM_DECODE_HOLD_ICT_FULL", 2959749adc3SSukadev Bhattiprolu "BriefDescription": "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread" 2969749adc3SSukadev Bhattiprolu }, 2979749adc3SSukadev Bhattiprolu {, 2983c22ba52SSukadev Bhattiprolu "EventCode": "0x26082", 2993c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_IC_INV", 3003c22ba52SSukadev Bhattiprolu "BriefDescription": "I-cache Invalidates sent over the realod bus to the core" 3013c22ba52SSukadev Bhattiprolu }, 3023c22ba52SSukadev Bhattiprolu {, 3033c22ba52SSukadev Bhattiprolu "EventCode": "0xC8AC", 3043c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_RELAUNCH_MISS", 3053c22ba52SSukadev Bhattiprolu "BriefDescription": "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent" 3063c22ba52SSukadev Bhattiprolu }, 3073c22ba52SSukadev Bhattiprolu {, 3083c22ba52SSukadev Bhattiprolu "EventCode": "0x260A4", 3093c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_LD_HIT", 3103c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Hits for demand LDs" 3113c22ba52SSukadev Bhattiprolu }, 3123c22ba52SSukadev Bhattiprolu {, 3133c22ba52SSukadev Bhattiprolu "EventCode": "0xF0A0", 3143c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_STORE", 3153c22ba52SSukadev Bhattiprolu "BriefDescription": "All ops that drain from s2q to L2 containing data" 3163c22ba52SSukadev Bhattiprolu }, 3173c22ba52SSukadev Bhattiprolu {, 3183c22ba52SSukadev Bhattiprolu "EventCode": "0x1D148", 3193c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_RMEM", 3203c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load" 3213c22ba52SSukadev Bhattiprolu }, 3223c22ba52SSukadev Bhattiprolu {, 3233c22ba52SSukadev Bhattiprolu "EventCode": "0x16088", 3243c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LOC_GUESS_CORRECT", 3253c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 guess local (LNS) and guess was correct (ie data local)" 3263c22ba52SSukadev Bhattiprolu }, 3273c22ba52SSukadev Bhattiprolu {, 3283c22ba52SSukadev Bhattiprolu "EventCode": "0x160A4", 3293c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_HIT", 3303c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)" 3313c22ba52SSukadev Bhattiprolu }, 3323c22ba52SSukadev Bhattiprolu {, 3333c22ba52SSukadev Bhattiprolu "EventCode": "0xE09C", 3343c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_TM_L1_MISS", 3353c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm L1 miss" 3363c22ba52SSukadev Bhattiprolu }, 3373c22ba52SSukadev Bhattiprolu {, 3383c22ba52SSukadev Bhattiprolu "EventCode": "0x168B4", 3393c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_LCO_RTY", 3403c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 initiated LCO received retry on port 1 (can try 4 times)" 3413c22ba52SSukadev Bhattiprolu }, 3423c22ba52SSukadev Bhattiprolu {, 3433c22ba52SSukadev Bhattiprolu "EventCode": "0x268AC", 3443c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_RD_USAGE", 3453c22ba52SSukadev Bhattiprolu "BriefDescription": "Rotating sample of 16 RD actives" 3463c22ba52SSukadev Bhattiprolu }, 3473c22ba52SSukadev Bhattiprolu {, 3483c22ba52SSukadev Bhattiprolu "EventCode": "0x1415C", 3493c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC", 3503c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load" 3513c22ba52SSukadev Bhattiprolu }, 3523c22ba52SSukadev Bhattiprolu {, 3533c22ba52SSukadev Bhattiprolu "EventCode": "0xE880", 3543c22ba52SSukadev Bhattiprolu "EventName": "PM_L1_SW_PREF", 3553c22ba52SSukadev Bhattiprolu "BriefDescription": "Software L1 Prefetches, including SW Transient Prefetches" 3563c22ba52SSukadev Bhattiprolu }, 3573c22ba52SSukadev Bhattiprolu {, 3583c22ba52SSukadev Bhattiprolu "EventCode": "0x288C", 3593c22ba52SSukadev Bhattiprolu "EventName": "PM_DISP_CLB_HELD_BAL", 3603c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch/CLB Hold: Balance Flush" 3613c22ba52SSukadev Bhattiprolu }, 3623c22ba52SSukadev Bhattiprolu {, 3633c22ba52SSukadev Bhattiprolu "EventCode": "0x101EA", 3643c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_L1_RELOAD_VALID", 3653c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked demand reload" 3663c22ba52SSukadev Bhattiprolu }, 3673c22ba52SSukadev Bhattiprolu {, 3683c22ba52SSukadev Bhattiprolu "EventCode": "0x1D156", 3693c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_LD_MISS_L1_CYC", 3703c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked ld latency" 3713c22ba52SSukadev Bhattiprolu }, 3723c22ba52SSukadev Bhattiprolu {, 3733c22ba52SSukadev Bhattiprolu "EventCode": "0x4C01A", 3743c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_DMISS_L3MISS", 3753c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion stall due to cache miss resolving missed the L3" 3763c22ba52SSukadev Bhattiprolu }, 3773c22ba52SSukadev Bhattiprolu {, 3783c22ba52SSukadev Bhattiprolu "EventCode": "0x2006C", 3793c22ba52SSukadev Bhattiprolu "EventName": "PM_RUN_CYC_SMT4_MODE", 3803c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT4 mode" 3813c22ba52SSukadev Bhattiprolu }, 3823c22ba52SSukadev Bhattiprolu {, 3833c22ba52SSukadev Bhattiprolu "EventCode": "0x1D14E", 3843c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", 3853c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load" 3863c22ba52SSukadev Bhattiprolu }, 3873c22ba52SSukadev Bhattiprolu {, 3889749adc3SSukadev Bhattiprolu "EventCode": "0xF888", 3899749adc3SSukadev Bhattiprolu "EventName": "PM_LSU1_STORE_REJECT", 3909749adc3SSukadev Bhattiprolu "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" 3919749adc3SSukadev Bhattiprolu }, 3929749adc3SSukadev Bhattiprolu {, 3939749adc3SSukadev Bhattiprolu "EventCode": "0xC098", 3949749adc3SSukadev Bhattiprolu "EventName": "PM_LS2_UNALIGNED_LD", 3959749adc3SSukadev Bhattiprolu "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 3969749adc3SSukadev Bhattiprolu }, 3979749adc3SSukadev Bhattiprolu {, 3983c22ba52SSukadev Bhattiprolu "EventCode": "0x20058", 3993c22ba52SSukadev Bhattiprolu "EventName": "PM_DARQ1_10_12_ENTRIES", 4003c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which 10 or more DARQ1 entries (out of 12) are in use" 4013c22ba52SSukadev Bhattiprolu }, 4023c22ba52SSukadev Bhattiprolu {, 4033c22ba52SSukadev Bhattiprolu "EventCode": "0x360A6", 4043c22ba52SSukadev Bhattiprolu "EventName": "PM_SNP_TM_HIT_M", 4059749adc3SSukadev Bhattiprolu "BriefDescription": "TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified)" 4063c22ba52SSukadev Bhattiprolu }, 4073c22ba52SSukadev Bhattiprolu {, 4083c22ba52SSukadev Bhattiprolu "EventCode": "0x5898", 4093c22ba52SSukadev Bhattiprolu "EventName": "PM_LINK_STACK_INVALID_PTR", 4103c22ba52SSukadev Bhattiprolu "BriefDescription": "It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable." 4113c22ba52SSukadev Bhattiprolu }, 4123c22ba52SSukadev Bhattiprolu {, 4133c22ba52SSukadev Bhattiprolu "EventCode": "0x46088", 4143c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_CHIP_PUMP", 4153c22ba52SSukadev Bhattiprolu "BriefDescription": "RC requests that were local (aka chip) pump attempts" 4163c22ba52SSukadev Bhattiprolu }, 4173c22ba52SSukadev Bhattiprolu {, 4183c22ba52SSukadev Bhattiprolu "EventCode": "0x28A0", 4193c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_TSUSPEND", 4203c22ba52SSukadev Bhattiprolu "BriefDescription": "TM suspend instruction completed" 4213c22ba52SSukadev Bhattiprolu }, 4223c22ba52SSukadev Bhattiprolu {, 4233c22ba52SSukadev Bhattiprolu "EventCode": "0x20054", 4243c22ba52SSukadev Bhattiprolu "EventName": "PM_L1_PREF", 4253c22ba52SSukadev Bhattiprolu "BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch" 4263c22ba52SSukadev Bhattiprolu }, 4273c22ba52SSukadev Bhattiprolu {, 4289749adc3SSukadev Bhattiprolu "EventCode": "0x2608E", 4299749adc3SSukadev Bhattiprolu "EventName": "PM_TM_LD_CONF", 4309749adc3SSukadev Bhattiprolu "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)" 4313c22ba52SSukadev Bhattiprolu }, 4323c22ba52SSukadev Bhattiprolu {, 4333c22ba52SSukadev Bhattiprolu "EventCode": "0x1D144", 4343c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", 4353c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load" 436826db0f1SSukadev Bhattiprolu }, 437826db0f1SSukadev Bhattiprolu {, 438826db0f1SSukadev Bhattiprolu "EventCode": "0x400FA", 439826db0f1SSukadev Bhattiprolu "EventName": "PM_RUN_INST_CMPL", 4403c22ba52SSukadev Bhattiprolu "BriefDescription": "Run_Instructions" 4413c22ba52SSukadev Bhattiprolu }, 4423c22ba52SSukadev Bhattiprolu {, 4433c22ba52SSukadev Bhattiprolu "EventCode": "0x15154", 4443c22ba52SSukadev Bhattiprolu "EventName": "PM_SYNC_MRK_L3MISS", 4453c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt" 4463c22ba52SSukadev Bhattiprolu }, 4473c22ba52SSukadev Bhattiprolu {, 4483c22ba52SSukadev Bhattiprolu "EventCode": "0xE0B4", 4493c22ba52SSukadev Bhattiprolu "EventName": "PM_LS0_TM_DISALLOW", 4503c22ba52SSukadev Bhattiprolu "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it" 4513c22ba52SSukadev Bhattiprolu }, 4523c22ba52SSukadev Bhattiprolu {, 4533c22ba52SSukadev Bhattiprolu "EventCode": "0x26884", 4543c22ba52SSukadev Bhattiprolu "EventName": "PM_DSIDE_MRU_TOUCH", 4559749adc3SSukadev Bhattiprolu "BriefDescription": "D-side L2 MRU touch commands sent to the L2" 4563c22ba52SSukadev Bhattiprolu }, 4573c22ba52SSukadev Bhattiprolu {, 4583c22ba52SSukadev Bhattiprolu "EventCode": "0x30134", 4593c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_ST_CMPL_INT", 4603c22ba52SSukadev Bhattiprolu "BriefDescription": "marked store finished with intervention" 4613c22ba52SSukadev Bhattiprolu }, 4623c22ba52SSukadev Bhattiprolu {, 4633c22ba52SSukadev Bhattiprolu "EventCode": "0xC0B8", 4643c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_SAO", 4653c22ba52SSukadev Bhattiprolu "BriefDescription": "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush" 4663c22ba52SSukadev Bhattiprolu }, 4673c22ba52SSukadev Bhattiprolu {, 4683c22ba52SSukadev Bhattiprolu "EventCode": "0x50A8", 4693c22ba52SSukadev Bhattiprolu "EventName": "PM_EAT_FORCE_MISPRED", 4703c22ba52SSukadev Bhattiprolu "BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued" 4713c22ba52SSukadev Bhattiprolu }, 4723c22ba52SSukadev Bhattiprolu {, 4739749adc3SSukadev Bhattiprolu "EventCode": "0xC094", 4749749adc3SSukadev Bhattiprolu "EventName": "PM_LS0_UNALIGNED_LD", 4759749adc3SSukadev Bhattiprolu "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 4769749adc3SSukadev Bhattiprolu }, 4779749adc3SSukadev Bhattiprolu {, 4789749adc3SSukadev Bhattiprolu "EventCode": "0xF8BC", 4799749adc3SSukadev Bhattiprolu "EventName": "PM_LS3_UNALIGNED_ST", 4809749adc3SSukadev Bhattiprolu "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 4819749adc3SSukadev Bhattiprolu }, 4829749adc3SSukadev Bhattiprolu {, 483e795dd42SSukadev Bhattiprolu "EventCode": "0x460AE", 484e795dd42SSukadev Bhattiprolu "EventName": "PM_L3_P2_CO_RTY", 485e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 CO received retry port 2 (memory only), every retry counted" 4863c22ba52SSukadev Bhattiprolu }, 4873c22ba52SSukadev Bhattiprolu {, 4883c22ba52SSukadev Bhattiprolu "EventCode": "0x58B0", 4893c22ba52SSukadev Bhattiprolu "EventName": "PM_BTAC_GOOD_RESULT", 4903c22ba52SSukadev Bhattiprolu "BriefDescription": "BTAC predicts a taken branch and the BHT agrees, and the target address is correct" 4913c22ba52SSukadev Bhattiprolu }, 4923c22ba52SSukadev Bhattiprolu {, 4933c22ba52SSukadev Bhattiprolu "EventCode": "0x1C04C", 4943c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_LL4", 4953c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load" 4963c22ba52SSukadev Bhattiprolu }, 4973c22ba52SSukadev Bhattiprolu {, 4983c22ba52SSukadev Bhattiprolu "EventCode": "0x3608E", 4993c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_ST_CONF", 5003c22ba52SSukadev Bhattiprolu "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)" 5013c22ba52SSukadev Bhattiprolu }, 5023c22ba52SSukadev Bhattiprolu {, 5033c22ba52SSukadev Bhattiprolu "EventCode": "0xF8A0", 5043c22ba52SSukadev Bhattiprolu "EventName": "PM_NON_DATA_STORE", 5053c22ba52SSukadev Bhattiprolu "BriefDescription": "All ops that drain from s2q to L2 and contain no data" 5063c22ba52SSukadev Bhattiprolu }, 5073c22ba52SSukadev Bhattiprolu {, 5083c22ba52SSukadev Bhattiprolu "EventCode": "0x3F146", 5093c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DPTEG_FROM_L21_SHR", 5103c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 5113c22ba52SSukadev Bhattiprolu }, 5123c22ba52SSukadev Bhattiprolu {, 5133c22ba52SSukadev Bhattiprolu "EventCode": "0x40A0", 5143c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_UNCOND", 5153c22ba52SSukadev Bhattiprolu "BriefDescription": "Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve." 5163c22ba52SSukadev Bhattiprolu }, 5173c22ba52SSukadev Bhattiprolu {, 5183c22ba52SSukadev Bhattiprolu "EventCode": "0xF8A8", 5193c22ba52SSukadev Bhattiprolu "EventName": "PM_DC_PREF_FUZZY_CONF", 5203c22ba52SSukadev Bhattiprolu "BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)" 5213c22ba52SSukadev Bhattiprolu }, 5223c22ba52SSukadev Bhattiprolu {, 5233c22ba52SSukadev Bhattiprolu "EventCode": "0xF8A4", 5243c22ba52SSukadev Bhattiprolu "EventName": "PM_DC_PREF_SW_ALLOC", 5253c22ba52SSukadev Bhattiprolu "BriefDescription": "Prefetch stream allocated by software prefetching" 5263c22ba52SSukadev Bhattiprolu }, 5273c22ba52SSukadev Bhattiprolu {, 5283c22ba52SSukadev Bhattiprolu "EventCode": "0xE0A0", 5293c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_TM_L1_MISS", 5303c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm L1 miss" 5313c22ba52SSukadev Bhattiprolu }, 5323c22ba52SSukadev Bhattiprolu {, 533e795dd42SSukadev Bhattiprolu "EventCode": "0xC880", 534e795dd42SSukadev Bhattiprolu "EventName": "PM_LS1_LD_VECTOR_FIN", 5359749adc3SSukadev Bhattiprolu "BriefDescription": "LS1 finished load vector op" 536e795dd42SSukadev Bhattiprolu }, 537e795dd42SSukadev Bhattiprolu {, 5383c22ba52SSukadev Bhattiprolu "EventCode": "0x2894", 5393c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_OUTER_TEND", 5403c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion time outer tend" 5413c22ba52SSukadev Bhattiprolu }, 5423c22ba52SSukadev Bhattiprolu {, 5433c22ba52SSukadev Bhattiprolu "EventCode": "0xF098", 5443c22ba52SSukadev Bhattiprolu "EventName": "PM_XLATE_HPT_MODE", 5453c22ba52SSukadev Bhattiprolu "BriefDescription": "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)" 5463c22ba52SSukadev Bhattiprolu }, 5473c22ba52SSukadev Bhattiprolu {, 5483c22ba52SSukadev Bhattiprolu "EventCode": "0x2C04E", 5493c22ba52SSukadev Bhattiprolu "EventName": "PM_LD_MISS_L1_FIN", 5503c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op." 5513c22ba52SSukadev Bhattiprolu }, 5523c22ba52SSukadev Bhattiprolu {, 5533c22ba52SSukadev Bhattiprolu "EventCode": "0x30162", 5543c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_LSU_DERAT_MISS", 5553c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked derat reload (miss) for any page size" 5563c22ba52SSukadev Bhattiprolu }, 5573c22ba52SSukadev Bhattiprolu {, 5589749adc3SSukadev Bhattiprolu "EventCode": "0x160A0", 5599749adc3SSukadev Bhattiprolu "EventName": "PM_L3_PF_MISS_L3", 5609749adc3SSukadev Bhattiprolu "BriefDescription": "L3 PF missed in L3" 5619749adc3SSukadev Bhattiprolu }, 5629749adc3SSukadev Bhattiprolu {, 5633c22ba52SSukadev Bhattiprolu "EventCode": "0x1C04A", 5643c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_RL2L3_SHR", 5653c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load" 5663c22ba52SSukadev Bhattiprolu }, 5673c22ba52SSukadev Bhattiprolu {, 5683c22ba52SSukadev Bhattiprolu "EventCode": "0x268B0", 5693c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_GRP_PUMP", 5703c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF sent with grp scope port 1, counts even retried requests" 5713c22ba52SSukadev Bhattiprolu }, 5723c22ba52SSukadev Bhattiprolu {, 5733c22ba52SSukadev Bhattiprolu "EventCode": "0x30016", 5743c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_SRQ_FULL", 5753c22ba52SSukadev Bhattiprolu "BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full" 5763c22ba52SSukadev Bhattiprolu }, 5773c22ba52SSukadev Bhattiprolu {, 5783c22ba52SSukadev Bhattiprolu "EventCode": "0x40B4", 5793c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_PRED_TA", 5803c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE" 5813c22ba52SSukadev Bhattiprolu }, 5823c22ba52SSukadev Bhattiprolu {, 5833c22ba52SSukadev Bhattiprolu "EventCode": "0x40AC", 5843c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_MPRED_CCACHE", 5853c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction" 5863c22ba52SSukadev Bhattiprolu }, 5873c22ba52SSukadev Bhattiprolu {, 5883c22ba52SSukadev Bhattiprolu "EventCode": "0x3688A", 5893c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RTY_LD", 5903c22ba52SSukadev Bhattiprolu "BriefDescription": "RC retries on PB for any load from core (excludes DCBFs)" 5913c22ba52SSukadev Bhattiprolu }, 5923c22ba52SSukadev Bhattiprolu {, 5933c22ba52SSukadev Bhattiprolu "EventCode": "0xE08C", 5943c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_ERAT_HIT", 5953c22ba52SSukadev Bhattiprolu "BriefDescription": "Primary ERAT hit. There is no secondary ERAT" 5963c22ba52SSukadev Bhattiprolu }, 5973c22ba52SSukadev Bhattiprolu {, 5983c22ba52SSukadev Bhattiprolu "EventCode": "0xE088", 5993c22ba52SSukadev Bhattiprolu "EventName": "PM_LS2_ERAT_MISS_PREF", 6003c22ba52SSukadev Bhattiprolu "BriefDescription": "LS0 Erat miss due to prefetch" 6013c22ba52SSukadev Bhattiprolu }, 6023c22ba52SSukadev Bhattiprolu {, 6033c22ba52SSukadev Bhattiprolu "EventCode": "0xF0A8", 6043c22ba52SSukadev Bhattiprolu "EventName": "PM_DC_PREF_CONF", 6053c22ba52SSukadev Bhattiprolu "BriefDescription": "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams" 6063c22ba52SSukadev Bhattiprolu }, 6073c22ba52SSukadev Bhattiprolu {, 6083c22ba52SSukadev Bhattiprolu "EventCode": "0x16888", 6093c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LOC_GUESS_WRONG", 6103c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 guess local (LNS) and guess was not correct (ie data not on chip)" 6113c22ba52SSukadev Bhattiprolu }, 6123c22ba52SSukadev Bhattiprolu {, 6139749adc3SSukadev Bhattiprolu "EventCode": "0xC888", 6149749adc3SSukadev Bhattiprolu "EventName": "PM_LSU_DTLB_MISS_64K", 6159749adc3SSukadev Bhattiprolu "BriefDescription": "Data TLB Miss page size 64K" 6169749adc3SSukadev Bhattiprolu }, 6179749adc3SSukadev Bhattiprolu {, 6183c22ba52SSukadev Bhattiprolu "EventCode": "0xE0A4", 6193c22ba52SSukadev Bhattiprolu "EventName": "PM_TMA_REQ_L2", 6203c22ba52SSukadev Bhattiprolu "BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding" 6213c22ba52SSukadev Bhattiprolu }, 6223c22ba52SSukadev Bhattiprolu {, 6239749adc3SSukadev Bhattiprolu "EventCode": "0xC088", 6249749adc3SSukadev Bhattiprolu "EventName": "PM_LSU_DTLB_MISS_4K", 6259749adc3SSukadev Bhattiprolu "BriefDescription": "Data TLB Miss page size 4K" 6269749adc3SSukadev Bhattiprolu }, 6279749adc3SSukadev Bhattiprolu {, 6283c22ba52SSukadev Bhattiprolu "EventCode": "0x3C042", 6293c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_L3_DISP_CONFLICT", 6303c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load" 6313c22ba52SSukadev Bhattiprolu }, 6323c22ba52SSukadev Bhattiprolu {, 6333c22ba52SSukadev Bhattiprolu "EventCode": "0x168AA", 6343c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_LCO_NO_DATA", 6353c22ba52SSukadev Bhattiprolu "BriefDescription": "Dataless L3 LCO sent port 1" 6363c22ba52SSukadev Bhattiprolu }, 6373c22ba52SSukadev Bhattiprolu {, 6383c22ba52SSukadev Bhattiprolu "EventCode": "0x3D140", 6393c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", 6403c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load" 6413c22ba52SSukadev Bhattiprolu }, 6423c22ba52SSukadev Bhattiprolu {, 6433c22ba52SSukadev Bhattiprolu "EventCode": "0xC89C", 6443c22ba52SSukadev Bhattiprolu "EventName": "PM_LS1_LAUNCH_HELD_PREF", 6453c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle" 6463c22ba52SSukadev Bhattiprolu }, 6473c22ba52SSukadev Bhattiprolu {, 6483c22ba52SSukadev Bhattiprolu "EventCode": "0x4894", 6493c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_RELOAD_PRIVATE", 6503c22ba52SSukadev Bhattiprolu "BriefDescription": "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat" 6513c22ba52SSukadev Bhattiprolu }, 6523c22ba52SSukadev Bhattiprolu {, 6533c22ba52SSukadev Bhattiprolu "EventCode": "0x1688E", 6543c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_LD_CAUSED_FAIL", 6553c22ba52SSukadev Bhattiprolu "BriefDescription": "Non-TM Load caused any thread to fail" 6563c22ba52SSukadev Bhattiprolu }, 6573c22ba52SSukadev Bhattiprolu {, 6583c22ba52SSukadev Bhattiprolu "EventCode": "0x26084", 6593c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RCLD_DISP_FAIL_OTHER", 6609749adc3SSukadev Bhattiprolu "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machines (e.g. Read-Claim/Snoop machine not available)" 6613c22ba52SSukadev Bhattiprolu }, 6623c22ba52SSukadev Bhattiprolu {, 6633c22ba52SSukadev Bhattiprolu "EventCode": "0x101E4", 6643c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_L1_ICACHE_MISS", 6653c22ba52SSukadev Bhattiprolu "BriefDescription": "sampled Instruction suffered an icache Miss" 6663c22ba52SSukadev Bhattiprolu }, 6673c22ba52SSukadev Bhattiprolu {, 6683c22ba52SSukadev Bhattiprolu "EventCode": "0x20A0", 6693c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_NESTED_TBEGIN", 6703c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion Tm nested tbegin" 6713c22ba52SSukadev Bhattiprolu }, 6723c22ba52SSukadev Bhattiprolu {, 6733c22ba52SSukadev Bhattiprolu "EventCode": "0x368AA", 6743c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_CO_MEM", 6753c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO to memory port 1 with or without data" 6763c22ba52SSukadev Bhattiprolu }, 6773c22ba52SSukadev Bhattiprolu {, 6783c22ba52SSukadev Bhattiprolu "EventCode": "0xC8A4", 6793c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_FALSE_LHS", 6803c22ba52SSukadev Bhattiprolu "BriefDescription": "False LHS match detected" 6813c22ba52SSukadev Bhattiprolu }, 6823c22ba52SSukadev Bhattiprolu {, 683e795dd42SSukadev Bhattiprolu "EventCode": "0xF0B0", 684e795dd42SSukadev Bhattiprolu "EventName": "PM_L3_LD_PREF", 685e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest" 6863c22ba52SSukadev Bhattiprolu }, 6873c22ba52SSukadev Bhattiprolu {, 6883c22ba52SSukadev Bhattiprolu "EventCode": "0x4D012", 6893c22ba52SSukadev Bhattiprolu "EventName": "PM_PMC3_SAVED", 6903c22ba52SSukadev Bhattiprolu "BriefDescription": "PMC3 Rewind Value saved" 6913c22ba52SSukadev Bhattiprolu }, 6923c22ba52SSukadev Bhattiprolu {, 6933c22ba52SSukadev Bhattiprolu "EventCode": "0xE888", 6943c22ba52SSukadev Bhattiprolu "EventName": "PM_LS3_ERAT_MISS_PREF", 6953c22ba52SSukadev Bhattiprolu "BriefDescription": "LS1 Erat miss due to prefetch" 6963c22ba52SSukadev Bhattiprolu }, 6973c22ba52SSukadev Bhattiprolu {, 6983c22ba52SSukadev Bhattiprolu "EventCode": "0x368B4", 6993c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_RD0_BUSY", 7003c22ba52SSukadev Bhattiprolu "BriefDescription": "Lifetime, sample of RD machine 0 valid" 7013c22ba52SSukadev Bhattiprolu }, 7023c22ba52SSukadev Bhattiprolu {, 7033c22ba52SSukadev Bhattiprolu "EventCode": "0x46080", 7043c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_DISP_ALL_L2MISS", 7059749adc3SSukadev Bhattiprolu "BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this thread that were an L2 miss" 7063c22ba52SSukadev Bhattiprolu }, 7073c22ba52SSukadev Bhattiprolu {, 7089749adc3SSukadev Bhattiprolu "EventCode": "0xF8B8", 7099749adc3SSukadev Bhattiprolu "EventName": "PM_LS1_UNALIGNED_ST", 7109749adc3SSukadev Bhattiprolu "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 7113c22ba52SSukadev Bhattiprolu }, 7123c22ba52SSukadev Bhattiprolu {, 7133c22ba52SSukadev Bhattiprolu "EventCode": "0x408C", 7143c22ba52SSukadev Bhattiprolu "EventName": "PM_L1_DEMAND_WRITE", 7153c22ba52SSukadev Bhattiprolu "BriefDescription": "Instruction Demand sectors written into IL1" 7163c22ba52SSukadev Bhattiprolu }, 7173c22ba52SSukadev Bhattiprolu {, 7183c22ba52SSukadev Bhattiprolu "EventCode": "0x368A8", 7193c22ba52SSukadev Bhattiprolu "EventName": "PM_SN_INVL", 7203c22ba52SSukadev Bhattiprolu "BriefDescription": "Any port snooper detects a store to a line in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1" 7213c22ba52SSukadev Bhattiprolu }, 7223c22ba52SSukadev Bhattiprolu {, 7233c22ba52SSukadev Bhattiprolu "EventCode": "0x160B2", 7243c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_LOC_GUESS_CORRECT", 7259749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected LNS and was correct" 7263c22ba52SSukadev Bhattiprolu }, 7273c22ba52SSukadev Bhattiprolu {, 7283c22ba52SSukadev Bhattiprolu "EventCode": "0x48B4", 7293c22ba52SSukadev Bhattiprolu "EventName": "PM_DECODE_FUSION_CONST_GEN", 7303c22ba52SSukadev Bhattiprolu "BriefDescription": "32-bit constant generation" 7313c22ba52SSukadev Bhattiprolu }, 7323c22ba52SSukadev Bhattiprolu {, 7333c22ba52SSukadev Bhattiprolu "EventCode": "0x4D146", 7343c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L21_MOD", 7353c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load" 7363c22ba52SSukadev Bhattiprolu }, 7373c22ba52SSukadev Bhattiprolu {, 7383c22ba52SSukadev Bhattiprolu "EventCode": "0xE080", 7393c22ba52SSukadev Bhattiprolu "EventName": "PM_S2Q_FULL", 7403c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles during which the S2Q is full" 7413c22ba52SSukadev Bhattiprolu }, 7423c22ba52SSukadev Bhattiprolu {, 7433c22ba52SSukadev Bhattiprolu "EventCode": "0x268B4", 7443c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P3_LCO_RTY", 7453c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 initiated LCO received retry on port 3 (can try 4 times)" 7463c22ba52SSukadev Bhattiprolu }, 7473c22ba52SSukadev Bhattiprolu {, 7483c22ba52SSukadev Bhattiprolu "EventCode": "0xD8B8", 7493c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_LMQ_S0_VALID", 7503c22ba52SSukadev Bhattiprolu "BriefDescription": "Slot 0 of LMQ valid" 7513c22ba52SSukadev Bhattiprolu }, 7523c22ba52SSukadev Bhattiprolu {, 7533c22ba52SSukadev Bhattiprolu "EventCode": "0x2098", 7543c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_NESTED_TEND", 7553c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion time nested tend" 7563c22ba52SSukadev Bhattiprolu }, 7573c22ba52SSukadev Bhattiprolu {, 7583c22ba52SSukadev Bhattiprolu "EventCode": "0x368A0", 7593c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF_OFF_CHIP_CACHE", 7603c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF from Off chip cache" 7613c22ba52SSukadev Bhattiprolu }, 7623c22ba52SSukadev Bhattiprolu {, 7633c22ba52SSukadev Bhattiprolu "EventCode": "0x20056", 7643c22ba52SSukadev Bhattiprolu "EventName": "PM_TAKEN_BR_MPRED_CMPL", 7653c22ba52SSukadev Bhattiprolu "BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions" 7663c22ba52SSukadev Bhattiprolu }, 7673c22ba52SSukadev Bhattiprolu {, 7683c22ba52SSukadev Bhattiprolu "EventCode": "0x4688A", 7693c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_SYS_PUMP", 7703c22ba52SSukadev Bhattiprolu "BriefDescription": "RC requests that were system pump attempts" 7713c22ba52SSukadev Bhattiprolu }, 7723c22ba52SSukadev Bhattiprolu {, 7733c22ba52SSukadev Bhattiprolu "EventCode": "0xE090", 7743c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_ERAT_HIT", 7753c22ba52SSukadev Bhattiprolu "BriefDescription": "Primary ERAT hit. There is no secondary ERAT" 7763c22ba52SSukadev Bhattiprolu }, 7773c22ba52SSukadev Bhattiprolu {, 7783c22ba52SSukadev Bhattiprolu "EventCode": "0x4001C", 7793c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_IMC_MATCH_CMPL", 7803c22ba52SSukadev Bhattiprolu "BriefDescription": "IMC Match Count" 7813c22ba52SSukadev Bhattiprolu }, 7823c22ba52SSukadev Bhattiprolu {, 7833c22ba52SSukadev Bhattiprolu "EventCode": "0x40A8", 7843c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_PRED_LSTACK", 7853c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that used the Link Stack for Target Prediction" 7863c22ba52SSukadev Bhattiprolu }, 7873c22ba52SSukadev Bhattiprolu {, 7883c22ba52SSukadev Bhattiprolu "EventCode": "0x268A2", 7893c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CI_MISS", 7903c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 castins miss (total count)" 7913c22ba52SSukadev Bhattiprolu }, 7923c22ba52SSukadev Bhattiprolu {, 7933c22ba52SSukadev Bhattiprolu "EventCode": "0x289C", 7943c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_NON_FAV_TBEGIN", 7953c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch time non favored tbegin" 7963c22ba52SSukadev Bhattiprolu }, 7973c22ba52SSukadev Bhattiprolu {, 7983c22ba52SSukadev Bhattiprolu "EventCode": "0xF08C", 7993c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_STORE_REJECT", 8003c22ba52SSukadev Bhattiprolu "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" 8013c22ba52SSukadev Bhattiprolu }, 8023c22ba52SSukadev Bhattiprolu {, 8033c22ba52SSukadev Bhattiprolu "EventCode": "0x360A0", 8043c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF_ON_CHIP_CACHE", 8053c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF from On chip cache" 8063c22ba52SSukadev Bhattiprolu }, 8073c22ba52SSukadev Bhattiprolu {, 8083c22ba52SSukadev Bhattiprolu "EventCode": "0x35152", 8093c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC", 8103c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load" 8113c22ba52SSukadev Bhattiprolu }, 8123c22ba52SSukadev Bhattiprolu {, 8133c22ba52SSukadev Bhattiprolu "EventCode": "0x160AC", 8143c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_SN_USAGE", 8153c22ba52SSukadev Bhattiprolu "BriefDescription": "Rotating sample of 16 snoop valids" 8163c22ba52SSukadev Bhattiprolu }, 8173c22ba52SSukadev Bhattiprolu {, 8183c22ba52SSukadev Bhattiprolu "EventCode": "0x1608C", 8193c22ba52SSukadev Bhattiprolu "EventName": "PM_RC0_BUSY", 8203c22ba52SSukadev Bhattiprolu "BriefDescription": "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)" 8213c22ba52SSukadev Bhattiprolu }, 8223c22ba52SSukadev Bhattiprolu {, 8233c22ba52SSukadev Bhattiprolu "EventCode": "0x36082", 8243c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LD_DISP", 8259749adc3SSukadev Bhattiprolu "BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread" 8263c22ba52SSukadev Bhattiprolu }, 8273c22ba52SSukadev Bhattiprolu {, 8283c22ba52SSukadev Bhattiprolu "EventCode": "0xF8B0", 8293c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_SW_PREF", 8303c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest" 8313c22ba52SSukadev Bhattiprolu }, 8323c22ba52SSukadev Bhattiprolu {, 8333c22ba52SSukadev Bhattiprolu "EventCode": "0xF884", 8343c22ba52SSukadev Bhattiprolu "EventName": "PM_TABLEWALK_CYC_PREF", 8353c22ba52SSukadev Bhattiprolu "BriefDescription": "tablewalk qualified for pte prefetches" 8363c22ba52SSukadev Bhattiprolu }, 8373c22ba52SSukadev Bhattiprolu {, 8383c22ba52SSukadev Bhattiprolu "EventCode": "0x4D144", 8393c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD", 8403c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load" 8413c22ba52SSukadev Bhattiprolu }, 8423c22ba52SSukadev Bhattiprolu {, 8433c22ba52SSukadev Bhattiprolu "EventCode": "0x16884", 8443c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RCLD_DISP_FAIL_ADDR", 8459749adc3SSukadev Bhattiprolu "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machines already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines)" 8463c22ba52SSukadev Bhattiprolu }, 8473c22ba52SSukadev Bhattiprolu {, 8483c22ba52SSukadev Bhattiprolu "EventCode": "0x460A0", 8493c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF_ON_CHIP_MEM", 8503c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF from On chip memory" 8513c22ba52SSukadev Bhattiprolu }, 8523c22ba52SSukadev Bhattiprolu {, 8533c22ba52SSukadev Bhattiprolu "EventCode": "0xF084", 8543c22ba52SSukadev Bhattiprolu "EventName": "PM_PTE_PREFETCH", 8553c22ba52SSukadev Bhattiprolu "BriefDescription": "PTE prefetches" 8563c22ba52SSukadev Bhattiprolu }, 8573c22ba52SSukadev Bhattiprolu {, 8583c22ba52SSukadev Bhattiprolu "EventCode": "0x2D026", 8593c22ba52SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L1_PDE_FROM_L2", 8603c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache" 8613c22ba52SSukadev Bhattiprolu }, 8623c22ba52SSukadev Bhattiprolu {, 8633c22ba52SSukadev Bhattiprolu "EventCode": "0x48B0", 8643c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_MPRED_PCACHE", 8653c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that was Mispredicted due to pattern cache prediction" 8663c22ba52SSukadev Bhattiprolu }, 8673c22ba52SSukadev Bhattiprolu {, 8683c22ba52SSukadev Bhattiprolu "EventCode": "0x2C126", 8693c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2", 8703c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load" 8713c22ba52SSukadev Bhattiprolu }, 8723c22ba52SSukadev Bhattiprolu {, 8733c22ba52SSukadev Bhattiprolu "EventCode": "0xE0AC", 8743c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_TLBIE", 8753c22ba52SSukadev Bhattiprolu "BriefDescription": "Transaction failed because there was a TLBIE hit in the bloom filter" 8763c22ba52SSukadev Bhattiprolu }, 8773c22ba52SSukadev Bhattiprolu {, 8783c22ba52SSukadev Bhattiprolu "EventCode": "0x260AA", 8793c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_LCO_DATA", 8803c22ba52SSukadev Bhattiprolu "BriefDescription": "LCO sent with data port 0" 8813c22ba52SSukadev Bhattiprolu }, 8823c22ba52SSukadev Bhattiprolu {, 8833c22ba52SSukadev Bhattiprolu "EventCode": "0x4888", 8843c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_PREF_REQ", 8853c22ba52SSukadev Bhattiprolu "BriefDescription": "Instruction prefetch requests" 8863c22ba52SSukadev Bhattiprolu }, 8873c22ba52SSukadev Bhattiprolu {, 8889749adc3SSukadev Bhattiprolu "EventCode": "0xC898", 8899749adc3SSukadev Bhattiprolu "EventName": "PM_LS3_UNALIGNED_LD", 8909749adc3SSukadev Bhattiprolu "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 8919749adc3SSukadev Bhattiprolu }, 8929749adc3SSukadev Bhattiprolu {, 8933c22ba52SSukadev Bhattiprolu "EventCode": "0x488C", 8943c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_PREF_WRITE", 8953c22ba52SSukadev Bhattiprolu "BriefDescription": "Instruction prefetch written into IL1" 8963c22ba52SSukadev Bhattiprolu }, 8973c22ba52SSukadev Bhattiprolu {, 8983c22ba52SSukadev Bhattiprolu "EventCode": "0xF89C", 8993c22ba52SSukadev Bhattiprolu "EventName": "PM_XLATE_MISS", 9009749adc3SSukadev Bhattiprolu "BriefDescription": "The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand" 9013c22ba52SSukadev Bhattiprolu }, 9023c22ba52SSukadev Bhattiprolu {, 9033c22ba52SSukadev Bhattiprolu "EventCode": "0x14158", 9043c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC", 9053c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load" 9063c22ba52SSukadev Bhattiprolu }, 9073c22ba52SSukadev Bhattiprolu {, 9083c22ba52SSukadev Bhattiprolu "EventCode": "0x35156", 9093c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L31_SHR_CYC", 9103c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load" 9113c22ba52SSukadev Bhattiprolu }, 9123c22ba52SSukadev Bhattiprolu {, 9139749adc3SSukadev Bhattiprolu "EventCode": "0xC88C", 9149749adc3SSukadev Bhattiprolu "EventName": "PM_LSU_DTLB_MISS_16G_1G", 9159749adc3SSukadev Bhattiprolu "BriefDescription": "Data TLB Miss page size 16G (HPT) or 1G (Radix)" 9169749adc3SSukadev Bhattiprolu }, 9179749adc3SSukadev Bhattiprolu {, 9183c22ba52SSukadev Bhattiprolu "EventCode": "0x268A6", 9193c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_RST_SC", 9209749adc3SSukadev Bhattiprolu "BriefDescription": "TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated" 9213c22ba52SSukadev Bhattiprolu }, 9223c22ba52SSukadev Bhattiprolu {, 9233c22ba52SSukadev Bhattiprolu "EventCode": "0x468A4", 9243c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_TRANS_PF", 9253c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Transient prefetch received from L2" 9263c22ba52SSukadev Bhattiprolu }, 9273c22ba52SSukadev Bhattiprolu {, 9283c22ba52SSukadev Bhattiprolu "EventCode": "0x4094", 9293c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_PREF_CANCEL_L2", 9303c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 Squashed a demand or prefetch request" 9313c22ba52SSukadev Bhattiprolu }, 9323c22ba52SSukadev Bhattiprolu {, 9333c22ba52SSukadev Bhattiprolu "EventCode": "0x48AC", 9343c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_MPRED_LSTACK", 9353c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction" 9363c22ba52SSukadev Bhattiprolu }, 9373c22ba52SSukadev Bhattiprolu {, 9383c22ba52SSukadev Bhattiprolu "EventCode": "0xE88C", 9393c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU1_ERAT_HIT", 9403c22ba52SSukadev Bhattiprolu "BriefDescription": "Primary ERAT hit. There is no secondary ERAT" 9413c22ba52SSukadev Bhattiprolu }, 9423c22ba52SSukadev Bhattiprolu {, 9433c22ba52SSukadev Bhattiprolu "EventCode": "0xC0B4", 9443c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_WRK_ARND", 9453c22ba52SSukadev Bhattiprolu "BriefDescription": "LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable." 9463c22ba52SSukadev Bhattiprolu }, 9473c22ba52SSukadev Bhattiprolu {, 9483c22ba52SSukadev Bhattiprolu "EventCode": "0x34054", 9493c22ba52SSukadev Bhattiprolu "EventName": "PM_PARTIAL_ST_FIN", 9503c22ba52SSukadev Bhattiprolu "BriefDescription": "Any store finished by an LSU slice" 9513c22ba52SSukadev Bhattiprolu }, 9523c22ba52SSukadev Bhattiprolu {, 9533c22ba52SSukadev Bhattiprolu "EventCode": "0x5880", 9543c22ba52SSukadev Bhattiprolu "EventName": "PM_THRD_PRIO_6_7_CYC", 9553c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles thread running at priority level 6 or 7" 9563c22ba52SSukadev Bhattiprolu }, 9573c22ba52SSukadev Bhattiprolu {, 9583c22ba52SSukadev Bhattiprolu "EventCode": "0x4898", 9593c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_DEMAND_L2_BR_REDIRECT", 9603c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 I cache demand request due to branch Mispredict ( 15 cycle path)" 9613c22ba52SSukadev Bhattiprolu }, 9623c22ba52SSukadev Bhattiprolu {, 9633c22ba52SSukadev Bhattiprolu "EventCode": "0x4880", 9643c22ba52SSukadev Bhattiprolu "EventName": "PM_BANK_CONFLICT", 9653c22ba52SSukadev Bhattiprolu "BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle." 9663c22ba52SSukadev Bhattiprolu }, 9673c22ba52SSukadev Bhattiprolu {, 9683c22ba52SSukadev Bhattiprolu "EventCode": "0x360B0", 9693c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_SYS_PUMP", 9703c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF sent with sys scope port 0, counts even retried requests" 9713c22ba52SSukadev Bhattiprolu }, 9723c22ba52SSukadev Bhattiprolu {, 9733c22ba52SSukadev Bhattiprolu "EventCode": "0x3006A", 9743c22ba52SSukadev Bhattiprolu "EventName": "PM_IERAT_RELOAD_64K", 9753c22ba52SSukadev Bhattiprolu "BriefDescription": "IERAT Reloaded (Miss) for a 64k page" 9763c22ba52SSukadev Bhattiprolu }, 9773c22ba52SSukadev Bhattiprolu {, 9783c22ba52SSukadev Bhattiprolu "EventCode": "0xD8BC", 9793c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_3_LRQF_FULL_CYC", 9803c22ba52SSukadev Bhattiprolu "BriefDescription": "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ" 9813c22ba52SSukadev Bhattiprolu }, 9823c22ba52SSukadev Bhattiprolu {, 9833c22ba52SSukadev Bhattiprolu "EventCode": "0x46086", 9843c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_SN_M_RD_DONE", 9859749adc3SSukadev Bhattiprolu "BriefDescription": "Snoop dispatched for a read and was M (true M)" 9863c22ba52SSukadev Bhattiprolu }, 9873c22ba52SSukadev Bhattiprolu {, 9883c22ba52SSukadev Bhattiprolu "EventCode": "0x40154", 9893c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_FAB_RSP_BKILL", 9903c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked store had to do a bkill" 9913c22ba52SSukadev Bhattiprolu }, 9923c22ba52SSukadev Bhattiprolu {, 9933c22ba52SSukadev Bhattiprolu "EventCode": "0xF094", 9943c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_L1_CAM_CANCEL", 9953c22ba52SSukadev Bhattiprolu "BriefDescription": "ls2 l1 tm cam cancel" 9963c22ba52SSukadev Bhattiprolu }, 9973c22ba52SSukadev Bhattiprolu {, 9983c22ba52SSukadev Bhattiprolu "EventCode": "0x2D014", 9993c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_LRQ_FULL", 10003c22ba52SSukadev Bhattiprolu "BriefDescription": "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full" 10013c22ba52SSukadev Bhattiprolu }, 10023c22ba52SSukadev Bhattiprolu {, 10033c22ba52SSukadev Bhattiprolu "EventCode": "0x3E05E", 10043c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CO_MEPF", 1005e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request" 10063c22ba52SSukadev Bhattiprolu }, 10073c22ba52SSukadev Bhattiprolu {, 10083c22ba52SSukadev Bhattiprolu "EventCode": "0x460A2", 10093c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_LAT_CI_HIT", 10103c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Lateral Castins Hit" 10113c22ba52SSukadev Bhattiprolu }, 10123c22ba52SSukadev Bhattiprolu {, 10133c22ba52SSukadev Bhattiprolu "EventCode": "0x3D14E", 10143c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD", 10153c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load" 10163c22ba52SSukadev Bhattiprolu }, 10173c22ba52SSukadev Bhattiprolu {, 10183c22ba52SSukadev Bhattiprolu "EventCode": "0x3D15E", 10193c22ba52SSukadev Bhattiprolu "EventName": "PM_MULT_MRK", 10203c22ba52SSukadev Bhattiprolu "BriefDescription": "mult marked instr" 10213c22ba52SSukadev Bhattiprolu }, 10223c22ba52SSukadev Bhattiprolu {, 10233c22ba52SSukadev Bhattiprolu "EventCode": "0x4084", 10243c22ba52SSukadev Bhattiprolu "EventName": "PM_EAT_FULL_CYC", 10253c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles No room in EAT" 10263c22ba52SSukadev Bhattiprolu }, 10273c22ba52SSukadev Bhattiprolu {, 10283c22ba52SSukadev Bhattiprolu "EventCode": "0x5098", 10293c22ba52SSukadev Bhattiprolu "EventName": "PM_LINK_STACK_WRONG_ADD_PRED", 10303c22ba52SSukadev Bhattiprolu "BriefDescription": "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions" 10313c22ba52SSukadev Bhattiprolu }, 10323c22ba52SSukadev Bhattiprolu {, 10333c22ba52SSukadev Bhattiprolu "EventCode": "0x2C050", 10343c22ba52SSukadev Bhattiprolu "EventName": "PM_DATA_GRP_PUMP_CPRED", 10353c22ba52SSukadev Bhattiprolu "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load" 10363c22ba52SSukadev Bhattiprolu }, 10373c22ba52SSukadev Bhattiprolu {, 10383c22ba52SSukadev Bhattiprolu "EventCode": "0xC0A4", 10393c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_FALSE_LHS", 10403c22ba52SSukadev Bhattiprolu "BriefDescription": "False LHS match detected" 10413c22ba52SSukadev Bhattiprolu }, 10423c22ba52SSukadev Bhattiprolu {, 10433c22ba52SSukadev Bhattiprolu "EventCode": "0x58A0", 10443c22ba52SSukadev Bhattiprolu "EventName": "PM_LINK_STACK_CORRECT", 10453c22ba52SSukadev Bhattiprolu "BriefDescription": "Link stack predicts right address" 10463c22ba52SSukadev Bhattiprolu }, 10473c22ba52SSukadev Bhattiprolu {, 10483c22ba52SSukadev Bhattiprolu "EventCode": "0x36886", 10493c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_SN_SX_I_DONE", 10509749adc3SSukadev Bhattiprolu "BriefDescription": "Snoop dispatched and went from Sx to Ix" 10513c22ba52SSukadev Bhattiprolu }, 10523c22ba52SSukadev Bhattiprolu {, 10533c22ba52SSukadev Bhattiprolu "EventCode": "0x4E04A", 10543c22ba52SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE", 10553c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 10563c22ba52SSukadev Bhattiprolu }, 10573c22ba52SSukadev Bhattiprolu {, 10583c22ba52SSukadev Bhattiprolu "EventCode": "0x2C12C", 10593c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL4_CYC", 10603c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load" 10613c22ba52SSukadev Bhattiprolu }, 10623c22ba52SSukadev Bhattiprolu {, 10633c22ba52SSukadev Bhattiprolu "EventCode": "0x4080", 10643c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L1", 10653c22ba52SSukadev Bhattiprolu "BriefDescription": "Instruction fetches from L1. L1 instruction hit" 10663c22ba52SSukadev Bhattiprolu }, 10673c22ba52SSukadev Bhattiprolu {, 10683c22ba52SSukadev Bhattiprolu "EventCode": "0xE898", 10693c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_TM_L1_HIT", 10703c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm hit in L1" 10713c22ba52SSukadev Bhattiprolu }, 10723c22ba52SSukadev Bhattiprolu {, 10733c22ba52SSukadev Bhattiprolu "EventCode": "0x260A0", 10743c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CO_MEM", 10753c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc)" 10763c22ba52SSukadev Bhattiprolu }, 10773c22ba52SSukadev Bhattiprolu {, 10783c22ba52SSukadev Bhattiprolu "EventCode": "0x16082", 10793c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_CASTOUT_MOD", 10803c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 Castouts - Modified (M,Mu,Me)" 10813c22ba52SSukadev Bhattiprolu }, 10823c22ba52SSukadev Bhattiprolu {, 10833c22ba52SSukadev Bhattiprolu "EventCode": "0xC09C", 10843c22ba52SSukadev Bhattiprolu "EventName": "PM_LS0_LAUNCH_HELD_PREF", 10853c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle" 10863c22ba52SSukadev Bhattiprolu }, 10873c22ba52SSukadev Bhattiprolu {, 10883c22ba52SSukadev Bhattiprolu "EventCode": "0xC8B8", 10893c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_LARX_STCX", 10903c22ba52SSukadev Bhattiprolu "BriefDescription": "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches" 10913c22ba52SSukadev Bhattiprolu }, 10923c22ba52SSukadev Bhattiprolu {, 10933c22ba52SSukadev Bhattiprolu "EventCode": "0x260A6", 10943c22ba52SSukadev Bhattiprolu "EventName": "PM_NON_TM_RST_SC", 10959749adc3SSukadev Bhattiprolu "BriefDescription": "Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated" 10963c22ba52SSukadev Bhattiprolu }, 10973c22ba52SSukadev Bhattiprolu {, 10983c22ba52SSukadev Bhattiprolu "EventCode": "0x3608A", 10993c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RTY_ST", 11003c22ba52SSukadev Bhattiprolu "BriefDescription": "RC retries on PB for any store from core (excludes DCBFs)" 11013c22ba52SSukadev Bhattiprolu }, 11023c22ba52SSukadev Bhattiprolu {, 11033c22ba52SSukadev Bhattiprolu "EventCode": "0x24040", 11043c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L2_MEPF", 11053c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)" 11063c22ba52SSukadev Bhattiprolu }, 11073c22ba52SSukadev Bhattiprolu {, 11083c22ba52SSukadev Bhattiprolu "EventCode": "0x209C", 11093c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAV_TBEGIN", 11103c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch time Favored tbegin" 11113c22ba52SSukadev Bhattiprolu }, 11123c22ba52SSukadev Bhattiprolu {, 11133c22ba52SSukadev Bhattiprolu "EventCode": "0x2D01E", 11143c22ba52SSukadev Bhattiprolu "EventName": "PM_ICT_NOSLOT_DISP_HELD_ISSQ", 11153c22ba52SSukadev Bhattiprolu "BriefDescription": "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full" 11163c22ba52SSukadev Bhattiprolu }, 11173c22ba52SSukadev Bhattiprolu {, 11183c22ba52SSukadev Bhattiprolu "EventCode": "0x50A4", 11193c22ba52SSukadev Bhattiprolu "EventName": "PM_FLUSH_MPRED", 11203c22ba52SSukadev Bhattiprolu "BriefDescription": "Branch mispredict flushes. Includes target and address misprecition" 11213c22ba52SSukadev Bhattiprolu }, 11223c22ba52SSukadev Bhattiprolu {, 11233c22ba52SSukadev Bhattiprolu "EventCode": "0x1504C", 11243c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_LL4", 11253c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request" 11263c22ba52SSukadev Bhattiprolu }, 11273c22ba52SSukadev Bhattiprolu {, 11283c22ba52SSukadev Bhattiprolu "EventCode": "0x268A4", 11293c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_LD_MISS", 11303c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Misses for demand LDs" 11313c22ba52SSukadev Bhattiprolu }, 11323c22ba52SSukadev Bhattiprolu {, 11333c22ba52SSukadev Bhattiprolu "EventCode": "0x26088", 11343c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_GRP_GUESS_CORRECT", 11353c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip)" 11363c22ba52SSukadev Bhattiprolu }, 11373c22ba52SSukadev Bhattiprolu {, 11383c22ba52SSukadev Bhattiprolu "EventCode": "0xD088", 11393c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_LDMX_FIN", 11403c22ba52SSukadev Bhattiprolu "BriefDescription": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])." 11413c22ba52SSukadev Bhattiprolu }, 11423c22ba52SSukadev Bhattiprolu {, 11433c22ba52SSukadev Bhattiprolu "EventCode": "0xE8B4", 11443c22ba52SSukadev Bhattiprolu "EventName": "PM_LS1_TM_DISALLOW", 11453c22ba52SSukadev Bhattiprolu "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it" 11463c22ba52SSukadev Bhattiprolu }, 11473c22ba52SSukadev Bhattiprolu {, 11483c22ba52SSukadev Bhattiprolu "EventCode": "0x1688C", 11493c22ba52SSukadev Bhattiprolu "EventName": "PM_RC_USAGE", 11503c22ba52SSukadev Bhattiprolu "BriefDescription": "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running" 11513c22ba52SSukadev Bhattiprolu }, 11523c22ba52SSukadev Bhattiprolu {, 11533c22ba52SSukadev Bhattiprolu "EventCode": "0x3F054", 11543c22ba52SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3MISS", 11553c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache" 11563c22ba52SSukadev Bhattiprolu }, 11573c22ba52SSukadev Bhattiprolu {, 11583c22ba52SSukadev Bhattiprolu "EventCode": "0x2608A", 11593c22ba52SSukadev Bhattiprolu "EventName": "PM_ISIDE_DISP_FAIL_ADDR", 11609749adc3SSukadev Bhattiprolu "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines)" 11613c22ba52SSukadev Bhattiprolu }, 11623c22ba52SSukadev Bhattiprolu {, 11633c22ba52SSukadev Bhattiprolu "EventCode": "0x50B4", 11643c22ba52SSukadev Bhattiprolu "EventName": "PM_TAGE_CORRECT_TAKEN_CMPL", 11653c22ba52SSukadev Bhattiprolu "BriefDescription": "The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only" 11663c22ba52SSukadev Bhattiprolu }, 11673c22ba52SSukadev Bhattiprolu {, 11683c22ba52SSukadev Bhattiprolu "EventCode": "0x2090", 11693c22ba52SSukadev Bhattiprolu "EventName": "PM_DISP_CLB_HELD_SB", 11703c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch/CLB Hold: Scoreboard" 11713c22ba52SSukadev Bhattiprolu }, 11723c22ba52SSukadev Bhattiprolu {, 11733c22ba52SSukadev Bhattiprolu "EventCode": "0xE0B0", 11743c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_NON_TX_CONFLICT", 11753c22ba52SSukadev Bhattiprolu "BriefDescription": "Non transactional conflict from LSU, gets reported to TEXASR" 11763c22ba52SSukadev Bhattiprolu }, 11773c22ba52SSukadev Bhattiprolu {, 11783c22ba52SSukadev Bhattiprolu "EventCode": "0x201E0", 11793c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_MEMORY", 11803c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load" 11813c22ba52SSukadev Bhattiprolu }, 11823c22ba52SSukadev Bhattiprolu {, 11833c22ba52SSukadev Bhattiprolu "EventCode": "0x368A2", 11843c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_L2_CO_MISS", 11853c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 CO miss" 11863c22ba52SSukadev Bhattiprolu }, 11873c22ba52SSukadev Bhattiprolu {, 11883c22ba52SSukadev Bhattiprolu "EventCode": "0x3608C", 11893c22ba52SSukadev Bhattiprolu "EventName": "PM_CO0_BUSY", 11903c22ba52SSukadev Bhattiprolu "BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)" 11913c22ba52SSukadev Bhattiprolu }, 11923c22ba52SSukadev Bhattiprolu {, 11933c22ba52SSukadev Bhattiprolu "EventCode": "0x2C122", 11943c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", 11953c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load" 11963c22ba52SSukadev Bhattiprolu }, 11973c22ba52SSukadev Bhattiprolu {, 11983c22ba52SSukadev Bhattiprolu "EventCode": "0x35154", 11993c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_CYC", 12003c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load" 12013c22ba52SSukadev Bhattiprolu }, 12023c22ba52SSukadev Bhattiprolu {, 12033c22ba52SSukadev Bhattiprolu "EventCode": "0x1D140", 12043c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L31_MOD_CYC", 12053c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load" 12063c22ba52SSukadev Bhattiprolu }, 12073c22ba52SSukadev Bhattiprolu {, 12083c22ba52SSukadev Bhattiprolu "EventCode": "0x4404A", 12093c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_FROM_OFF_CHIP_CACHE", 12103c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)" 12113c22ba52SSukadev Bhattiprolu }, 12123c22ba52SSukadev Bhattiprolu {, 12133c22ba52SSukadev Bhattiprolu "EventCode": "0x28AC", 12143c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_SELF", 12153c22ba52SSukadev Bhattiprolu "BriefDescription": "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally; a dcbf, dcbi, or icbi specify- ing a block that was previously accessed transactionally; a dcbst specifying a block that was previously written transactionally; or a tlbie that specifies a translation that was pre- viously used transactionally" 12163c22ba52SSukadev Bhattiprolu }, 12173c22ba52SSukadev Bhattiprolu {, 12183c22ba52SSukadev Bhattiprolu "EventCode": "0x45056", 12193c22ba52SSukadev Bhattiprolu "EventName": "PM_SCALAR_FLOP_CMPL", 12203c22ba52SSukadev Bhattiprolu "BriefDescription": "Scalar flop operation completed" 12213c22ba52SSukadev Bhattiprolu }, 12223c22ba52SSukadev Bhattiprolu {, 12233c22ba52SSukadev Bhattiprolu "EventCode": "0x16092", 12243c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LD_MISS_128B", 12253c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0)" 12263c22ba52SSukadev Bhattiprolu }, 12273c22ba52SSukadev Bhattiprolu {, 12283c22ba52SSukadev Bhattiprolu "EventCode": "0x2E014", 12293c22ba52SSukadev Bhattiprolu "EventName": "PM_STCX_FIN", 12303c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed" 12313c22ba52SSukadev Bhattiprolu }, 12323c22ba52SSukadev Bhattiprolu {, 12339749adc3SSukadev Bhattiprolu "EventCode": "0xD8AC", 12349749adc3SSukadev Bhattiprolu "EventName": "PM_LWSYNC", 1235123a039dSMichael Petlan "BriefDescription": "An lwsync instruction was decoded and transferred" 12363c22ba52SSukadev Bhattiprolu }, 12373c22ba52SSukadev Bhattiprolu {, 12383c22ba52SSukadev Bhattiprolu "EventCode": "0x2094", 12393c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_OUTER_TBEGIN", 12403c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion time outer tbegin" 12413c22ba52SSukadev Bhattiprolu }, 12423c22ba52SSukadev Bhattiprolu {, 12433c22ba52SSukadev Bhattiprolu "EventCode": "0x160B4", 12443c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_LCO_RTY", 12453c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 initiated LCO received retry on port 0 (can try 4 times)" 12463c22ba52SSukadev Bhattiprolu }, 12473c22ba52SSukadev Bhattiprolu {, 12483c22ba52SSukadev Bhattiprolu "EventCode": "0x36892", 12493c22ba52SSukadev Bhattiprolu "EventName": "PM_DSIDE_OTHER_64B_L2MEMACC", 12503c22ba52SSukadev Bhattiprolu "BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.e., number of times RC had to go to memory to get 'missing' 64B" 12513c22ba52SSukadev Bhattiprolu }, 12523c22ba52SSukadev Bhattiprolu {, 12533c22ba52SSukadev Bhattiprolu "EventCode": "0x20A8", 12543c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_FOOTPRINT_OVERFLOW", 12553c22ba52SSukadev Bhattiprolu "BriefDescription": "TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous" 12563c22ba52SSukadev Bhattiprolu }, 12573c22ba52SSukadev Bhattiprolu {, 12583c22ba52SSukadev Bhattiprolu "EventCode": "0x30018", 12593c22ba52SSukadev Bhattiprolu "EventName": "PM_ICT_NOSLOT_DISP_HELD_HB_FULL", 12603c22ba52SSukadev Bhattiprolu "BriefDescription": "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)" 12613c22ba52SSukadev Bhattiprolu }, 12623c22ba52SSukadev Bhattiprolu {, 12639749adc3SSukadev Bhattiprolu "EventCode": "0xC894", 12649749adc3SSukadev Bhattiprolu "EventName": "PM_LS1_UNALIGNED_LD", 12659749adc3SSukadev Bhattiprolu "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 12669749adc3SSukadev Bhattiprolu }, 12679749adc3SSukadev Bhattiprolu {, 12683c22ba52SSukadev Bhattiprolu "EventCode": "0x360A2", 12693c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_L2_CO_HIT", 12703c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 CO hits" 12713c22ba52SSukadev Bhattiprolu }, 12723c22ba52SSukadev Bhattiprolu {, 12733c22ba52SSukadev Bhattiprolu "EventCode": "0x36092", 12743c22ba52SSukadev Bhattiprolu "EventName": "PM_DSIDE_L2MEMACC", 12753c22ba52SSukadev Bhattiprolu "BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.e., total memory accesses by RCs" 12763c22ba52SSukadev Bhattiprolu }, 12773c22ba52SSukadev Bhattiprolu {, 12783c22ba52SSukadev Bhattiprolu "EventCode": "0x10138", 12793c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_BR_2PATH", 12803c22ba52SSukadev Bhattiprolu "BriefDescription": "marked branches which are not strongly biased" 12813c22ba52SSukadev Bhattiprolu }, 12823c22ba52SSukadev Bhattiprolu {, 12833c22ba52SSukadev Bhattiprolu "EventCode": "0x2884", 12843c22ba52SSukadev Bhattiprolu "EventName": "PM_ISYNC", 12853c22ba52SSukadev Bhattiprolu "BriefDescription": "Isync completion count per thread" 12863c22ba52SSukadev Bhattiprolu }, 12873c22ba52SSukadev Bhattiprolu {, 12883c22ba52SSukadev Bhattiprolu "EventCode": "0x16882", 12893c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_CASTOUT_SHR", 12903c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 Castouts - Shared (Tx,Sx)" 12913c22ba52SSukadev Bhattiprolu }, 12923c22ba52SSukadev Bhattiprolu {, 12933c22ba52SSukadev Bhattiprolu "EventCode": "0x26092", 12943c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LD_MISS_64B", 12953c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.e., M=1)" 12963c22ba52SSukadev Bhattiprolu }, 12973c22ba52SSukadev Bhattiprolu {, 12983c22ba52SSukadev Bhattiprolu "EventCode": "0x26080", 12993c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LD_MISS", 13003c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-Side Load dispatches that were an L2 miss for this thread" 13013c22ba52SSukadev Bhattiprolu }, 13023c22ba52SSukadev Bhattiprolu {, 13033c22ba52SSukadev Bhattiprolu "EventCode": "0x3D14C", 13043c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DMEM", 13053c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load" 13063c22ba52SSukadev Bhattiprolu }, 13073c22ba52SSukadev Bhattiprolu {, 13083c22ba52SSukadev Bhattiprolu "EventCode": "0x100FA", 13093c22ba52SSukadev Bhattiprolu "EventName": "PM_ANY_THRD_RUN_CYC", 13103c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which at least one thread has the run latch set" 13113c22ba52SSukadev Bhattiprolu }, 13123c22ba52SSukadev Bhattiprolu {, 13133c22ba52SSukadev Bhattiprolu "EventCode": "0x2C12A", 13143c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_RMEM_CYC", 13153c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load" 13163c22ba52SSukadev Bhattiprolu }, 13173c22ba52SSukadev Bhattiprolu {, 13183c22ba52SSukadev Bhattiprolu "EventCode": "0x25048", 13193c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_LMEM", 13203c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request" 13213c22ba52SSukadev Bhattiprolu }, 13223c22ba52SSukadev Bhattiprolu {, 13233c22ba52SSukadev Bhattiprolu "EventCode": "0xD8A8", 13243c22ba52SSukadev Bhattiprolu "EventName": "PM_ISLB_MISS", 1325e795dd42SSukadev Bhattiprolu "BriefDescription": "Instruction SLB Miss - Total of all segment sizes" 13263c22ba52SSukadev Bhattiprolu }, 13273c22ba52SSukadev Bhattiprolu {, 1328e795dd42SSukadev Bhattiprolu "EventCode": "0x368AE", 1329e795dd42SSukadev Bhattiprolu "EventName": "PM_L3_P1_CO_RTY", 1330e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 CO received retry port 1 (memory only), every retry counted" 13313c22ba52SSukadev Bhattiprolu }, 13323c22ba52SSukadev Bhattiprolu {, 13333c22ba52SSukadev Bhattiprolu "EventCode": "0x260A2", 13343c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CI_HIT", 13353c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Castins Hit (total count)" 13363c22ba52SSukadev Bhattiprolu }, 13373c22ba52SSukadev Bhattiprolu {, 13383c22ba52SSukadev Bhattiprolu "EventCode": "0x44054", 13393c22ba52SSukadev Bhattiprolu "EventName": "PM_VECTOR_LD_CMPL", 13403c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of vector load instructions completed" 13413c22ba52SSukadev Bhattiprolu }, 13423c22ba52SSukadev Bhattiprolu {, 13433c22ba52SSukadev Bhattiprolu "EventCode": "0x1E05C", 13443c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_NESTED_TBEGIN", 13453c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT" 13463c22ba52SSukadev Bhattiprolu }, 13473c22ba52SSukadev Bhattiprolu {, 1348e795dd42SSukadev Bhattiprolu "EventCode": "0xC084", 1349e795dd42SSukadev Bhattiprolu "EventName": "PM_LS2_LD_VECTOR_FIN", 13509749adc3SSukadev Bhattiprolu "BriefDescription": "LS2 finished load vector op" 1351e795dd42SSukadev Bhattiprolu }, 1352e795dd42SSukadev Bhattiprolu {, 13533c22ba52SSukadev Bhattiprolu "EventCode": "0x1608E", 13543c22ba52SSukadev Bhattiprolu "EventName": "PM_ST_CAUSED_FAIL", 13553c22ba52SSukadev Bhattiprolu "BriefDescription": "Non-TM Store caused any thread to fail" 13563c22ba52SSukadev Bhattiprolu }, 13573c22ba52SSukadev Bhattiprolu {, 13583c22ba52SSukadev Bhattiprolu "EventCode": "0x3080", 13593c22ba52SSukadev Bhattiprolu "EventName": "PM_ISU0_ISS_HOLD_ALL", 13603c22ba52SSukadev Bhattiprolu "BriefDescription": "All ISU rejects" 13613c22ba52SSukadev Bhattiprolu }, 13623c22ba52SSukadev Bhattiprolu {, 13633c22ba52SSukadev Bhattiprolu "EventCode": "0x1515A", 13643c22ba52SSukadev Bhattiprolu "EventName": "PM_SYNC_MRK_L2MISS", 13653c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt" 13663c22ba52SSukadev Bhattiprolu }, 13673c22ba52SSukadev Bhattiprolu {, 13683c22ba52SSukadev Bhattiprolu "EventCode": "0x26892", 13693c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_ST_MISS_64B", 13703c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.e., M=1)" 13713c22ba52SSukadev Bhattiprolu }, 13723c22ba52SSukadev Bhattiprolu {, 13733c22ba52SSukadev Bhattiprolu "EventCode": "0x2688C", 13743c22ba52SSukadev Bhattiprolu "EventName": "PM_CO_USAGE", 13753c22ba52SSukadev Bhattiprolu "BriefDescription": "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running" 13763c22ba52SSukadev Bhattiprolu }, 13773c22ba52SSukadev Bhattiprolu {, 13783c22ba52SSukadev Bhattiprolu "EventCode": "0x48B8", 13793c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_MPRED_TAKEN_TA", 13803c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event." 13813c22ba52SSukadev Bhattiprolu }, 13823c22ba52SSukadev Bhattiprolu {, 13833c22ba52SSukadev Bhattiprolu "EventCode": "0x50B0", 13843c22ba52SSukadev Bhattiprolu "EventName": "PM_BTAC_BAD_RESULT", 13853c22ba52SSukadev Bhattiprolu "BriefDescription": "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen" 13863c22ba52SSukadev Bhattiprolu }, 13873c22ba52SSukadev Bhattiprolu {, 13883c22ba52SSukadev Bhattiprolu "EventCode": "0xD888", 13893c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU1_LDMX_FIN", 13903c22ba52SSukadev Bhattiprolu "BriefDescription": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])." 13913c22ba52SSukadev Bhattiprolu }, 13923c22ba52SSukadev Bhattiprolu {, 13933c22ba52SSukadev Bhattiprolu "EventCode": "0x58B4", 13943c22ba52SSukadev Bhattiprolu "EventName": "PM_TAGE_CORRECT", 13953c22ba52SSukadev Bhattiprolu "BriefDescription": "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time" 13963c22ba52SSukadev Bhattiprolu }, 13973c22ba52SSukadev Bhattiprolu {, 13983c22ba52SSukadev Bhattiprolu "EventCode": "0x3688C", 13993c22ba52SSukadev Bhattiprolu "EventName": "PM_SN_USAGE", 14003c22ba52SSukadev Bhattiprolu "BriefDescription": "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running" 14013c22ba52SSukadev Bhattiprolu }, 14023c22ba52SSukadev Bhattiprolu {, 14039749adc3SSukadev Bhattiprolu "EventCode": "0x36084", 14049749adc3SSukadev Bhattiprolu "EventName": "PM_L2_RCST_DISP", 14059749adc3SSukadev Bhattiprolu "BriefDescription": "All D-side store dispatch attempts for this thread" 14069749adc3SSukadev Bhattiprolu }, 14079749adc3SSukadev Bhattiprolu {, 14083c22ba52SSukadev Bhattiprolu "EventCode": "0x46084", 14093c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RCST_DISP_FAIL_OTHER", 14103c22ba52SSukadev Bhattiprolu "BriefDescription": "All D-side store dispatch attempts for this thread that failed due to reason other than address collision" 14113c22ba52SSukadev Bhattiprolu }, 14123c22ba52SSukadev Bhattiprolu {, 14133c22ba52SSukadev Bhattiprolu "EventCode": "0xF0AC", 14143c22ba52SSukadev Bhattiprolu "EventName": "PM_DC_PREF_STRIDED_CONF", 14153c22ba52SSukadev Bhattiprolu "BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software." 14163c22ba52SSukadev Bhattiprolu }, 14173c22ba52SSukadev Bhattiprolu {, 14183c22ba52SSukadev Bhattiprolu "EventCode": "0x45054", 14193c22ba52SSukadev Bhattiprolu "EventName": "PM_FMA_CMPL", 14203c22ba52SSukadev Bhattiprolu "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. " 14213c22ba52SSukadev Bhattiprolu }, 14223c22ba52SSukadev Bhattiprolu {, 14233c22ba52SSukadev Bhattiprolu "EventCode": "0x201E8", 14243c22ba52SSukadev Bhattiprolu "EventName": "PM_THRESH_EXC_512", 14253c22ba52SSukadev Bhattiprolu "BriefDescription": "Threshold counter exceeded a value of 512" 14263c22ba52SSukadev Bhattiprolu }, 14273c22ba52SSukadev Bhattiprolu {, 14283c22ba52SSukadev Bhattiprolu "EventCode": "0x36080", 14293c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_INST", 14309749adc3SSukadev Bhattiprolu "BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread" 14313c22ba52SSukadev Bhattiprolu }, 14323c22ba52SSukadev Bhattiprolu {, 14333c22ba52SSukadev Bhattiprolu "EventCode": "0x3504C", 14343c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_DL4", 14353c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request" 14363c22ba52SSukadev Bhattiprolu }, 14373c22ba52SSukadev Bhattiprolu {, 14383c22ba52SSukadev Bhattiprolu "EventCode": "0xD890", 14393c22ba52SSukadev Bhattiprolu "EventName": "PM_LS1_DC_COLLISIONS", 14403c22ba52SSukadev Bhattiprolu "BriefDescription": "Read-write data cache collisions" 14413c22ba52SSukadev Bhattiprolu }, 14423c22ba52SSukadev Bhattiprolu {, 14433c22ba52SSukadev Bhattiprolu "EventCode": "0x1688A", 14443c22ba52SSukadev Bhattiprolu "EventName": "PM_ISIDE_DISP", 14459749adc3SSukadev Bhattiprolu "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread" 14463c22ba52SSukadev Bhattiprolu }, 14473c22ba52SSukadev Bhattiprolu {, 14483c22ba52SSukadev Bhattiprolu "EventCode": "0x468AA", 14493c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_CO_L31", 14503c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO to L3.1 (LCO) port 1 with or without data" 14513c22ba52SSukadev Bhattiprolu }, 14523c22ba52SSukadev Bhattiprolu {, 14533c22ba52SSukadev Bhattiprolu "EventCode": "0x28B0", 14543c22ba52SSukadev Bhattiprolu "EventName": "PM_DISP_HELD_TBEGIN", 14553c22ba52SSukadev Bhattiprolu "BriefDescription": "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes" 14563c22ba52SSukadev Bhattiprolu }, 14573c22ba52SSukadev Bhattiprolu {, 14583c22ba52SSukadev Bhattiprolu "EventCode": "0xE8A0", 14593c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_TM_L1_MISS", 14603c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm L1 miss" 14613c22ba52SSukadev Bhattiprolu }, 14623c22ba52SSukadev Bhattiprolu {, 14633c22ba52SSukadev Bhattiprolu "EventCode": "0x2C05E", 14643c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_GRP_PUMP_MPRED", 14653c22ba52SSukadev Bhattiprolu "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)" 14663c22ba52SSukadev Bhattiprolu }, 14673c22ba52SSukadev Bhattiprolu {, 14683c22ba52SSukadev Bhattiprolu "EventCode": "0xC8BC", 14693c22ba52SSukadev Bhattiprolu "EventName": "PM_STCX_SUCCESS_CMPL", 14703c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of stcx instructions that completed successfully" 14713c22ba52SSukadev Bhattiprolu }, 14723c22ba52SSukadev Bhattiprolu {, 14733c22ba52SSukadev Bhattiprolu "EventCode": "0xE098", 14743c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU2_TM_L1_HIT", 14753c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm hit in L1" 14763c22ba52SSukadev Bhattiprolu }, 14773c22ba52SSukadev Bhattiprolu {, 14789749adc3SSukadev Bhattiprolu "EventCode": "0xE0B8", 14799749adc3SSukadev Bhattiprolu "EventName": "PM_LS2_TM_DISALLOW", 14809749adc3SSukadev Bhattiprolu "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it" 14819749adc3SSukadev Bhattiprolu }, 14829749adc3SSukadev Bhattiprolu {, 14833c22ba52SSukadev Bhattiprolu "EventCode": "0x44044", 14843c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L31_ECO_MOD", 14853c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)" 14863c22ba52SSukadev Bhattiprolu }, 14873c22ba52SSukadev Bhattiprolu {, 14883c22ba52SSukadev Bhattiprolu "EventCode": "0x16886", 14893c22ba52SSukadev Bhattiprolu "EventName": "PM_CO_DISP_FAIL", 14903c22ba52SSukadev Bhattiprolu "BriefDescription": "CO dispatch failed due to all CO machines being busy" 14913c22ba52SSukadev Bhattiprolu }, 14923c22ba52SSukadev Bhattiprolu {, 14933c22ba52SSukadev Bhattiprolu "EventCode": "0x3D146", 14943c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT", 14953c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load" 14963c22ba52SSukadev Bhattiprolu }, 14973c22ba52SSukadev Bhattiprolu {, 14983c22ba52SSukadev Bhattiprolu "EventCode": "0x16892", 14993c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_ST_MISS_128B", 15003c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0)" 15013c22ba52SSukadev Bhattiprolu }, 15023c22ba52SSukadev Bhattiprolu {, 15033c22ba52SSukadev Bhattiprolu "EventCode": "0x26890", 15043c22ba52SSukadev Bhattiprolu "EventName": "PM_ISIDE_L2MEMACC", 15053c22ba52SSukadev Bhattiprolu "BriefDescription": "Valid when first beat of data comes in for an I-side fetch where data came from memory" 15063c22ba52SSukadev Bhattiprolu }, 15073c22ba52SSukadev Bhattiprolu {, 15083c22ba52SSukadev Bhattiprolu "EventCode": "0xD094", 15093c22ba52SSukadev Bhattiprolu "EventName": "PM_LS2_DC_COLLISIONS", 15103c22ba52SSukadev Bhattiprolu "BriefDescription": "Read-write data cache collisions" 15113c22ba52SSukadev Bhattiprolu }, 15123c22ba52SSukadev Bhattiprolu {, 15133c22ba52SSukadev Bhattiprolu "EventCode": "0x3C05E", 15143c22ba52SSukadev Bhattiprolu "EventName": "PM_MEM_RWITM", 15153c22ba52SSukadev Bhattiprolu "BriefDescription": "Memory Read With Intent to Modify for this thread" 15163c22ba52SSukadev Bhattiprolu }, 15173c22ba52SSukadev Bhattiprolu {, 15183c22ba52SSukadev Bhattiprolu "EventCode": "0xC090", 15193c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_STCX", 15203c22ba52SSukadev Bhattiprolu "BriefDescription": "STCX sent to nest, i.e. total" 15213c22ba52SSukadev Bhattiprolu }, 15223c22ba52SSukadev Bhattiprolu {, 15233c22ba52SSukadev Bhattiprolu "EventCode": "0x2C120", 15243c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT", 15253c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load" 15263c22ba52SSukadev Bhattiprolu }, 15273c22ba52SSukadev Bhattiprolu {, 15283c22ba52SSukadev Bhattiprolu "EventCode": "0x36086", 15293c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RC_ST_DONE", 15309749adc3SSukadev Bhattiprolu "BriefDescription": "Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared state)" 15313c22ba52SSukadev Bhattiprolu }, 15323c22ba52SSukadev Bhattiprolu {, 15333c22ba52SSukadev Bhattiprolu "EventCode": "0xE8AC", 15343c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_TX_CONFLICT", 15353c22ba52SSukadev Bhattiprolu "BriefDescription": "Transactional conflict from LSU, gets reported to TEXASR" 15363c22ba52SSukadev Bhattiprolu }, 15373c22ba52SSukadev Bhattiprolu {, 15383c22ba52SSukadev Bhattiprolu "EventCode": "0x48A8", 15393c22ba52SSukadev Bhattiprolu "EventName": "PM_DECODE_FUSION_LD_ST_DISP", 15403c22ba52SSukadev Bhattiprolu "BriefDescription": "32-bit displacement D-form and 16-bit displacement X-form" 15413c22ba52SSukadev Bhattiprolu }, 15423c22ba52SSukadev Bhattiprolu {, 15433c22ba52SSukadev Bhattiprolu "EventCode": "0x3D144", 15443c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC", 15453c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load" 15463c22ba52SSukadev Bhattiprolu }, 15473c22ba52SSukadev Bhattiprolu {, 15483c22ba52SSukadev Bhattiprolu "EventCode": "0x44046", 15493c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L21_MOD", 15503c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)" 15513c22ba52SSukadev Bhattiprolu }, 15523c22ba52SSukadev Bhattiprolu {, 15533c22ba52SSukadev Bhattiprolu "EventCode": "0x40B0", 15543c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_PRED_TAKEN_CR", 15553c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches" 15563c22ba52SSukadev Bhattiprolu }, 15573c22ba52SSukadev Bhattiprolu {, 15583c22ba52SSukadev Bhattiprolu "EventCode": "0x15040", 15593c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT", 15603c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request" 15613c22ba52SSukadev Bhattiprolu }, 15623c22ba52SSukadev Bhattiprolu {, 15639749adc3SSukadev Bhattiprolu "EventCode": "0x460A6", 15649749adc3SSukadev Bhattiprolu "EventName": "PM_RD_FORMING_SC", 15659749adc3SSukadev Bhattiprolu "BriefDescription": "Doesn't occur" 15669749adc3SSukadev Bhattiprolu }, 15679749adc3SSukadev Bhattiprolu {, 15683c22ba52SSukadev Bhattiprolu "EventCode": "0x35042", 15693c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT", 15703c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request" 15713c22ba52SSukadev Bhattiprolu }, 15723c22ba52SSukadev Bhattiprolu {, 15733c22ba52SSukadev Bhattiprolu "EventCode": "0xF898", 15743c22ba52SSukadev Bhattiprolu "EventName": "PM_XLATE_RADIX_MODE", 15753c22ba52SSukadev Bhattiprolu "BriefDescription": "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)" 15763c22ba52SSukadev Bhattiprolu }, 15773c22ba52SSukadev Bhattiprolu {, 15783c22ba52SSukadev Bhattiprolu "EventCode": "0x2D142", 15793c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_MEPF", 15803c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load" 15813c22ba52SSukadev Bhattiprolu }, 15823c22ba52SSukadev Bhattiprolu {, 15833c22ba52SSukadev Bhattiprolu "EventCode": "0x160B0", 15843c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_NODE_PUMP", 15853c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF sent with nodal scope port 0, counts even retried requests" 15863c22ba52SSukadev Bhattiprolu }, 15873c22ba52SSukadev Bhattiprolu {, 15883c22ba52SSukadev Bhattiprolu "EventCode": "0xD88C", 15893c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_LDMX_FIN", 15903c22ba52SSukadev Bhattiprolu "BriefDescription": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])." 15913c22ba52SSukadev Bhattiprolu }, 15923c22ba52SSukadev Bhattiprolu {, 15933c22ba52SSukadev Bhattiprolu "EventCode": "0x36882", 15943c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LD_HIT", 15959749adc3SSukadev Bhattiprolu "BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits" 15963c22ba52SSukadev Bhattiprolu }, 15973c22ba52SSukadev Bhattiprolu {, 15983c22ba52SSukadev Bhattiprolu "EventCode": "0x168AC", 15993c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CI_USAGE", 16003c22ba52SSukadev Bhattiprolu "BriefDescription": "Rotating sample of 16 CI or CO actives" 16013c22ba52SSukadev Bhattiprolu }, 16023c22ba52SSukadev Bhattiprolu {, 16033c22ba52SSukadev Bhattiprolu "EventCode": "0x20134", 16043c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_FXU_FIN", 16053c22ba52SSukadev Bhattiprolu "BriefDescription": "fxu marked instr finish" 16063c22ba52SSukadev Bhattiprolu }, 16073c22ba52SSukadev Bhattiprolu {, 16083c22ba52SSukadev Bhattiprolu "EventCode": "0x4608E", 16093c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_CAP_OVERFLOW", 16103c22ba52SSukadev Bhattiprolu "BriefDescription": "TM Footprint Capacity Overflow" 16113c22ba52SSukadev Bhattiprolu }, 16123c22ba52SSukadev Bhattiprolu {, 16133c22ba52SSukadev Bhattiprolu "EventCode": "0x4F05C", 16143c22ba52SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L2_PTE_FROM_L3MISS", 16153c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache" 16163c22ba52SSukadev Bhattiprolu }, 16173c22ba52SSukadev Bhattiprolu {, 16183c22ba52SSukadev Bhattiprolu "EventCode": "0x40014", 16193c22ba52SSukadev Bhattiprolu "EventName": "PM_PROBE_NOP_DISP", 16203c22ba52SSukadev Bhattiprolu "BriefDescription": "ProbeNops dispatched" 16213c22ba52SSukadev Bhattiprolu }, 16223c22ba52SSukadev Bhattiprolu {, 16233c22ba52SSukadev Bhattiprolu "EventCode": "0x10052", 16243c22ba52SSukadev Bhattiprolu "EventName": "PM_GRP_PUMP_MPRED_RTY", 16253c22ba52SSukadev Bhattiprolu "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" 16263c22ba52SSukadev Bhattiprolu }, 16273c22ba52SSukadev Bhattiprolu {, 16283c22ba52SSukadev Bhattiprolu "EventCode": "0x2505E", 16293c22ba52SSukadev Bhattiprolu "EventName": "PM_BACK_BR_CMPL", 16303c22ba52SSukadev Bhattiprolu "BriefDescription": "Branch instruction completed with a target address less than current instruction address" 16313c22ba52SSukadev Bhattiprolu }, 16323c22ba52SSukadev Bhattiprolu {, 16333c22ba52SSukadev Bhattiprolu "EventCode": "0x2688A", 16343c22ba52SSukadev Bhattiprolu "EventName": "PM_ISIDE_DISP_FAIL_OTHER", 16359749adc3SSukadev Bhattiprolu "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines)" 16363c22ba52SSukadev Bhattiprolu }, 16373c22ba52SSukadev Bhattiprolu {, 16383c22ba52SSukadev Bhattiprolu "EventCode": "0x2001A", 16393c22ba52SSukadev Bhattiprolu "EventName": "PM_NTC_ALL_FIN", 1640e795dd42SSukadev Bhattiprolu "BriefDescription": "Cycles after instruction finished to instruction completed." 16413c22ba52SSukadev Bhattiprolu }, 16423c22ba52SSukadev Bhattiprolu {, 16433c22ba52SSukadev Bhattiprolu "EventCode": "0x3005A", 16443c22ba52SSukadev Bhattiprolu "EventName": "PM_ISQ_0_8_ENTRIES", 16453c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread" 16463c22ba52SSukadev Bhattiprolu }, 16473c22ba52SSukadev Bhattiprolu {, 16483c22ba52SSukadev Bhattiprolu "EventCode": "0x3515E", 16493c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_BACK_BR_CMPL", 16503c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked branch instruction completed with a target address less than current instruction address" 16513c22ba52SSukadev Bhattiprolu }, 16523c22ba52SSukadev Bhattiprolu {, 16533c22ba52SSukadev Bhattiprolu "EventCode": "0xF890", 16543c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU1_L1_CAM_CANCEL", 16553c22ba52SSukadev Bhattiprolu "BriefDescription": "ls1 l1 tm cam cancel" 16563c22ba52SSukadev Bhattiprolu }, 16573c22ba52SSukadev Bhattiprolu {, 1658e795dd42SSukadev Bhattiprolu "EventCode": "0x268AE", 1659e795dd42SSukadev Bhattiprolu "EventName": "PM_L3_P3_PF_RTY", 1660e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 PF received retry port 3, every retry counted" 1661e795dd42SSukadev Bhattiprolu }, 1662e795dd42SSukadev Bhattiprolu {, 16633c22ba52SSukadev Bhattiprolu "EventCode": "0xE884", 16643c22ba52SSukadev Bhattiprolu "EventName": "PM_LS1_ERAT_MISS_PREF", 16653c22ba52SSukadev Bhattiprolu "BriefDescription": "LS1 Erat miss due to prefetch" 16663c22ba52SSukadev Bhattiprolu }, 16673c22ba52SSukadev Bhattiprolu {, 16683c22ba52SSukadev Bhattiprolu "EventCode": "0xE89C", 16693c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU1_TM_L1_MISS", 16703c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm L1 miss" 16713c22ba52SSukadev Bhattiprolu }, 16723c22ba52SSukadev Bhattiprolu {, 16733c22ba52SSukadev Bhattiprolu "EventCode": "0x28A8", 16743c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_CONF_NON_TM", 16753c22ba52SSukadev Bhattiprolu "BriefDescription": "TM aborted because a conflict occurred with a non-transactional access by another processor" 16763c22ba52SSukadev Bhattiprolu }, 16773c22ba52SSukadev Bhattiprolu {, 16783c22ba52SSukadev Bhattiprolu "EventCode": "0x16890", 16793c22ba52SSukadev Bhattiprolu "EventName": "PM_L1PF_L2MEMACC", 16803c22ba52SSukadev Bhattiprolu "BriefDescription": "Valid when first beat of data comes in for an L1PF where data came from memory" 16813c22ba52SSukadev Bhattiprolu }, 16823c22ba52SSukadev Bhattiprolu {, 16833c22ba52SSukadev Bhattiprolu "EventCode": "0x4504C", 16843c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_DMEM", 16853c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request" 16863c22ba52SSukadev Bhattiprolu }, 16873c22ba52SSukadev Bhattiprolu {, 16883c22ba52SSukadev Bhattiprolu "EventCode": "0x1002E", 16893c22ba52SSukadev Bhattiprolu "EventName": "PM_LMQ_MERGE", 16903c22ba52SSukadev Bhattiprolu "BriefDescription": "A demand miss collides with a prefetch for the same line" 16913c22ba52SSukadev Bhattiprolu }, 16923c22ba52SSukadev Bhattiprolu {, 16933c22ba52SSukadev Bhattiprolu "EventCode": "0x160B6", 16943c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_WI0_BUSY", 1695e795dd42SSukadev Bhattiprolu "BriefDescription": "Rotating sample of 8 WI valid (duplicate)" 16963c22ba52SSukadev Bhattiprolu }, 16973c22ba52SSukadev Bhattiprolu {, 16983c22ba52SSukadev Bhattiprolu "EventCode": "0x368AC", 16993c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CO0_BUSY", 17003c22ba52SSukadev Bhattiprolu "BriefDescription": "Lifetime, sample of CO machine 0 valid" 17013c22ba52SSukadev Bhattiprolu }, 17023c22ba52SSukadev Bhattiprolu {, 17033c22ba52SSukadev Bhattiprolu "EventCode": "0x2E040", 17043c22ba52SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_L2_MEPF", 17053c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 17063c22ba52SSukadev Bhattiprolu }, 17073c22ba52SSukadev Bhattiprolu {, 17083c22ba52SSukadev Bhattiprolu "EventCode": "0x1D152", 17093c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL4", 17103c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load" 17113c22ba52SSukadev Bhattiprolu }, 17123c22ba52SSukadev Bhattiprolu {, 17133c22ba52SSukadev Bhattiprolu "EventCode": "0x46880", 17143c22ba52SSukadev Bhattiprolu "EventName": "PM_ISIDE_MRU_TOUCH", 17159749adc3SSukadev Bhattiprolu "BriefDescription": "I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands sent to the L2 for this thread" 17163c22ba52SSukadev Bhattiprolu }, 17173c22ba52SSukadev Bhattiprolu {, 17189749adc3SSukadev Bhattiprolu "EventCode": "0x508C", 17199749adc3SSukadev Bhattiprolu "EventName": "PM_SHL_CREATED", 17209749adc3SSukadev Bhattiprolu "BriefDescription": "Store-Hit-Load Table Entry Created" 17213c22ba52SSukadev Bhattiprolu }, 17223c22ba52SSukadev Bhattiprolu {, 17233c22ba52SSukadev Bhattiprolu "EventCode": "0x50B8", 17243c22ba52SSukadev Bhattiprolu "EventName": "PM_TAGE_OVERRIDE_WRONG", 17253c22ba52SSukadev Bhattiprolu "BriefDescription": "The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only" 17263c22ba52SSukadev Bhattiprolu }, 17273c22ba52SSukadev Bhattiprolu {, 17283c22ba52SSukadev Bhattiprolu "EventCode": "0x160AE", 17293c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_PF_RTY", 17303c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF received retry port 0, every retry counted" 17313c22ba52SSukadev Bhattiprolu }, 17323c22ba52SSukadev Bhattiprolu {, 17333c22ba52SSukadev Bhattiprolu "EventCode": "0x268B2", 17343c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_LOC_GUESS_WRONG", 17359749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected LNS, but was wrong" 17363c22ba52SSukadev Bhattiprolu }, 17373c22ba52SSukadev Bhattiprolu {, 17383c22ba52SSukadev Bhattiprolu "EventCode": "0x36088", 17393c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_SYS_GUESS_CORRECT", 17403c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)" 17413c22ba52SSukadev Bhattiprolu }, 17423c22ba52SSukadev Bhattiprolu {, 1743e795dd42SSukadev Bhattiprolu "EventCode": "0x260AE", 1744e795dd42SSukadev Bhattiprolu "EventName": "PM_L3_P2_PF_RTY", 1745e795dd42SSukadev Bhattiprolu "BriefDescription": "L3 PF received retry port 2, every retry counted" 17463c22ba52SSukadev Bhattiprolu }, 17473c22ba52SSukadev Bhattiprolu {, 17489749adc3SSukadev Bhattiprolu "EventCode": "0xD8B0", 17499749adc3SSukadev Bhattiprolu "EventName": "PM_PTESYNC", 1750123a039dSMichael Petlan "BriefDescription": "A ptesync instruction was counted when the instruction is decoded and transmitted" 17519749adc3SSukadev Bhattiprolu }, 17529749adc3SSukadev Bhattiprolu {, 17533c22ba52SSukadev Bhattiprolu "EventCode": "0x26086", 17543c22ba52SSukadev Bhattiprolu "EventName": "PM_CO_TM_SC_FOOTPRINT", 17553c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus" 17563c22ba52SSukadev Bhattiprolu }, 17573c22ba52SSukadev Bhattiprolu {, 17583c22ba52SSukadev Bhattiprolu "EventCode": "0x1E05A", 17593c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_ANY_SYNC", 17603c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete" 17613c22ba52SSukadev Bhattiprolu }, 17623c22ba52SSukadev Bhattiprolu {, 17633c22ba52SSukadev Bhattiprolu "EventCode": "0xF090", 17643c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_L1_CAM_CANCEL", 17653c22ba52SSukadev Bhattiprolu "BriefDescription": "ls0 l1 tm cam cancel" 17663c22ba52SSukadev Bhattiprolu }, 17673c22ba52SSukadev Bhattiprolu {, 17683c22ba52SSukadev Bhattiprolu "EventCode": "0xC0A8", 17693c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_CI", 17703c22ba52SSukadev Bhattiprolu "BriefDescription": "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited" 17713c22ba52SSukadev Bhattiprolu }, 17723c22ba52SSukadev Bhattiprolu {, 17733c22ba52SSukadev Bhattiprolu "EventCode": "0x20AC", 17743c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAIL_CONF_TM", 17753c22ba52SSukadev Bhattiprolu "BriefDescription": "TM aborted because a conflict occurred with another transaction." 17763c22ba52SSukadev Bhattiprolu }, 17773c22ba52SSukadev Bhattiprolu {, 17783c22ba52SSukadev Bhattiprolu "EventCode": "0x588C", 17793c22ba52SSukadev Bhattiprolu "EventName": "PM_SHL_ST_DEP_CREATED", 17803c22ba52SSukadev Bhattiprolu "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled" 17813c22ba52SSukadev Bhattiprolu }, 17823c22ba52SSukadev Bhattiprolu {, 1783e795dd42SSukadev Bhattiprolu "EventCode": "0x46882", 1784e795dd42SSukadev Bhattiprolu "EventName": "PM_L2_ST_HIT", 1785e795dd42SSukadev Bhattiprolu "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits" 1786e795dd42SSukadev Bhattiprolu }, 1787e795dd42SSukadev Bhattiprolu {, 17883c22ba52SSukadev Bhattiprolu "EventCode": "0x360AC", 17893c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_SN0_BUSY", 17903c22ba52SSukadev Bhattiprolu "BriefDescription": "Lifetime, sample of snooper machine 0 valid" 17913c22ba52SSukadev Bhattiprolu }, 17923c22ba52SSukadev Bhattiprolu {, 17933c22ba52SSukadev Bhattiprolu "EventCode": "0x3005C", 17943c22ba52SSukadev Bhattiprolu "EventName": "PM_BFU_BUSY", 17953c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity" 17963c22ba52SSukadev Bhattiprolu }, 17973c22ba52SSukadev Bhattiprolu {, 17983c22ba52SSukadev Bhattiprolu "EventCode": "0x48A0", 17993c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_PRED_PCACHE", 18003c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional branch completed that used pattern cache prediction" 18013c22ba52SSukadev Bhattiprolu }, 18023c22ba52SSukadev Bhattiprolu {, 18033c22ba52SSukadev Bhattiprolu "EventCode": "0x26880", 18043c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_ST_MISS", 18053c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-Side Store dispatches that were an L2 miss for this thread" 18063c22ba52SSukadev Bhattiprolu }, 18073c22ba52SSukadev Bhattiprolu {, 18089749adc3SSukadev Bhattiprolu "EventCode": "0xF8B4", 18099749adc3SSukadev Bhattiprolu "EventName": "PM_DC_PREF_XCONS_ALLOC", 18109749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch" 18119749adc3SSukadev Bhattiprolu }, 18129749adc3SSukadev Bhattiprolu {, 18133c22ba52SSukadev Bhattiprolu "EventCode": "0x35048", 18143c22ba52SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_DL2L3_SHR", 18153c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request" 18163c22ba52SSukadev Bhattiprolu }, 18173c22ba52SSukadev Bhattiprolu {, 18183c22ba52SSukadev Bhattiprolu "EventCode": "0x260A8", 18193c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF_HIT_L3", 18203c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF hit in L3 (abandoned)" 18213c22ba52SSukadev Bhattiprolu }, 18223c22ba52SSukadev Bhattiprolu {, 18233c22ba52SSukadev Bhattiprolu "EventCode": "0x360B4", 18243c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF0_BUSY", 18253c22ba52SSukadev Bhattiprolu "BriefDescription": "Lifetime, sample of PF machine 0 valid" 18263c22ba52SSukadev Bhattiprolu }, 18273c22ba52SSukadev Bhattiprolu {, 18283c22ba52SSukadev Bhattiprolu "EventCode": "0xC0B0", 18293c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_UE", 18303c22ba52SSukadev Bhattiprolu "BriefDescription": "Correctable ECC error on reload data, reported at critical data forward time" 18313c22ba52SSukadev Bhattiprolu }, 18323c22ba52SSukadev Bhattiprolu {, 18333c22ba52SSukadev Bhattiprolu "EventCode": "0x4013A", 18343c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_IC_MISS", 18353c22ba52SSukadev Bhattiprolu "BriefDescription": "Marked instruction experienced I cache miss" 18363c22ba52SSukadev Bhattiprolu }, 18373c22ba52SSukadev Bhattiprolu {, 18383c22ba52SSukadev Bhattiprolu "EventCode": "0x2088", 18393c22ba52SSukadev Bhattiprolu "EventName": "PM_FLUSH_DISP_SB", 18403c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch Flush: Scoreboard" 18413c22ba52SSukadev Bhattiprolu }, 18423c22ba52SSukadev Bhattiprolu {, 18433c22ba52SSukadev Bhattiprolu "EventCode": "0x401E8", 18443c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2MISS", 18453c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load" 18463c22ba52SSukadev Bhattiprolu }, 18473c22ba52SSukadev Bhattiprolu {, 18483c22ba52SSukadev Bhattiprolu "EventCode": "0x3688E", 18493c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_ST_CAUSED_FAIL", 18503c22ba52SSukadev Bhattiprolu "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail" 18513c22ba52SSukadev Bhattiprolu }, 18523c22ba52SSukadev Bhattiprolu {, 18533c22ba52SSukadev Bhattiprolu "EventCode": "0x460B2", 18543c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_SYS_GUESS_WRONG", 18559749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected VGS or RNS, but was wrong" 18563c22ba52SSukadev Bhattiprolu }, 18573c22ba52SSukadev Bhattiprolu {, 18583c22ba52SSukadev Bhattiprolu "EventCode": "0x58B8", 18593c22ba52SSukadev Bhattiprolu "EventName": "PM_TAGE_OVERRIDE_WRONG_SPEC", 18603c22ba52SSukadev Bhattiprolu "BriefDescription": "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time" 18613c22ba52SSukadev Bhattiprolu }, 18623c22ba52SSukadev Bhattiprolu {, 18633c22ba52SSukadev Bhattiprolu "EventCode": "0xE890", 18643c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_ERAT_HIT", 18653c22ba52SSukadev Bhattiprolu "BriefDescription": "Primary ERAT hit. There is no secondary ERAT" 18663c22ba52SSukadev Bhattiprolu }, 18673c22ba52SSukadev Bhattiprolu {, 18683c22ba52SSukadev Bhattiprolu "EventCode": "0x2898", 18693c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_TABORT_TRECLAIM", 18703c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion time tabortnoncd, tabortcd, treclaim" 18713c22ba52SSukadev Bhattiprolu }, 18723c22ba52SSukadev Bhattiprolu {, 18733c22ba52SSukadev Bhattiprolu "EventCode": "0x268A0", 18743c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CO_L31", 18753c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come in the same cyc)" 18763c22ba52SSukadev Bhattiprolu }, 18773c22ba52SSukadev Bhattiprolu {, 18783c22ba52SSukadev Bhattiprolu "EventCode": "0x5080", 18793c22ba52SSukadev Bhattiprolu "EventName": "PM_THRD_PRIO_4_5_CYC", 18803c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles thread running at priority level 4 or 5" 18813c22ba52SSukadev Bhattiprolu }, 18823c22ba52SSukadev Bhattiprolu {, 18833c22ba52SSukadev Bhattiprolu "EventCode": "0x2505C", 18843c22ba52SSukadev Bhattiprolu "EventName": "PM_VSU_FIN", 18853c22ba52SSukadev Bhattiprolu "BriefDescription": "VSU instruction finished. Up to 4 per cycle" 18863c22ba52SSukadev Bhattiprolu }, 18873c22ba52SSukadev Bhattiprolu {, 18883c22ba52SSukadev Bhattiprolu "EventCode": "0x40A4", 18893c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_PRED_CCACHE", 18903c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed that used the Count Cache for Target Prediction" 18913c22ba52SSukadev Bhattiprolu }, 18923c22ba52SSukadev Bhattiprolu {, 18933c22ba52SSukadev Bhattiprolu "EventCode": "0x2E04A", 18943c22ba52SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_RL4", 18953c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 18963c22ba52SSukadev Bhattiprolu }, 18973c22ba52SSukadev Bhattiprolu {, 18983c22ba52SSukadev Bhattiprolu "EventCode": "0x4D12E", 18993c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", 19003c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load" 19013c22ba52SSukadev Bhattiprolu }, 19023c22ba52SSukadev Bhattiprolu {, 19033c22ba52SSukadev Bhattiprolu "EventCode": "0xC8B4", 19043c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_LHL_SHL", 19053c22ba52SSukadev Bhattiprolu "BriefDescription": "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores)." 19063c22ba52SSukadev Bhattiprolu }, 19073c22ba52SSukadev Bhattiprolu {, 19083c22ba52SSukadev Bhattiprolu "EventCode": "0x58A4", 19093c22ba52SSukadev Bhattiprolu "EventName": "PM_FLUSH_LSU", 19103c22ba52SSukadev Bhattiprolu "BriefDescription": "LSU flushes. Includes all lsu flushes" 19113c22ba52SSukadev Bhattiprolu }, 19123c22ba52SSukadev Bhattiprolu {, 19133c22ba52SSukadev Bhattiprolu "EventCode": "0x1D150", 19143c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR", 19153c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load" 19163c22ba52SSukadev Bhattiprolu }, 19173c22ba52SSukadev Bhattiprolu {, 19183c22ba52SSukadev Bhattiprolu "EventCode": "0xC8A0", 19193c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU1_FALSE_LHS", 19203c22ba52SSukadev Bhattiprolu "BriefDescription": "False LHS match detected" 19213c22ba52SSukadev Bhattiprolu }, 19223c22ba52SSukadev Bhattiprolu {, 19233c22ba52SSukadev Bhattiprolu "EventCode": "0x48BC", 19243c22ba52SSukadev Bhattiprolu "EventName": "PM_THRD_PRIO_2_3_CYC", 19253c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles thread running at priority level 2 or 3" 19263c22ba52SSukadev Bhattiprolu }, 19273c22ba52SSukadev Bhattiprolu {, 19283c22ba52SSukadev Bhattiprolu "EventCode": "0x368B2", 19293c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_GRP_GUESS_WRONG_HIGH", 19309749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was VGS or RNS" 19313c22ba52SSukadev Bhattiprolu }, 19323c22ba52SSukadev Bhattiprolu {, 19333c22ba52SSukadev Bhattiprolu "EventCode": "0xE8BC", 19343c22ba52SSukadev Bhattiprolu "EventName": "PM_LS1_PTE_TABLEWALK_CYC", 19353c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles when a tablewalk is pending on this thread on table 1" 19363c22ba52SSukadev Bhattiprolu }, 19373c22ba52SSukadev Bhattiprolu {, 19383c22ba52SSukadev Bhattiprolu "EventCode": "0x1F152", 19393c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_FAB_RSP_BKILL_CYC", 19403c22ba52SSukadev Bhattiprolu "BriefDescription": "cycles L2 RC took for a bkill" 19413c22ba52SSukadev Bhattiprolu }, 19423c22ba52SSukadev Bhattiprolu {, 19433c22ba52SSukadev Bhattiprolu "EventCode": "0x4C124", 19443c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC", 19453c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load" 19463c22ba52SSukadev Bhattiprolu }, 19473c22ba52SSukadev Bhattiprolu {, 19483c22ba52SSukadev Bhattiprolu "EventCode": "0x2F14A", 19493c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DPTEG_FROM_RL4", 19503c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 19513c22ba52SSukadev Bhattiprolu }, 19523c22ba52SSukadev Bhattiprolu {, 19533c22ba52SSukadev Bhattiprolu "EventCode": "0x26888", 19543c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_GRP_GUESS_WRONG", 19553c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)" 19563c22ba52SSukadev Bhattiprolu }, 19573c22ba52SSukadev Bhattiprolu {, 19583c22ba52SSukadev Bhattiprolu "EventCode": "0xC0AC", 19593c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_EMSH", 19603c22ba52SSukadev Bhattiprolu "BriefDescription": "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address" 19613c22ba52SSukadev Bhattiprolu }, 19623c22ba52SSukadev Bhattiprolu {, 19633c22ba52SSukadev Bhattiprolu "EventCode": "0x260B2", 19643c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_SYS_GUESS_CORRECT", 19659749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected VGS or RNS and was correct" 19663c22ba52SSukadev Bhattiprolu }, 19673c22ba52SSukadev Bhattiprolu {, 19683c22ba52SSukadev Bhattiprolu "EventCode": "0x1D146", 19693c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_MEMORY_CYC", 19703c22ba52SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load" 19713c22ba52SSukadev Bhattiprolu }, 19723c22ba52SSukadev Bhattiprolu {, 19733c22ba52SSukadev Bhattiprolu "EventCode": "0xE094", 19743c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_TM_L1_HIT", 19753c22ba52SSukadev Bhattiprolu "BriefDescription": "Load tm hit in L1" 19763c22ba52SSukadev Bhattiprolu }, 19773c22ba52SSukadev Bhattiprolu {, 19783c22ba52SSukadev Bhattiprolu "EventCode": "0x46888", 19793c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_GROUP_PUMP", 19803c22ba52SSukadev Bhattiprolu "BriefDescription": "RC requests that were on group (aka nodel) pump attempts" 19813c22ba52SSukadev Bhattiprolu }, 19823c22ba52SSukadev Bhattiprolu {, 19839749adc3SSukadev Bhattiprolu "EventCode": "0xC08C", 19849749adc3SSukadev Bhattiprolu "EventName": "PM_LSU_DTLB_MISS_16M_2M", 19859749adc3SSukadev Bhattiprolu "BriefDescription": "Data TLB Miss page size 16M (HPT) or 2M (Radix)" 19869749adc3SSukadev Bhattiprolu }, 19879749adc3SSukadev Bhattiprolu {, 19883c22ba52SSukadev Bhattiprolu "EventCode": "0x16080", 19893c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_LD", 19903c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)" 19913c22ba52SSukadev Bhattiprolu }, 19923c22ba52SSukadev Bhattiprolu {, 19933c22ba52SSukadev Bhattiprolu "EventCode": "0x4505C", 19943c22ba52SSukadev Bhattiprolu "EventName": "PM_MATH_FLOP_CMPL", 19953c22ba52SSukadev Bhattiprolu "BriefDescription": "Math flop instruction completed" 19963c22ba52SSukadev Bhattiprolu }, 19973c22ba52SSukadev Bhattiprolu {, 1998e795dd42SSukadev Bhattiprolu "EventCode": "0xC080", 1999e795dd42SSukadev Bhattiprolu "EventName": "PM_LS0_LD_VECTOR_FIN", 20009749adc3SSukadev Bhattiprolu "BriefDescription": "LS0 finished load vector op" 2001e795dd42SSukadev Bhattiprolu }, 2002e795dd42SSukadev Bhattiprolu {, 20033c22ba52SSukadev Bhattiprolu "EventCode": "0x368B0", 20043c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_SYS_PUMP", 20053c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF sent with sys scope port 1, counts even retried requests" 20063c22ba52SSukadev Bhattiprolu }, 20073c22ba52SSukadev Bhattiprolu {, 20083c22ba52SSukadev Bhattiprolu "EventCode": "0x1F146", 20093c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DPTEG_FROM_L31_SHR", 20103c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 20113c22ba52SSukadev Bhattiprolu }, 20123c22ba52SSukadev Bhattiprolu {, 20133c22ba52SSukadev Bhattiprolu "EventCode": "0x2000C", 20143c22ba52SSukadev Bhattiprolu "EventName": "PM_THRD_ALL_RUN_CYC", 20153c22ba52SSukadev Bhattiprolu "BriefDescription": "Cycles in which all the threads have the run latch set" 20163c22ba52SSukadev Bhattiprolu }, 20173c22ba52SSukadev Bhattiprolu {, 20183c22ba52SSukadev Bhattiprolu "EventCode": "0xC0BC", 20193c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_OTHER", 20203c22ba52SSukadev Bhattiprolu "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops)" 20213c22ba52SSukadev Bhattiprolu }, 20223c22ba52SSukadev Bhattiprolu {, 20233c22ba52SSukadev Bhattiprolu "EventCode": "0x5094", 20243c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_MISS_ICBI", 20253c22ba52SSukadev Bhattiprolu "BriefDescription": "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out" 20263c22ba52SSukadev Bhattiprolu }, 20273c22ba52SSukadev Bhattiprolu {, 20283c22ba52SSukadev Bhattiprolu "EventCode": "0xC8A8", 20293c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_ATOMIC", 20303c22ba52SSukadev Bhattiprolu "BriefDescription": "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed" 20313c22ba52SSukadev Bhattiprolu }, 20323c22ba52SSukadev Bhattiprolu {, 20333c22ba52SSukadev Bhattiprolu "EventCode": "0x1E04E", 20343c22ba52SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_L2MISS", 20353c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 20363c22ba52SSukadev Bhattiprolu }, 20373c22ba52SSukadev Bhattiprolu {, 20383c22ba52SSukadev Bhattiprolu "EventCode": "0x4D05E", 20393c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_CMPL", 20403c22ba52SSukadev Bhattiprolu "BriefDescription": "Any Branch instruction completed" 20413c22ba52SSukadev Bhattiprolu }, 20423c22ba52SSukadev Bhattiprolu {, 20433c22ba52SSukadev Bhattiprolu "EventCode": "0x260B0", 20443c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_GRP_PUMP", 20453c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF sent with grp scope port 0, counts even retried requests" 20463c22ba52SSukadev Bhattiprolu }, 20473c22ba52SSukadev Bhattiprolu {, 20483c22ba52SSukadev Bhattiprolu "EventCode": "0x30132", 20493c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_VSU_FIN", 20503c22ba52SSukadev Bhattiprolu "BriefDescription": "VSU marked instr finish" 20513c22ba52SSukadev Bhattiprolu }, 20523c22ba52SSukadev Bhattiprolu {, 20533c22ba52SSukadev Bhattiprolu "EventCode": "0x2D120", 20543c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", 20553c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load" 20563c22ba52SSukadev Bhattiprolu }, 20573c22ba52SSukadev Bhattiprolu {, 20583c22ba52SSukadev Bhattiprolu "EventCode": "0x1E048", 20593c22ba52SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE", 20603c22ba52SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 20613c22ba52SSukadev Bhattiprolu }, 20623c22ba52SSukadev Bhattiprolu {, 20633c22ba52SSukadev Bhattiprolu "EventCode": "0x16086", 20643c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_SN_M_WR_DONE", 20653c22ba52SSukadev Bhattiprolu "BriefDescription": "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)" 20663c22ba52SSukadev Bhattiprolu }, 20673c22ba52SSukadev Bhattiprolu {, 20683c22ba52SSukadev Bhattiprolu "EventCode": "0x489C", 20693c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_CORECT_PRED_TAKEN_CMPL", 20703c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time" 20713c22ba52SSukadev Bhattiprolu }, 20723c22ba52SSukadev Bhattiprolu {, 20739749adc3SSukadev Bhattiprolu "EventCode": "0xF0B8", 20749749adc3SSukadev Bhattiprolu "EventName": "PM_LS0_UNALIGNED_ST", 20759749adc3SSukadev Bhattiprolu "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" 20769749adc3SSukadev Bhattiprolu }, 20779749adc3SSukadev Bhattiprolu {, 20783c22ba52SSukadev Bhattiprolu "EventCode": "0x20132", 20793c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DFU_FIN", 20803c22ba52SSukadev Bhattiprolu "BriefDescription": "Decimal Unit marked Instruction Finish" 20813c22ba52SSukadev Bhattiprolu }, 20823c22ba52SSukadev Bhattiprolu {, 20833c22ba52SSukadev Bhattiprolu "EventCode": "0x160A6", 20843c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_SC_CO", 20859749adc3SSukadev Bhattiprolu "BriefDescription": "L3 castout of line that was StoreCopy (original value of speculatively written line) in a Transaction" 20863c22ba52SSukadev Bhattiprolu }, 20873c22ba52SSukadev Bhattiprolu {, 20883c22ba52SSukadev Bhattiprolu "EventCode": "0xC8B0", 20893c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_LHS", 20903c22ba52SSukadev Bhattiprolu "BriefDescription": "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed" 20913c22ba52SSukadev Bhattiprolu }, 20923c22ba52SSukadev Bhattiprolu {, 2093e795dd42SSukadev Bhattiprolu "EventCode": "0x16084", 2094e795dd42SSukadev Bhattiprolu "EventName": "PM_L2_RCLD_DISP", 20959749adc3SSukadev Bhattiprolu "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread" 2096e795dd42SSukadev Bhattiprolu }, 2097e795dd42SSukadev Bhattiprolu {, 20983c22ba52SSukadev Bhattiprolu "EventCode": "0x3F150", 20993c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", 21003c22ba52SSukadev Bhattiprolu "BriefDescription": "cycles to drain st from core to L2" 21013c22ba52SSukadev Bhattiprolu }, 21023c22ba52SSukadev Bhattiprolu {, 21033c22ba52SSukadev Bhattiprolu "EventCode": "0x168A4", 21043c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_MISS", 21053c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Misses (L2 miss also missing L3, including data/instrn/xlate)" 21063c22ba52SSukadev Bhattiprolu }, 21073c22ba52SSukadev Bhattiprolu {, 21083c22ba52SSukadev Bhattiprolu "EventCode": "0xF080", 21093c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_STCX_FAIL", 2110123a039dSMichael Petlan "BriefDescription": "The LSU detects the condition that a stcx instruction failed. No requirement to wait for a response from the nest" 21113c22ba52SSukadev Bhattiprolu }, 21123c22ba52SSukadev Bhattiprolu {, 21133c22ba52SSukadev Bhattiprolu "EventCode": "0x30038", 21143c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_DMISS_LMEM", 21153c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion stall due to cache miss that resolves in local memory" 21163c22ba52SSukadev Bhattiprolu }, 21173c22ba52SSukadev Bhattiprolu {, 21183c22ba52SSukadev Bhattiprolu "EventCode": "0x28A4", 21193c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_TEND_FAIL", 21203c22ba52SSukadev Bhattiprolu "BriefDescription": "Nested or not nested tend failed for a marked tend instruction" 21213c22ba52SSukadev Bhattiprolu }, 21223c22ba52SSukadev Bhattiprolu {, 21233c22ba52SSukadev Bhattiprolu "EventCode": "0x100FC", 21243c22ba52SSukadev Bhattiprolu "EventName": "PM_LD_REF_L1", 21253c22ba52SSukadev Bhattiprolu "BriefDescription": "All L1 D cache load references counted at finish, gated by reject" 21263c22ba52SSukadev Bhattiprolu }, 21273c22ba52SSukadev Bhattiprolu {, 21283c22ba52SSukadev Bhattiprolu "EventCode": "0xC0A0", 21293c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_FALSE_LHS", 21303c22ba52SSukadev Bhattiprolu "BriefDescription": "False LHS match detected" 21313c22ba52SSukadev Bhattiprolu }, 21323c22ba52SSukadev Bhattiprolu {, 21333c22ba52SSukadev Bhattiprolu "EventCode": "0x468A8", 21343c22ba52SSukadev Bhattiprolu "EventName": "PM_SN_MISS", 21353c22ba52SSukadev Bhattiprolu "BriefDescription": "Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we only count 1" 21363c22ba52SSukadev Bhattiprolu }, 21373c22ba52SSukadev Bhattiprolu {, 21383c22ba52SSukadev Bhattiprolu "EventCode": "0x36888", 21393c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_SYS_GUESS_WRONG", 21403c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group)" 21413c22ba52SSukadev Bhattiprolu }, 21423c22ba52SSukadev Bhattiprolu {, 21433c22ba52SSukadev Bhattiprolu "EventCode": "0x2080", 21443c22ba52SSukadev Bhattiprolu "EventName": "PM_EE_OFF_EXT_INT", 21453c22ba52SSukadev Bhattiprolu "BriefDescription": "CyclesMSR[EE] is off and external interrupts are active" 21463c22ba52SSukadev Bhattiprolu }, 21473c22ba52SSukadev Bhattiprolu {, 21483c22ba52SSukadev Bhattiprolu "EventCode": "0xE8B8", 21493c22ba52SSukadev Bhattiprolu "EventName": "PM_LS3_TM_DISALLOW", 21503c22ba52SSukadev Bhattiprolu "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it" 21513c22ba52SSukadev Bhattiprolu }, 21523c22ba52SSukadev Bhattiprolu {, 21533c22ba52SSukadev Bhattiprolu "EventCode": "0x2688E", 21543c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_FAV_CAUSED_FAIL", 21553c22ba52SSukadev Bhattiprolu "BriefDescription": "TM Load (fav) caused another thread to fail" 21563c22ba52SSukadev Bhattiprolu }, 21573c22ba52SSukadev Bhattiprolu {, 21583c22ba52SSukadev Bhattiprolu "EventCode": "0x16090", 21593c22ba52SSukadev Bhattiprolu "EventName": "PM_SN0_BUSY", 21603c22ba52SSukadev Bhattiprolu "BriefDescription": "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)" 21613c22ba52SSukadev Bhattiprolu }, 21623c22ba52SSukadev Bhattiprolu {, 21633c22ba52SSukadev Bhattiprolu "EventCode": "0x360AE", 21643c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_CO_RTY", 21653c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO received retry port 0 (memory only), every retry counted" 21663c22ba52SSukadev Bhattiprolu }, 21673c22ba52SSukadev Bhattiprolu {, 21683c22ba52SSukadev Bhattiprolu "EventCode": "0x168A8", 21693c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_WI_USAGE", 21703c22ba52SSukadev Bhattiprolu "BriefDescription": "Lifetime, sample of Write Inject machine 0 valid" 21713c22ba52SSukadev Bhattiprolu }, 21723c22ba52SSukadev Bhattiprolu {, 21733c22ba52SSukadev Bhattiprolu "EventCode": "0x468A2", 21743c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_LAT_CI_MISS", 21753c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 Lateral Castins Miss" 21763c22ba52SSukadev Bhattiprolu }, 21773c22ba52SSukadev Bhattiprolu {, 21783c22ba52SSukadev Bhattiprolu "EventCode": "0x4090", 21793c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_PREF_CANCEL_PAGE", 21803c22ba52SSukadev Bhattiprolu "BriefDescription": "Prefetch Canceled due to page boundary" 21813c22ba52SSukadev Bhattiprolu }, 21823c22ba52SSukadev Bhattiprolu {, 21833c22ba52SSukadev Bhattiprolu "EventCode": "0x460AA", 21843c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_CO_L31", 21853c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 CO to L3.1 (LCO) port 0 with or without data" 21863c22ba52SSukadev Bhattiprolu }, 21873c22ba52SSukadev Bhattiprolu {, 21883c22ba52SSukadev Bhattiprolu "EventCode": "0x2880", 21893c22ba52SSukadev Bhattiprolu "EventName": "PM_FLUSH_DISP", 21903c22ba52SSukadev Bhattiprolu "BriefDescription": "Dispatch flush" 21913c22ba52SSukadev Bhattiprolu }, 21923c22ba52SSukadev Bhattiprolu {, 21933c22ba52SSukadev Bhattiprolu "EventCode": "0x168AE", 21943c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P1_PF_RTY", 21953c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 PF received retry port 1, every retry counted" 21963c22ba52SSukadev Bhattiprolu }, 21973c22ba52SSukadev Bhattiprolu {, 21983c22ba52SSukadev Bhattiprolu "EventCode": "0x46082", 21993c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_ST_DISP", 22009749adc3SSukadev Bhattiprolu "BriefDescription": "All successful D-side store dispatches for this thread" 22013c22ba52SSukadev Bhattiprolu }, 22023c22ba52SSukadev Bhattiprolu {, 2203e795dd42SSukadev Bhattiprolu "EventCode": "0x36880", 22043c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_INST_MISS", 22059749adc3SSukadev Bhattiprolu "BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread that were an L2 miss" 22063c22ba52SSukadev Bhattiprolu }, 22073c22ba52SSukadev Bhattiprolu {, 22083c22ba52SSukadev Bhattiprolu "EventCode": "0xE084", 22093c22ba52SSukadev Bhattiprolu "EventName": "PM_LS0_ERAT_MISS_PREF", 22103c22ba52SSukadev Bhattiprolu "BriefDescription": "LS0 Erat miss due to prefetch" 22113c22ba52SSukadev Bhattiprolu }, 22123c22ba52SSukadev Bhattiprolu {, 22133c22ba52SSukadev Bhattiprolu "EventCode": "0x409C", 22143c22ba52SSukadev Bhattiprolu "EventName": "PM_BR_PRED", 22153c22ba52SSukadev Bhattiprolu "BriefDescription": "Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time" 22163c22ba52SSukadev Bhattiprolu }, 22173c22ba52SSukadev Bhattiprolu {, 22183c22ba52SSukadev Bhattiprolu "EventCode": "0x2D144", 22193c22ba52SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L31_MOD", 22203c22ba52SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load" 22213c22ba52SSukadev Bhattiprolu }, 22223c22ba52SSukadev Bhattiprolu {, 22233c22ba52SSukadev Bhattiprolu "EventCode": "0x360A4", 22243c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CO_LCO", 22253c22ba52SSukadev Bhattiprolu "BriefDescription": "Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry)" 22263c22ba52SSukadev Bhattiprolu }, 22273c22ba52SSukadev Bhattiprolu {, 22283c22ba52SSukadev Bhattiprolu "EventCode": "0x4890", 22293c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_PREF_CANCEL_HIT", 22303c22ba52SSukadev Bhattiprolu "BriefDescription": "Prefetch Canceled due to icache hit" 22313c22ba52SSukadev Bhattiprolu }, 22323c22ba52SSukadev Bhattiprolu {, 22333c22ba52SSukadev Bhattiprolu "EventCode": "0x268A8", 22343c22ba52SSukadev Bhattiprolu "EventName": "PM_RD_HIT_PF", 22353c22ba52SSukadev Bhattiprolu "BriefDescription": "RD machine hit L3 PF machine" 22363c22ba52SSukadev Bhattiprolu }, 22373c22ba52SSukadev Bhattiprolu {, 22383c22ba52SSukadev Bhattiprolu "EventCode": "0x16880", 22393c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_ST", 22403c22ba52SSukadev Bhattiprolu "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)" 22413c22ba52SSukadev Bhattiprolu }, 22423c22ba52SSukadev Bhattiprolu {, 22433c22ba52SSukadev Bhattiprolu "EventCode": "0x4098", 22443c22ba52SSukadev Bhattiprolu "EventName": "PM_IC_DEMAND_L2_BHT_REDIRECT", 22453c22ba52SSukadev Bhattiprolu "BriefDescription": "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)" 22463c22ba52SSukadev Bhattiprolu }, 22473c22ba52SSukadev Bhattiprolu {, 22483c22ba52SSukadev Bhattiprolu "EventCode": "0xD0B4", 22493c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU0_SRQ_S0_VALID_CYC", 22503c22ba52SSukadev Bhattiprolu "BriefDescription": "Slot 0 of SRQ valid" 22513c22ba52SSukadev Bhattiprolu }, 22523c22ba52SSukadev Bhattiprolu {, 22533c22ba52SSukadev Bhattiprolu "EventCode": "0x160AA", 22543c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_P0_LCO_NO_DATA", 22553c22ba52SSukadev Bhattiprolu "BriefDescription": "Dataless L3 LCO sent port 0" 22563c22ba52SSukadev Bhattiprolu }, 22573c22ba52SSukadev Bhattiprolu {, 22583c22ba52SSukadev Bhattiprolu "EventCode": "0x208C", 22593c22ba52SSukadev Bhattiprolu "EventName": "PM_CLB_HELD", 22603c22ba52SSukadev Bhattiprolu "BriefDescription": "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason" 22613c22ba52SSukadev Bhattiprolu }, 22623c22ba52SSukadev Bhattiprolu {, 22633c22ba52SSukadev Bhattiprolu "EventCode": "0xF88C", 22643c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU3_STORE_REJECT", 22653c22ba52SSukadev Bhattiprolu "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" 22663c22ba52SSukadev Bhattiprolu }, 22673c22ba52SSukadev Bhattiprolu {, 22683c22ba52SSukadev Bhattiprolu "EventCode": "0x200F2", 22693c22ba52SSukadev Bhattiprolu "EventName": "PM_INST_DISP", 22703c22ba52SSukadev Bhattiprolu "BriefDescription": "# PPC Dispatched" 22713c22ba52SSukadev Bhattiprolu }, 22723c22ba52SSukadev Bhattiprolu {, 22733c22ba52SSukadev Bhattiprolu "EventCode": "0x4E05E", 22743c22ba52SSukadev Bhattiprolu "EventName": "PM_TM_OUTER_TBEGIN_DISP", 22753c22ba52SSukadev Bhattiprolu "BriefDescription": "Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions" 22763c22ba52SSukadev Bhattiprolu }, 22773c22ba52SSukadev Bhattiprolu {, 22783c22ba52SSukadev Bhattiprolu "EventCode": "0x2D018", 22793c22ba52SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_EXEC_UNIT", 22803c22ba52SSukadev Bhattiprolu "BriefDescription": "Completion stall due to execution units (FXU/VSU/CRU)" 22813c22ba52SSukadev Bhattiprolu }, 22823c22ba52SSukadev Bhattiprolu {, 22833c22ba52SSukadev Bhattiprolu "EventCode": "0x20B0", 22843c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_FLUSH_NEXT", 22853c22ba52SSukadev Bhattiprolu "BriefDescription": "LSU flush next reported at flush time. Sometimes these also come with an exception" 22863c22ba52SSukadev Bhattiprolu }, 22873c22ba52SSukadev Bhattiprolu {, 22883c22ba52SSukadev Bhattiprolu "EventCode": "0x3880", 22893c22ba52SSukadev Bhattiprolu "EventName": "PM_ISU2_ISS_HOLD_ALL", 22903c22ba52SSukadev Bhattiprolu "BriefDescription": "All ISU rejects" 22913c22ba52SSukadev Bhattiprolu }, 22923c22ba52SSukadev Bhattiprolu {, 2293e795dd42SSukadev Bhattiprolu "EventCode": "0xC884", 2294e795dd42SSukadev Bhattiprolu "EventName": "PM_LS3_LD_VECTOR_FIN", 22959749adc3SSukadev Bhattiprolu "BriefDescription": "LS3 finished load vector op" 22963c22ba52SSukadev Bhattiprolu }, 22973c22ba52SSukadev Bhattiprolu {, 22983c22ba52SSukadev Bhattiprolu "EventCode": "0x360A8", 22993c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CO", 23003c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 castout occurring (does not include casthrough or log writes (cinj/dmaw))" 23013c22ba52SSukadev Bhattiprolu }, 23023c22ba52SSukadev Bhattiprolu {, 23033c22ba52SSukadev Bhattiprolu "EventCode": "0x368A4", 23043c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_CINJ", 23053c22ba52SSukadev Bhattiprolu "BriefDescription": "L3 castin of cache inject" 23063c22ba52SSukadev Bhattiprolu }, 23073c22ba52SSukadev Bhattiprolu {, 23083c22ba52SSukadev Bhattiprolu "EventCode": "0xC890", 23093c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_NCST", 23103c22ba52SSukadev Bhattiprolu "BriefDescription": "Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1" 23113c22ba52SSukadev Bhattiprolu }, 23123c22ba52SSukadev Bhattiprolu {, 23133c22ba52SSukadev Bhattiprolu "EventCode": "0xD0B8", 23143c22ba52SSukadev Bhattiprolu "EventName": "PM_LSU_LMQ_FULL_CYC", 23153c22ba52SSukadev Bhattiprolu "BriefDescription": "Counts the number of cycles the LMQ is full" 23163c22ba52SSukadev Bhattiprolu }, 23173c22ba52SSukadev Bhattiprolu {, 23183c22ba52SSukadev Bhattiprolu "EventCode": "0x168B2", 23193c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_GRP_GUESS_CORRECT", 23209749adc3SSukadev Bhattiprolu "BriefDescription": "Prefetch scope predictor selected GS or NNS and was correct" 23213c22ba52SSukadev Bhattiprolu }, 23223c22ba52SSukadev Bhattiprolu {, 23233c22ba52SSukadev Bhattiprolu "EventCode": "0x48A4", 23243c22ba52SSukadev Bhattiprolu "EventName": "PM_STOP_FETCH_PENDING_CYC", 23253c22ba52SSukadev Bhattiprolu "BriefDescription": "Fetching is stopped due to an incoming instruction that will result in a flush" 23263c22ba52SSukadev Bhattiprolu }, 23273c22ba52SSukadev Bhattiprolu {, 23283c22ba52SSukadev Bhattiprolu "EventCode": "0x36884", 23293c22ba52SSukadev Bhattiprolu "EventName": "PM_L2_RCST_DISP_FAIL_ADDR", 23303c22ba52SSukadev Bhattiprolu "BriefDescription": "All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ" 23313c22ba52SSukadev Bhattiprolu }, 23323c22ba52SSukadev Bhattiprolu {, 23333c22ba52SSukadev Bhattiprolu "EventCode": "0x260AC", 23343c22ba52SSukadev Bhattiprolu "EventName": "PM_L3_PF_USAGE", 23353c22ba52SSukadev Bhattiprolu "BriefDescription": "Rotating sample of 32 PF actives" 2336826db0f1SSukadev Bhattiprolu } 2337826db0f1SSukadev Bhattiprolu]