1[ 2 { 3 "BriefDescription": "Completion stall due to a Branch Unit", 4 "MetricExpr": "PM_CMPLU_STALL_BRU/PM_RUN_INST_CMPL", 5 "MetricGroup": "cpi_breakdown", 6 "MetricName": "bru_stall_cpi" 7 }, 8 { 9 "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish", 10 "MetricExpr": "PM_CMPLU_STALL_CRYPTO/PM_RUN_INST_CMPL", 11 "MetricGroup": "cpi_breakdown", 12 "MetricName": "crypto_stall_cpi" 13 }, 14 { 15 "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest", 16 "MetricExpr": "PM_CMPLU_STALL_DCACHE_MISS/PM_RUN_INST_CMPL", 17 "MetricGroup": "cpi_breakdown", 18 "MetricName": "dcache_miss_stall_cpi" 19 }, 20 { 21 "BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish.", 22 "MetricExpr": "PM_CMPLU_STALL_DFLONG/PM_RUN_INST_CMPL", 23 "MetricGroup": "cpi_breakdown", 24 "MetricName": "dflong_stall_cpi" 25 }, 26 { 27 "BriefDescription": "Stalls due to short latency decimal floating ops.", 28 "MetricExpr": "(PM_CMPLU_STALL_DFU - PM_CMPLU_STALL_DFLONG)/PM_RUN_INST_CMPL", 29 "MetricGroup": "cpi_breakdown", 30 "MetricName": "dfu_other_stall_cpi" 31 }, 32 { 33 "BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish.", 34 "MetricExpr": "PM_CMPLU_STALL_DFU/PM_RUN_INST_CMPL", 35 "MetricGroup": "cpi_breakdown", 36 "MetricName": "dfu_stall_cpi" 37 }, 38 { 39 "BriefDescription": "Completion stall by Dcache miss which resolved off node memory/cache", 40 "MetricExpr": "(PM_CMPLU_STALL_DMISS_L3MISS - PM_CMPLU_STALL_DMISS_L21_L31 - PM_CMPLU_STALL_DMISS_LMEM - PM_CMPLU_STALL_DMISS_REMOTE)/PM_RUN_INST_CMPL", 41 "MetricGroup": "cpi_breakdown", 42 "MetricName": "dmiss_distant_stall_cpi" 43 }, 44 { 45 "BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", 46 "MetricExpr": "PM_CMPLU_STALL_DMISS_L21_L31/PM_RUN_INST_CMPL", 47 "MetricGroup": "cpi_breakdown", 48 "MetricName": "dmiss_l21_l31_stall_cpi" 49 }, 50 { 51 "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", 52 "MetricExpr": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT/PM_RUN_INST_CMPL", 53 "MetricGroup": "cpi_breakdown", 54 "MetricName": "dmiss_l2l3_conflict_stall_cpi" 55 }, 56 { 57 "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conflict", 58 "MetricExpr": "(PM_CMPLU_STALL_DMISS_L2L3 - PM_CMPLU_STALL_DMISS_L2L3_CONFLICT)/PM_RUN_INST_CMPL", 59 "MetricGroup": "cpi_breakdown", 60 "MetricName": "dmiss_l2l3_noconflict_stall_cpi" 61 }, 62 { 63 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", 64 "MetricExpr": "PM_CMPLU_STALL_DMISS_L2L3/PM_RUN_INST_CMPL", 65 "MetricGroup": "cpi_breakdown", 66 "MetricName": "dmiss_l2l3_stall_cpi" 67 }, 68 { 69 "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 70 "MetricExpr": "PM_CMPLU_STALL_DMISS_L3MISS/PM_RUN_INST_CMPL", 71 "MetricGroup": "cpi_breakdown", 72 "MetricName": "dmiss_l3miss_stall_cpi" 73 }, 74 { 75 "BriefDescription": "Completion stall due to cache miss that resolves in local memory", 76 "MetricExpr": "PM_CMPLU_STALL_DMISS_LMEM/PM_RUN_INST_CMPL", 77 "MetricGroup": "cpi_breakdown", 78 "MetricName": "dmiss_lmem_stall_cpi" 79 }, 80 { 81 "BriefDescription": "Completion stall by Dcache miss which resolved outside of local memory", 82 "MetricExpr": "(PM_CMPLU_STALL_DMISS_L3MISS - PM_CMPLU_STALL_DMISS_L21_L31 - PM_CMPLU_STALL_DMISS_LMEM)/PM_RUN_INST_CMPL", 83 "MetricGroup": "cpi_breakdown", 84 "MetricName": "dmiss_non_local_stall_cpi" 85 }, 86 { 87 "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)", 88 "MetricExpr": "PM_CMPLU_STALL_DMISS_REMOTE/PM_RUN_INST_CMPL", 89 "MetricGroup": "cpi_breakdown", 90 "MetricName": "dmiss_remote_stall_cpi" 91 }, 92 { 93 "BriefDescription": "Stalls due to short latency double precision ops.", 94 "MetricExpr": "(PM_CMPLU_STALL_DP - PM_CMPLU_STALL_DPLONG)/PM_RUN_INST_CMPL", 95 "MetricGroup": "cpi_breakdown", 96 "MetricName": "dp_other_stall_cpi" 97 }, 98 { 99 "BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format.", 100 "MetricExpr": "PM_CMPLU_STALL_DP/PM_RUN_INST_CMPL", 101 "MetricGroup": "cpi_breakdown", 102 "MetricName": "dp_stall_cpi" 103 }, 104 { 105 "BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format.", 106 "MetricExpr": "PM_CMPLU_STALL_DPLONG/PM_RUN_INST_CMPL", 107 "MetricGroup": "cpi_breakdown", 108 "MetricName": "dplong_stall_cpi" 109 }, 110 { 111 "BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2", 112 "MetricExpr": "PM_CMPLU_STALL_EIEIO/PM_RUN_INST_CMPL", 113 "MetricGroup": "cpi_breakdown", 114 "MetricName": "eieio_stall_cpi" 115 }, 116 { 117 "BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full", 118 "MetricExpr": "PM_CMPLU_STALL_EMQ_FULL/PM_RUN_INST_CMPL", 119 "MetricGroup": "cpi_breakdown", 120 "MetricName": "emq_full_stall_cpi" 121 }, 122 { 123 "MetricExpr": "(PM_CMPLU_STALL_ERAT_MISS + PM_CMPLU_STALL_EMQ_FULL)/PM_RUN_INST_CMPL", 124 "MetricGroup": "cpi_breakdown", 125 "MetricName": "emq_stall_cpi" 126 }, 127 { 128 "BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a translation miss", 129 "MetricExpr": "PM_CMPLU_STALL_ERAT_MISS/PM_RUN_INST_CMPL", 130 "MetricGroup": "cpi_breakdown", 131 "MetricName": "erat_miss_stall_cpi" 132 }, 133 { 134 "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete", 135 "MetricExpr": "PM_CMPLU_STALL_EXCEPTION/PM_RUN_INST_CMPL", 136 "MetricGroup": "cpi_breakdown", 137 "MetricName": "exception_stall_cpi" 138 }, 139 { 140 "BriefDescription": "Completion stall due to execution units for other reasons.", 141 "MetricExpr": "(PM_CMPLU_STALL_EXEC_UNIT - PM_CMPLU_STALL_FXU - PM_CMPLU_STALL_DP - PM_CMPLU_STALL_DFU - PM_CMPLU_STALL_PM - PM_CMPLU_STALL_CRYPTO - PM_CMPLU_STALL_VFXU - PM_CMPLU_STALL_VDP)/PM_RUN_INST_CMPL", 142 "MetricGroup": "cpi_breakdown", 143 "MetricName": "exec_unit_other_stall_cpi" 144 }, 145 { 146 "BriefDescription": "Completion stall due to execution units (FXU/VSU/CRU)", 147 "MetricExpr": "PM_CMPLU_STALL_EXEC_UNIT/PM_RUN_INST_CMPL", 148 "MetricGroup": "cpi_breakdown", 149 "MetricName": "exec_unit_stall_cpi" 150 }, 151 { 152 "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion", 153 "MetricExpr": "PM_CMPLU_STALL_FLUSH_ANY_THREAD/PM_RUN_INST_CMPL", 154 "MetricGroup": "cpi_breakdown", 155 "MetricName": "flush_any_thread_stall_cpi" 156 }, 157 { 158 "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)", 159 "MetricExpr": "PM_CMPLU_STALL_FXLONG/PM_RUN_INST_CMPL", 160 "MetricGroup": "cpi_breakdown", 161 "MetricName": "fxlong_stall_cpi" 162 }, 163 { 164 "BriefDescription": "Stalls due to short latency integer ops", 165 "MetricExpr": "(PM_CMPLU_STALL_FXU - PM_CMPLU_STALL_FXLONG)/PM_RUN_INST_CMPL", 166 "MetricGroup": "cpi_breakdown", 167 "MetricName": "fxu_other_stall_cpi" 168 }, 169 { 170 "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", 171 "MetricExpr": "PM_CMPLU_STALL_FXU/PM_RUN_INST_CMPL", 172 "MetricGroup": "cpi_breakdown", 173 "MetricName": "fxu_stall_cpi" 174 }, 175 { 176 "MetricExpr": "(PM_NTC_ISSUE_HELD_DARQ_FULL + PM_NTC_ISSUE_HELD_ARB + PM_NTC_ISSUE_HELD_OTHER)/PM_RUN_INST_CMPL", 177 "MetricGroup": "cpi_breakdown", 178 "MetricName": "issue_hold_cpi" 179 }, 180 { 181 "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied", 182 "MetricExpr": "PM_CMPLU_STALL_LARX/PM_RUN_INST_CMPL", 183 "MetricGroup": "cpi_breakdown", 184 "MetricName": "larx_stall_cpi" 185 }, 186 { 187 "BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data", 188 "MetricExpr": "PM_CMPLU_STALL_LHS/PM_RUN_INST_CMPL", 189 "MetricGroup": "cpi_breakdown", 190 "MetricName": "lhs_stall_cpi" 191 }, 192 { 193 "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full", 194 "MetricExpr": "PM_CMPLU_STALL_LMQ_FULL/PM_RUN_INST_CMPL", 195 "MetricGroup": "cpi_breakdown", 196 "MetricName": "lmq_full_stall_cpi" 197 }, 198 { 199 "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish", 200 "MetricExpr": "PM_CMPLU_STALL_LOAD_FINISH/PM_RUN_INST_CMPL", 201 "MetricGroup": "cpi_breakdown", 202 "MetricName": "load_finish_stall_cpi" 203 }, 204 { 205 "BriefDescription": "Finish stall because the NTF instruction was a load that was held in LSAQ because the LRQ was full", 206 "MetricExpr": "PM_CMPLU_STALL_LRQ_FULL/PM_RUN_INST_CMPL", 207 "MetricGroup": "cpi_breakdown", 208 "MetricName": "lrq_full_stall_cpi" 209 }, 210 { 211 "BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others", 212 "MetricExpr": "PM_CMPLU_STALL_LRQ_OTHER/PM_RUN_INST_CMPL", 213 "MetricGroup": "cpi_breakdown", 214 "MetricName": "lrq_other_stall_cpi" 215 }, 216 { 217 "MetricExpr": "(PM_CMPLU_STALL_LMQ_FULL + PM_CMPLU_STALL_ST_FWD + PM_CMPLU_STALL_LHS + PM_CMPLU_STALL_LSU_MFSPR + PM_CMPLU_STALL_LARX + PM_CMPLU_STALL_LRQ_OTHER)/PM_RUN_INST_CMPL", 218 "MetricGroup": "cpi_breakdown", 219 "MetricName": "lrq_stall_cpi" 220 }, 221 { 222 "BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch", 223 "MetricExpr": "PM_CMPLU_STALL_LSAQ_ARB/PM_RUN_INST_CMPL", 224 "MetricGroup": "cpi_breakdown", 225 "MetricName": "lsaq_arb_stall_cpi" 226 }, 227 { 228 "MetricExpr": "(PM_CMPLU_STALL_LRQ_FULL + PM_CMPLU_STALL_SRQ_FULL + PM_CMPLU_STALL_LSAQ_ARB)/PM_RUN_INST_CMPL", 229 "MetricGroup": "cpi_breakdown", 230 "MetricName": "lsaq_stall_cpi" 231 }, 232 { 233 "BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish", 234 "MetricExpr": "PM_CMPLU_STALL_LSU_FIN/PM_RUN_INST_CMPL", 235 "MetricGroup": "cpi_breakdown", 236 "MetricName": "lsu_fin_stall_cpi" 237 }, 238 { 239 "BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete", 240 "MetricExpr": "PM_CMPLU_STALL_LSU_FLUSH_NEXT/PM_RUN_INST_CMPL", 241 "MetricGroup": "cpi_breakdown", 242 "MetricName": "lsu_flush_next_stall_cpi" 243 }, 244 { 245 "BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned", 246 "MetricExpr": "PM_CMPLU_STALL_LSU_MFSPR/PM_RUN_INST_CMPL", 247 "MetricGroup": "cpi_breakdown", 248 "MetricName": "lsu_mfspr_stall_cpi" 249 }, 250 { 251 "BriefDescription": "Completion LSU stall for other reasons", 252 "MetricExpr": "(PM_CMPLU_STALL_LSU - PM_CMPLU_STALL_LSU_FIN - PM_CMPLU_STALL_STORE_FINISH - PM_CMPLU_STALL_STORE_DATA - PM_CMPLU_STALL_EIEIO - PM_CMPLU_STALL_STCX - PM_CMPLU_STALL_SLB - PM_CMPLU_STALL_TEND - PM_CMPLU_STALL_PASTE - PM_CMPLU_STALL_TLBIE - PM_CMPLU_STALL_STORE_PIPE_ARB - PM_CMPLU_STALL_STORE_FIN_ARB - PM_CMPLU_STALL_LOAD_FINISH + PM_CMPLU_STALL_DCACHE_MISS - PM_CMPLU_STALL_LMQ_FULL - PM_CMPLU_STALL_ST_FWD - PM_CMPLU_STALL_LHS - PM_CMPLU_STALL_LSU_MFSPR - PM_CMPLU_STALL_LARX - PM_CMPLU_STALL_LRQ_OTHER + PM_CMPLU_STALL_ERAT_MISS + PM_CMPLU_STALL_EMQ_FULL - PM_CMPLU_STALL_LRQ_FULL - PM_CMPLU_STALL_SRQ_FULL - PM_CMPLU_STALL_LSAQ_ARB) / PM_RUN_INST_CMPL", 253 "MetricGroup": "cpi_breakdown", 254 "MetricName": "lsu_other_stall_cpi" 255 }, 256 { 257 "BriefDescription": "Completion stall by LSU instruction", 258 "MetricExpr": "PM_CMPLU_STALL_LSU/PM_RUN_INST_CMPL", 259 "MetricGroup": "cpi_breakdown", 260 "MetricName": "lsu_stall_cpi" 261 }, 262 { 263 "BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)", 264 "MetricExpr": "PM_CMPLU_STALL_MTFPSCR/PM_RUN_INST_CMPL", 265 "MetricGroup": "cpi_breakdown", 266 "MetricName": "mtfpscr_stall_cpi" 267 }, 268 { 269 "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT", 270 "MetricExpr": "PM_CMPLU_STALL_NESTED_TBEGIN/PM_RUN_INST_CMPL", 271 "MetricGroup": "cpi_breakdown", 272 "MetricName": "nested_tbegin_stall_cpi" 273 }, 274 { 275 "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay", 276 "MetricExpr": "PM_CMPLU_STALL_NESTED_TEND/PM_RUN_INST_CMPL", 277 "MetricGroup": "cpi_breakdown", 278 "MetricName": "nested_tend_stall_cpi" 279 }, 280 { 281 "BriefDescription": "Number of cycles the ICT has no itags assigned to this thread", 282 "MetricExpr": "PM_ICT_NOSLOT_CYC/PM_RUN_INST_CMPL", 283 "MetricGroup": "cpi_breakdown", 284 "MetricName": "nothing_dispatched_cpi" 285 }, 286 { 287 "BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch.", 288 "MetricExpr": "PM_CMPLU_STALL_NTC_DISP_FIN/PM_RUN_INST_CMPL", 289 "MetricGroup": "cpi_breakdown", 290 "MetricName": "ntc_disp_fin_stall_cpi" 291 }, 292 { 293 "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack", 294 "MetricExpr": "PM_NTC_FIN/PM_RUN_INST_CMPL", 295 "MetricGroup": "cpi_breakdown", 296 "MetricName": "ntc_fin_cpi" 297 }, 298 { 299 "BriefDescription": "Completion stall due to ntc flush", 300 "MetricExpr": "PM_CMPLU_STALL_NTC_FLUSH/PM_RUN_INST_CMPL", 301 "MetricGroup": "cpi_breakdown", 302 "MetricName": "ntc_flush_stall_cpi" 303 }, 304 { 305 "BriefDescription": "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)", 306 "MetricExpr": "PM_NTC_ISSUE_HELD_ARB/PM_RUN_INST_CMPL", 307 "MetricGroup": "cpi_breakdown", 308 "MetricName": "ntc_issue_held_arb_cpi" 309 }, 310 { 311 "BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it", 312 "MetricExpr": "PM_NTC_ISSUE_HELD_DARQ_FULL/PM_RUN_INST_CMPL", 313 "MetricGroup": "cpi_breakdown", 314 "MetricName": "ntc_issue_held_darq_full_cpi" 315 }, 316 { 317 "BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU", 318 "MetricExpr": "PM_NTC_ISSUE_HELD_OTHER/PM_RUN_INST_CMPL", 319 "MetricGroup": "cpi_breakdown", 320 "MetricName": "ntc_issue_held_other_cpi" 321 }, 322 { 323 "BriefDescription": "Cycles unaccounted for.", 324 "MetricExpr": "(PM_RUN_CYC - PM_1PLUS_PPC_CMPL - PM_CMPLU_STALL_THRD - PM_CMPLU_STALL - PM_ICT_NOSLOT_CYC)/PM_RUN_INST_CMPL", 325 "MetricGroup": "cpi_breakdown", 326 "MetricName": "other_cpi" 327 }, 328 { 329 "BriefDescription": "Completion stall for other reasons", 330 "MetricExpr": "PM_CMPLU_STALL - PM_CMPLU_STALL_NTC_DISP_FIN - PM_CMPLU_STALL_NTC_FLUSH - PM_CMPLU_STALL_LSU - PM_CMPLU_STALL_EXEC_UNIT - PM_CMPLU_STALL_BRU)/PM_RUN_INST_CMPL", 331 "MetricGroup": "cpi_breakdown", 332 "MetricName": "other_stall_cpi" 333 }, 334 { 335 "BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response from L2", 336 "MetricExpr": "PM_CMPLU_STALL_PASTE/PM_RUN_INST_CMPL", 337 "MetricGroup": "cpi_breakdown", 338 "MetricName": "paste_stall_cpi" 339 }, 340 { 341 "BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish.", 342 "MetricExpr": "PM_CMPLU_STALL_PM/PM_RUN_INST_CMPL", 343 "MetricGroup": "cpi_breakdown", 344 "MetricName": "pm_stall_cpi" 345 }, 346 { 347 "BriefDescription": "Run cycles per run instruction", 348 "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL", 349 "MetricGroup": "cpi_breakdown", 350 "MetricName": "run_cpi" 351 }, 352 { 353 "BriefDescription": "Run_cycles", 354 "MetricExpr": "PM_RUN_CYC/PM_RUN_INST_CMPL", 355 "MetricGroup": "cpi_breakdown", 356 "MetricName": "run_cyc_cpi" 357 }, 358 { 359 "MetricExpr": "(PM_CMPLU_STALL_FXU + PM_CMPLU_STALL_DP + PM_CMPLU_STALL_DFU + PM_CMPLU_STALL_PM + PM_CMPLU_STALL_CRYPTO)/PM_RUN_INST_CMPL", 360 "MetricGroup": "cpi_breakdown", 361 "MetricName": "scalar_stall_cpi" 362 }, 363 { 364 "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB", 365 "MetricExpr": "PM_CMPLU_STALL_SLB/PM_RUN_INST_CMPL", 366 "MetricGroup": "cpi_breakdown", 367 "MetricName": "slb_stall_cpi" 368 }, 369 { 370 "BriefDescription": "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC", 371 "MetricExpr": "PM_CMPLU_STALL_SPEC_FINISH/PM_RUN_INST_CMPL", 372 "MetricGroup": "cpi_breakdown", 373 "MetricName": "spec_finish_stall_cpi" 374 }, 375 { 376 "BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full", 377 "MetricExpr": "PM_CMPLU_STALL_SRQ_FULL/PM_RUN_INST_CMPL", 378 "MetricGroup": "cpi_breakdown", 379 "MetricName": "srq_full_stall_cpi" 380 }, 381 { 382 "MetricExpr": "(PM_CMPLU_STALL_STORE_DATA + PM_CMPLU_STALL_EIEIO + PM_CMPLU_STALL_STCX + PM_CMPLU_STALL_SLB + PM_CMPLU_STALL_TEND + PM_CMPLU_STALL_PASTE + PM_CMPLU_STALL_TLBIE + PM_CMPLU_STALL_STORE_PIPE_ARB + PM_CMPLU_STALL_STORE_FIN_ARB)/PM_RUN_INST_CMPL", 383 "MetricGroup": "cpi_breakdown", 384 "MetricName": "srq_stall_cpi" 385 }, 386 { 387 "BriefDescription": "Completion stall due to store forward", 388 "MetricExpr": "PM_CMPLU_STALL_ST_FWD/PM_RUN_INST_CMPL", 389 "MetricGroup": "cpi_breakdown", 390 "MetricName": "st_fwd_stall_cpi" 391 }, 392 { 393 "BriefDescription": "Nothing completed and ICT not empty", 394 "MetricExpr": "PM_CMPLU_STALL/PM_RUN_INST_CMPL", 395 "MetricGroup": "cpi_breakdown", 396 "MetricName": "stall_cpi" 397 }, 398 { 399 "BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2", 400 "MetricExpr": "PM_CMPLU_STALL_STCX/PM_RUN_INST_CMPL", 401 "MetricGroup": "cpi_breakdown", 402 "MetricName": "stcx_stall_cpi" 403 }, 404 { 405 "BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data", 406 "MetricExpr": "PM_CMPLU_STALL_STORE_DATA/PM_RUN_INST_CMPL", 407 "MetricGroup": "cpi_breakdown", 408 "MetricName": "store_data_stall_cpi" 409 }, 410 { 411 "BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe", 412 "MetricExpr": "PM_CMPLU_STALL_STORE_FIN_ARB/PM_RUN_INST_CMPL", 413 "MetricGroup": "cpi_breakdown", 414 "MetricName": "store_fin_arb_stall_cpi" 415 }, 416 { 417 "BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish", 418 "MetricExpr": "PM_CMPLU_STALL_STORE_FINISH/PM_RUN_INST_CMPL", 419 "MetricGroup": "cpi_breakdown", 420 "MetricName": "store_finish_stall_cpi" 421 }, 422 { 423 "BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration", 424 "MetricExpr": "PM_CMPLU_STALL_STORE_PIPE_ARB/PM_RUN_INST_CMPL", 425 "MetricGroup": "cpi_breakdown", 426 "MetricName": "store_pipe_arb_stall_cpi" 427 }, 428 { 429 "BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2", 430 "MetricExpr": "PM_CMPLU_STALL_TEND/PM_RUN_INST_CMPL", 431 "MetricGroup": "cpi_breakdown", 432 "MetricName": "tend_stall_cpi" 433 }, 434 { 435 "BriefDescription": "Completion Stalled because the thread was blocked", 436 "MetricExpr": "PM_CMPLU_STALL_THRD/PM_RUN_INST_CMPL", 437 "MetricGroup": "cpi_breakdown", 438 "MetricName": "thread_block_stall_cpi" 439 }, 440 { 441 "BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2", 442 "MetricExpr": "PM_CMPLU_STALL_TLBIE/PM_RUN_INST_CMPL", 443 "MetricGroup": "cpi_breakdown", 444 "MetricName": "tlbie_stall_cpi" 445 }, 446 { 447 "BriefDescription": "Vector stalls due to small latency double precision ops", 448 "MetricExpr": "(PM_CMPLU_STALL_VDP - PM_CMPLU_STALL_VDPLONG)/PM_RUN_INST_CMPL", 449 "MetricGroup": "cpi_breakdown", 450 "MetricName": "vdp_other_stall_cpi" 451 }, 452 { 453 "BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish.", 454 "MetricExpr": "PM_CMPLU_STALL_VDP/PM_RUN_INST_CMPL", 455 "MetricGroup": "cpi_breakdown", 456 "MetricName": "vdp_stall_cpi" 457 }, 458 { 459 "BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format.", 460 "MetricExpr": "PM_CMPLU_STALL_VDPLONG/PM_RUN_INST_CMPL", 461 "MetricGroup": "cpi_breakdown", 462 "MetricName": "vdplong_stall_cpi" 463 }, 464 { 465 "MetricExpr": "(PM_CMPLU_STALL_VFXU + PM_CMPLU_STALL_VDP)/PM_RUN_INST_CMPL", 466 "MetricGroup": "cpi_breakdown", 467 "MetricName": "vector_stall_cpi" 468 }, 469 { 470 "BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)", 471 "MetricExpr": "PM_CMPLU_STALL_VFXLONG/PM_RUN_INST_CMPL", 472 "MetricGroup": "cpi_breakdown", 473 "MetricName": "vfxlong_stall_cpi" 474 }, 475 { 476 "BriefDescription": "Vector stalls due to small latency integer ops", 477 "MetricExpr": "(PM_CMPLU_STALL_VFXU - PM_CMPLU_STALL_VFXLONG)/PM_RUN_INST_CMPL", 478 "MetricGroup": "cpi_breakdown", 479 "MetricName": "vfxu_other_stall_cpi" 480 }, 481 { 482 "BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", 483 "MetricExpr": "PM_CMPLU_STALL_VFXU/PM_RUN_INST_CMPL", 484 "MetricGroup": "cpi_breakdown", 485 "MetricName": "vfxu_stall_cpi" 486 }, 487 { 488 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst", 489 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL", 490 "MetricGroup": "dl1_reloads_percent_per_inst", 491 "MetricName": "dl1_reload_from_dl2l3_mod_rate_percent" 492 }, 493 { 494 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst", 495 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL", 496 "MetricGroup": "dl1_reloads_percent_per_inst", 497 "MetricName": "dl1_reload_from_dl2l3_shr_rate_percent" 498 }, 499 { 500 "BriefDescription": "% of DL1 Reloads from Distant Memory per Inst", 501 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_RUN_INST_CMPL", 502 "MetricGroup": "dl1_reloads_percent_per_inst", 503 "MetricName": "dl1_reload_from_dmem_rate_percent" 504 }, 505 { 506 "BriefDescription": "% of DL1 reloads from Private L2, other core per Inst", 507 "MetricExpr": "PM_DATA_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL", 508 "MetricGroup": "dl1_reloads_percent_per_inst", 509 "MetricName": "dl1_reload_from_l21_mod_rate_percent" 510 }, 511 { 512 "BriefDescription": "% of DL1 reloads from Private L2, other core per Inst", 513 "MetricExpr": "PM_DATA_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL", 514 "MetricGroup": "dl1_reloads_percent_per_inst", 515 "MetricName": "dl1_reload_from_l21_shr_rate_percent" 516 }, 517 { 518 "BriefDescription": "% of DL1 reloads from L2 per Inst", 519 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL", 520 "MetricGroup": "dl1_reloads_percent_per_inst", 521 "MetricName": "dl1_reload_from_l2_miss_rate_percent" 522 }, 523 { 524 "BriefDescription": "% of DL1 reloads from L2 per Inst", 525 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_RUN_INST_CMPL", 526 "MetricGroup": "dl1_reloads_percent_per_inst", 527 "MetricName": "dl1_reload_from_l2_rate_percent" 528 }, 529 { 530 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst", 531 "MetricExpr": "PM_DATA_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL", 532 "MetricGroup": "dl1_reloads_percent_per_inst", 533 "MetricName": "dl1_reload_from_l31_mod_rate_percent" 534 }, 535 { 536 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst", 537 "MetricExpr": "PM_DATA_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL", 538 "MetricGroup": "dl1_reloads_percent_per_inst", 539 "MetricName": "dl1_reload_from_l31_shr_rate_percent" 540 }, 541 { 542 "BriefDescription": "% of DL1 Reloads that came from the L3 and were brought into the L3 by a prefetch, per instruction completed", 543 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_RUN_INST_CMPL", 544 "MetricGroup": "dl1_reloads_percent_per_inst", 545 "MetricName": "dl1_reload_from_l3_mepf_rate_percent" 546 }, 547 { 548 "BriefDescription": "% of DL1 reloads from L3 per Inst", 549 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL", 550 "MetricGroup": "dl1_reloads_percent_per_inst", 551 "MetricName": "dl1_reload_from_l3_miss_rate_percent" 552 }, 553 { 554 "BriefDescription": "% of DL1 Reloads from L3 per Inst", 555 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_RUN_INST_CMPL", 556 "MetricGroup": "dl1_reloads_percent_per_inst", 557 "MetricName": "dl1_reload_from_l3_rate_percent" 558 }, 559 { 560 "BriefDescription": "% of DL1 Reloads from Local Memory per Inst", 561 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 562 "MetricGroup": "dl1_reloads_percent_per_inst", 563 "MetricName": "dl1_reload_from_lmem_rate_percent" 564 }, 565 { 566 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst", 567 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL", 568 "MetricGroup": "dl1_reloads_percent_per_inst", 569 "MetricName": "dl1_reload_from_rl2l3_mod_rate_percent" 570 }, 571 { 572 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst", 573 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL", 574 "MetricGroup": "dl1_reloads_percent_per_inst", 575 "MetricName": "dl1_reload_from_rl2l3_shr_rate_percent" 576 }, 577 { 578 "BriefDescription": "% of DL1 Reloads from Remote Memory per Inst", 579 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_RUN_INST_CMPL", 580 "MetricGroup": "dl1_reloads_percent_per_inst", 581 "MetricName": "dl1_reload_from_rmem_rate_percent" 582 }, 583 { 584 "BriefDescription": "Percentage of L1 demand load misses per run instruction", 585 "MetricExpr": "PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL", 586 "MetricGroup": "dl1_reloads_percent_per_inst", 587 "MetricName": "l1_ld_miss_rate_percent" 588 }, 589 { 590 "BriefDescription": "% of DL1 misses that result in a cache reload", 591 "MetricExpr": "PM_L1_DCACHE_RELOAD_VALID * 100 / PM_LD_MISS_L1", 592 "MetricGroup": "dl1_reloads_percent_per_ref", 593 "MetricName": "dl1_miss_reloads_percent" 594 }, 595 { 596 "BriefDescription": "% of DL1 dL1_Reloads from Distant L2 or L3 (Modified)", 597 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 598 "MetricGroup": "dl1_reloads_percent_per_ref", 599 "MetricName": "dl1_reload_from_dl2l3_mod_percent" 600 }, 601 { 602 "BriefDescription": "% of DL1 dL1_Reloads from Distant L2 or L3 (Shared)", 603 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 604 "MetricGroup": "dl1_reloads_percent_per_ref", 605 "MetricName": "dl1_reload_from_dl2l3_shr_percent" 606 }, 607 { 608 "BriefDescription": "% of DL1 dL1_Reloads from Distant Memory", 609 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_L1_DCACHE_RELOAD_VALID", 610 "MetricGroup": "dl1_reloads_percent_per_ref", 611 "MetricName": "dl1_reload_from_dmem_percent" 612 }, 613 { 614 "BriefDescription": "% of DL1 reloads from Private L2, other core", 615 "MetricExpr": "PM_DATA_FROM_L21_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 616 "MetricGroup": "dl1_reloads_percent_per_ref", 617 "MetricName": "dl1_reload_from_l21_mod_percent" 618 }, 619 { 620 "BriefDescription": "% of DL1 reloads from Private L2, other core", 621 "MetricExpr": "PM_DATA_FROM_L21_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 622 "MetricGroup": "dl1_reloads_percent_per_ref", 623 "MetricName": "dl1_reload_from_l21_shr_percent" 624 }, 625 { 626 "BriefDescription": "% of DL1 Reloads from sources beyond the local L2", 627 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_L1_DCACHE_RELOAD_VALID", 628 "MetricGroup": "dl1_reloads_percent_per_ref", 629 "MetricName": "dl1_reload_from_l2_miss_percent" 630 }, 631 { 632 "BriefDescription": "% of DL1 reloads from L2", 633 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_L1_DCACHE_RELOAD_VALID", 634 "MetricGroup": "dl1_reloads_percent_per_ref", 635 "MetricName": "dl1_reload_from_l2_percent" 636 }, 637 { 638 "BriefDescription": "% of DL1 reloads from Private L3, other core", 639 "MetricExpr": "PM_DATA_FROM_L31_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 640 "MetricGroup": "dl1_reloads_percent_per_ref", 641 "MetricName": "dl1_reload_from_l31_mod_percent" 642 }, 643 { 644 "BriefDescription": "% of DL1 reloads from Private L3, other core", 645 "MetricExpr": "PM_DATA_FROM_L31_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 646 "MetricGroup": "dl1_reloads_percent_per_ref", 647 "MetricName": "dl1_reload_from_l31_shr_percent" 648 }, 649 { 650 "BriefDescription": "% of DL1 Reloads that came from L3 and were brought into the L3 by a prefetch", 651 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_L1_DCACHE_RELOAD_VALID", 652 "MetricGroup": "dl1_reloads_percent_per_ref", 653 "MetricName": "dl1_reload_from_l3_mepf_percent" 654 }, 655 { 656 "BriefDescription": "% of DL1 Reloads from sources beyond the local L3", 657 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_L1_DCACHE_RELOAD_VALID", 658 "MetricGroup": "dl1_reloads_percent_per_ref", 659 "MetricName": "dl1_reload_from_l3_miss_percent" 660 }, 661 { 662 "BriefDescription": "% of DL1 Reloads from L3", 663 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_L1_DCACHE_RELOAD_VALID", 664 "MetricGroup": "dl1_reloads_percent_per_ref", 665 "MetricName": "dl1_reload_from_l3_percent" 666 }, 667 { 668 "BriefDescription": "% of DL1 dL1_Reloads from Local Memory", 669 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_L1_DCACHE_RELOAD_VALID", 670 "MetricGroup": "dl1_reloads_percent_per_ref", 671 "MetricName": "dl1_reload_from_lmem_percent" 672 }, 673 { 674 "BriefDescription": "% of DL1 dL1_Reloads from Remote L2 or L3 (Modified)", 675 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 676 "MetricGroup": "dl1_reloads_percent_per_ref", 677 "MetricName": "dl1_reload_from_rl2l3_mod_percent" 678 }, 679 { 680 "BriefDescription": "% of DL1 dL1_Reloads from Remote L2 or L3 (Shared)", 681 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 682 "MetricGroup": "dl1_reloads_percent_per_ref", 683 "MetricName": "dl1_reload_from_rl2l3_shr_percent" 684 }, 685 { 686 "BriefDescription": "% of DL1 dL1_Reloads from Remote Memory", 687 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_L1_DCACHE_RELOAD_VALID", 688 "MetricGroup": "dl1_reloads_percent_per_ref", 689 "MetricName": "dl1_reload_from_rmem_percent" 690 }, 691 { 692 "BriefDescription": "estimate of dl2l3 distant MOD miss rates with measured DL2L3 MOD latency as a %of dcache miss cpi", 693 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * PM_MRK_DATA_FROM_DL2L3_MOD_CYC / PM_MRK_DATA_FROM_DL2L3_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 694 "MetricGroup": "estimated_dcache_miss_cpi", 695 "MetricName": "dl2l3_mod_cpi_percent" 696 }, 697 { 698 "BriefDescription": "estimate of dl2l3 distant SHR miss rates with measured DL2L3 SHR latency as a %of dcache miss cpi", 699 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * PM_MRK_DATA_FROM_DL2L3_SHR_CYC / PM_MRK_DATA_FROM_DL2L3_SHR / PM_CMPLU_STALL_DCACHE_MISS *100", 700 "MetricGroup": "estimated_dcache_miss_cpi", 701 "MetricName": "dl2l3_shr_cpi_percent" 702 }, 703 { 704 "BriefDescription": "estimate of distant L4 miss rates with measured DL4 latency as a %of dcache miss cpi", 705 "MetricExpr": "PM_DATA_FROM_DL4 * PM_MRK_DATA_FROM_DL4_CYC / PM_MRK_DATA_FROM_DL4 / PM_CMPLU_STALL_DCACHE_MISS *100", 706 "MetricGroup": "estimated_dcache_miss_cpi", 707 "MetricName": "dl4_cpi_percent" 708 }, 709 { 710 "BriefDescription": "estimate of distant memory miss rates with measured DMEM latency as a %of dcache miss cpi", 711 "MetricExpr": "PM_DATA_FROM_DMEM * PM_MRK_DATA_FROM_DMEM_CYC / PM_MRK_DATA_FROM_DMEM / PM_CMPLU_STALL_DCACHE_MISS *100", 712 "MetricGroup": "estimated_dcache_miss_cpi", 713 "MetricName": "dmem_cpi_percent" 714 }, 715 { 716 "BriefDescription": "estimate of dl21 MOD miss rates with measured L21 MOD latency as a %of dcache miss cpi", 717 "MetricExpr": "PM_DATA_FROM_L21_MOD * PM_MRK_DATA_FROM_L21_MOD_CYC / PM_MRK_DATA_FROM_L21_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 718 "MetricGroup": "estimated_dcache_miss_cpi", 719 "MetricName": "l21_mod_cpi_percent" 720 }, 721 { 722 "BriefDescription": "estimate of dl21 SHR miss rates with measured L21 SHR latency as a %of dcache miss cpi", 723 "MetricExpr": "PM_DATA_FROM_L21_SHR * PM_MRK_DATA_FROM_L21_SHR_CYC / PM_MRK_DATA_FROM_L21_SHR / PM_CMPLU_STALL_DCACHE_MISS *100", 724 "MetricGroup": "estimated_dcache_miss_cpi", 725 "MetricName": "l21_shr_cpi_percent" 726 }, 727 { 728 "BriefDescription": "estimate of dl2 miss rates with measured L2 latency as a %of dcache miss cpi", 729 "MetricExpr": "PM_DATA_FROM_L2 * PM_MRK_DATA_FROM_L2_CYC / PM_MRK_DATA_FROM_L2 / PM_CMPLU_STALL_DCACHE_MISS *100", 730 "MetricGroup": "estimated_dcache_miss_cpi", 731 "MetricName": "l2_cpi_percent" 732 }, 733 { 734 "BriefDescription": "estimate of dl31 MOD miss rates with measured L31 MOD latency as a %of dcache miss cpi", 735 "MetricExpr": "PM_DATA_FROM_L31_MOD * PM_MRK_DATA_FROM_L31_MOD_CYC / PM_MRK_DATA_FROM_L31_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 736 "MetricGroup": "estimated_dcache_miss_cpi", 737 "MetricName": "l31_mod_cpi_percent" 738 }, 739 { 740 "BriefDescription": "estimate of dl31 SHR miss rates with measured L31 SHR latency as a %of dcache miss cpi", 741 "MetricExpr": "PM_DATA_FROM_L31_SHR * PM_MRK_DATA_FROM_L31_SHR_CYC / PM_MRK_DATA_FROM_L31_SHR / PM_CMPLU_STALL_DCACHE_MISS *100", 742 "MetricGroup": "estimated_dcache_miss_cpi", 743 "MetricName": "l31_shr_cpi_percent" 744 }, 745 { 746 "BriefDescription": "estimate of dl3 miss rates with measured L3 latency as a % of dcache miss cpi", 747 "MetricExpr": "PM_DATA_FROM_L3 * PM_MRK_DATA_FROM_L3_CYC / PM_MRK_DATA_FROM_L3 / PM_CMPLU_STALL_DCACHE_MISS * 100", 748 "MetricGroup": "estimated_dcache_miss_cpi", 749 "MetricName": "l3_cpi_percent" 750 }, 751 { 752 "BriefDescription": "estimate of Local memory miss rates with measured LMEM latency as a %of dcache miss cpi", 753 "MetricExpr": "PM_DATA_FROM_LMEM * PM_MRK_DATA_FROM_LMEM_CYC / PM_MRK_DATA_FROM_LMEM / PM_CMPLU_STALL_DCACHE_MISS *100", 754 "MetricGroup": "estimated_dcache_miss_cpi", 755 "MetricName": "lmem_cpi_percent" 756 }, 757 { 758 "BriefDescription": "estimate of dl2l3 remote MOD miss rates with measured RL2L3 MOD latency as a %of dcache miss cpi", 759 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * PM_MRK_DATA_FROM_RL2L3_MOD_CYC / PM_MRK_DATA_FROM_RL2L3_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 760 "MetricGroup": "estimated_dcache_miss_cpi", 761 "MetricName": "rl2l3_mod_cpi_percent" 762 }, 763 { 764 "BriefDescription": "estimate of dl2l3 shared miss rates with measured RL2L3 SHR latency as a %of dcache miss cpi", 765 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * PM_MRK_DATA_FROM_RL2L3_SHR_CYC / PM_MRK_DATA_FROM_RL2L3_SHR / PM_CMPLU_STALL_DCACHE_MISS * 100", 766 "MetricGroup": "estimated_dcache_miss_cpi", 767 "MetricName": "rl2l3_shr_cpi_percent" 768 }, 769 { 770 "BriefDescription": "estimate of remote L4 miss rates with measured RL4 latency as a %of dcache miss cpi", 771 "MetricExpr": "PM_DATA_FROM_RL4 * PM_MRK_DATA_FROM_RL4_CYC / PM_MRK_DATA_FROM_RL4 / PM_CMPLU_STALL_DCACHE_MISS *100", 772 "MetricGroup": "estimated_dcache_miss_cpi", 773 "MetricName": "rl4_cpi_percent" 774 }, 775 { 776 "BriefDescription": "estimate of remote memory miss rates with measured RMEM latency as a %of dcache miss cpi", 777 "MetricExpr": "PM_DATA_FROM_RMEM * PM_MRK_DATA_FROM_RMEM_CYC / PM_MRK_DATA_FROM_RMEM / PM_CMPLU_STALL_DCACHE_MISS *100", 778 "MetricGroup": "estimated_dcache_miss_cpi", 779 "MetricName": "rmem_cpi_percent" 780 }, 781 { 782 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Modified) per Inst", 783 "MetricExpr": "PM_INST_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL", 784 "MetricGroup": "instruction_misses_percent_per_inst", 785 "MetricName": "inst_from_dl2l3_mod_rate_percent" 786 }, 787 { 788 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Shared) per Inst", 789 "MetricExpr": "PM_INST_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL", 790 "MetricGroup": "instruction_misses_percent_per_inst", 791 "MetricName": "inst_from_dl2l3_shr_rate_percent" 792 }, 793 { 794 "BriefDescription": "% of ICache reloads from Distant L4 per Inst", 795 "MetricExpr": "PM_INST_FROM_DL4 * 100 / PM_RUN_INST_CMPL", 796 "MetricGroup": "instruction_misses_percent_per_inst", 797 "MetricName": "inst_from_dl4_rate_percent" 798 }, 799 { 800 "BriefDescription": "% of ICache reloads from Distant Memory per Inst", 801 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_RUN_INST_CMPL", 802 "MetricGroup": "instruction_misses_percent_per_inst", 803 "MetricName": "inst_from_dmem_rate_percent" 804 }, 805 { 806 "BriefDescription": "% of ICache reloads from Private L2, other core per Inst", 807 "MetricExpr": "PM_INST_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL", 808 "MetricGroup": "instruction_misses_percent_per_inst", 809 "MetricName": "inst_from_l21_mod_rate_percent" 810 }, 811 { 812 "BriefDescription": "% of ICache reloads from Private L2, other core per Inst", 813 "MetricExpr": "PM_INST_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL", 814 "MetricGroup": "instruction_misses_percent_per_inst", 815 "MetricName": "inst_from_l21_shr_rate_percent" 816 }, 817 { 818 "BriefDescription": "% of ICache reloads from L2 per Inst", 819 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL", 820 "MetricGroup": "instruction_misses_percent_per_inst", 821 "MetricName": "inst_from_l2_rate_percent" 822 }, 823 { 824 "BriefDescription": "% of ICache reloads from Private L3, other core per Inst", 825 "MetricExpr": "PM_INST_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL", 826 "MetricGroup": "instruction_misses_percent_per_inst", 827 "MetricName": "inst_from_l31_mod_rate_percent" 828 }, 829 { 830 "BriefDescription": "% of ICache reloads from Private L3 other core per Inst", 831 "MetricExpr": "PM_INST_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL", 832 "MetricGroup": "instruction_misses_percent_per_inst", 833 "MetricName": "inst_from_l31_shr_rate_percent" 834 }, 835 { 836 "BriefDescription": "% of ICache reloads from L3 per Inst", 837 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_RUN_INST_CMPL", 838 "MetricGroup": "instruction_misses_percent_per_inst", 839 "MetricName": "inst_from_l3_rate_percent" 840 }, 841 { 842 "BriefDescription": "% of ICache reloads from Local L4 per Inst", 843 "MetricExpr": "PM_INST_FROM_LL4 * 100 / PM_RUN_INST_CMPL", 844 "MetricGroup": "instruction_misses_percent_per_inst", 845 "MetricName": "inst_from_ll4_rate_percent" 846 }, 847 { 848 "BriefDescription": "% of ICache reloads from Local Memory per Inst", 849 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 850 "MetricGroup": "instruction_misses_percent_per_inst", 851 "MetricName": "inst_from_lmem_rate_percent" 852 }, 853 { 854 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Modified) per Inst", 855 "MetricExpr": "PM_INST_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL", 856 "MetricGroup": "instruction_misses_percent_per_inst", 857 "MetricName": "inst_from_rl2l3_mod_rate_percent" 858 }, 859 { 860 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Shared) per Inst", 861 "MetricExpr": "PM_INST_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL", 862 "MetricGroup": "instruction_misses_percent_per_inst", 863 "MetricName": "inst_from_rl2l3_shr_rate_percent" 864 }, 865 { 866 "BriefDescription": "% of ICache reloads from Remote L4 per Inst", 867 "MetricExpr": "PM_INST_FROM_RL4 * 100 / PM_RUN_INST_CMPL", 868 "MetricGroup": "instruction_misses_percent_per_inst", 869 "MetricName": "inst_from_rl4_rate_percent" 870 }, 871 { 872 "BriefDescription": "% of ICache reloads from Remote Memory per Inst", 873 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL", 874 "MetricGroup": "instruction_misses_percent_per_inst", 875 "MetricName": "inst_from_rmem_rate_percent" 876 }, 877 { 878 "BriefDescription": "Instruction Cache Miss Rate (Per run Instruction)(%)", 879 "MetricExpr": "PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL", 880 "MetricGroup": "instruction_misses_percent_per_inst", 881 "MetricName": "l1_inst_miss_rate_percent" 882 }, 883 { 884 "BriefDescription": "%L2 Modified CO Cache read Utilization (4 pclks per disp attempt)", 885 "MetricExpr": "((PM_L2_CASTOUT_MOD/2)*4)/ PM_RUN_CYC * 100", 886 "MetricGroup": "l2_stats", 887 "MetricName": "l2_co_m_rd_util" 888 }, 889 { 890 "BriefDescription": "L2 dcache invalidates per run inst (per core)", 891 "MetricExpr": "(PM_L2_DC_INV / 2) / PM_RUN_INST_CMPL * 100", 892 "MetricGroup": "l2_stats", 893 "MetricName": "l2_dc_inv_rate_percent" 894 }, 895 { 896 "BriefDescription": "Demand load misses as a % of L2 LD dispatches (per thread)", 897 "MetricExpr": "PM_L1_DCACHE_RELOAD_VALID / (PM_L2_LD / 2) * 100", 898 "MetricGroup": "l2_stats", 899 "MetricName": "l2_dem_ld_disp_percent" 900 }, 901 { 902 "BriefDescription": "L2 Icache invalidates per run inst (per core)", 903 "MetricExpr": "(PM_L2_IC_INV / 2) / PM_RUN_INST_CMPL * 100", 904 "MetricGroup": "l2_stats", 905 "MetricName": "l2_ic_inv_rate_percent" 906 }, 907 { 908 "BriefDescription": "L2 Inst misses as a % of total L2 Inst dispatches (per thread)", 909 "MetricExpr": "PM_L2_INST_MISS / PM_L2_INST * 100", 910 "MetricGroup": "l2_stats", 911 "MetricName": "l2_inst_miss_ratio_percent" 912 }, 913 { 914 "BriefDescription": "Average number of cycles between L2 Load hits", 915 "MetricExpr": "(PM_L2_LD_HIT / PM_RUN_CYC) / 2", 916 "MetricGroup": "l2_stats", 917 "MetricName": "l2_ld_hit_frequency" 918 }, 919 { 920 "BriefDescription": "Average number of cycles between L2 Load misses", 921 "MetricExpr": "(PM_L2_LD_MISS / PM_RUN_CYC) / 2", 922 "MetricGroup": "l2_stats", 923 "MetricName": "l2_ld_miss_frequency" 924 }, 925 { 926 "BriefDescription": "L2 Load misses as a % of total L2 Load dispatches (per thread)", 927 "MetricExpr": "PM_L2_LD_MISS / PM_L2_LD * 100", 928 "MetricGroup": "l2_stats", 929 "MetricName": "l2_ld_miss_ratio_percent" 930 }, 931 { 932 "BriefDescription": "% L2 load disp attempts Cache read Utilization (4 pclks per disp attempt)", 933 "MetricExpr": "((PM_L2_RCLD_DISP/2)*4)/ PM_RUN_CYC * 100", 934 "MetricGroup": "l2_stats", 935 "MetricName": "l2_ld_rd_util" 936 }, 937 { 938 "BriefDescription": "L2 load misses that require a cache write (4 pclks per disp attempt) % of pclks", 939 "MetricExpr": "((( PM_L2_LD_DISP - PM_L2_LD_HIT)/2)*4)/ PM_RUN_CYC * 100", 940 "MetricGroup": "l2_stats", 941 "MetricName": "l2_ldmiss_wr_util" 942 }, 943 { 944 "BriefDescription": "L2 local pump prediction success", 945 "MetricExpr": "PM_L2_LOC_GUESS_CORRECT / (PM_L2_LOC_GUESS_CORRECT + PM_L2_LOC_GUESS_WRONG) * 100", 946 "MetricGroup": "l2_stats", 947 "MetricName": "l2_local_pred_correct_percent" 948 }, 949 { 950 "BriefDescription": "L2 COs that were in M,Me,Mu state as a % of all L2 COs", 951 "MetricExpr": "PM_L2_CASTOUT_MOD / (PM_L2_CASTOUT_MOD + PM_L2_CASTOUT_SHR) * 100", 952 "MetricGroup": "l2_stats", 953 "MetricName": "l2_mod_co_percent" 954 }, 955 { 956 "BriefDescription": "% of L2 Load RC dispatch atampts that failed because of address collisions and cclass conflicts", 957 "MetricExpr": "(PM_L2_RCLD_DISP_FAIL_ADDR )/ PM_L2_RCLD_DISP * 100", 958 "MetricGroup": "l2_stats", 959 "MetricName": "l2_rc_ld_disp_addr_fail_percent" 960 }, 961 { 962 "BriefDescription": "% of L2 Load RC dispatch attempts that failed", 963 "MetricExpr": "(PM_L2_RCLD_DISP_FAIL_ADDR + PM_L2_RCLD_DISP_FAIL_OTHER)/ PM_L2_RCLD_DISP * 100", 964 "MetricGroup": "l2_stats", 965 "MetricName": "l2_rc_ld_disp_fail_percent" 966 }, 967 { 968 "BriefDescription": "% of L2 Store RC dispatch atampts that failed because of address collisions and cclass conflicts", 969 "MetricExpr": "PM_L2_RCST_DISP_FAIL_ADDR / PM_L2_RCST_DISP * 100", 970 "MetricGroup": "l2_stats", 971 "MetricName": "l2_rc_st_disp_addr_fail_percent" 972 }, 973 { 974 "BriefDescription": "% of L2 Store RC dispatch attempts that failed", 975 "MetricExpr": "(PM_L2_RCST_DISP_FAIL_ADDR + PM_L2_RCST_DISP_FAIL_OTHER)/ PM_L2_RCST_DISP * 100", 976 "MetricGroup": "l2_stats", 977 "MetricName": "l2_rc_st_disp_fail_percent" 978 }, 979 { 980 "BriefDescription": "L2 Cache Read Utilization (per core)", 981 "MetricExpr": "(((PM_L2_RCLD_DISP/2)*4)/ PM_RUN_CYC * 100) + (((PM_L2_RCST_DISP/2)*4)/PM_RUN_CYC * 100) + (((PM_L2_CASTOUT_MOD/2)*4)/PM_RUN_CYC * 100)", 982 "MetricGroup": "l2_stats", 983 "MetricName": "l2_rd_util_percent" 984 }, 985 { 986 "BriefDescription": "L2 COs that were in T,Te,Si,S state as a % of all L2 COs", 987 "MetricExpr": "PM_L2_CASTOUT_SHR / (PM_L2_CASTOUT_MOD + PM_L2_CASTOUT_SHR) * 100", 988 "MetricGroup": "l2_stats", 989 "MetricName": "l2_shr_co_percent" 990 }, 991 { 992 "BriefDescription": "L2 Store misses as a % of total L2 Store dispatches (per thread)", 993 "MetricExpr": "PM_L2_ST_MISS / PM_L2_ST * 100", 994 "MetricGroup": "l2_stats", 995 "MetricName": "l2_st_miss_ratio_percent" 996 }, 997 { 998 "BriefDescription": "% L2 store disp attempts Cache read Utilization (4 pclks per disp attempt)", 999 "MetricExpr": "((PM_L2_RCST_DISP/2)*4) / PM_RUN_CYC * 100", 1000 "MetricGroup": "l2_stats", 1001 "MetricName": "l2_st_rd_util" 1002 }, 1003 { 1004 "BriefDescription": "L2 stores that require a cache write (4 pclks per disp attempt) % of pclks", 1005 "MetricExpr": "((PM_L2_ST_DISP/2)*4) / PM_RUN_CYC * 100", 1006 "MetricGroup": "l2_stats", 1007 "MetricName": "l2_st_wr_util" 1008 }, 1009 { 1010 "BriefDescription": "L2 Cache Write Utilization (per core)", 1011 "MetricExpr": "((((PM_L2_LD_DISP - PM_L2_LD_HIT)/2)*4) / PM_RUN_CYC * 100) + (((PM_L2_ST_DISP/2)*4) / PM_RUN_CYC * 100)", 1012 "MetricGroup": "l2_stats", 1013 "MetricName": "l2_wr_util_percent" 1014 }, 1015 { 1016 "BriefDescription": "Average number of cycles between L3 Load hits", 1017 "MetricExpr": "(PM_L3_LD_HIT / PM_RUN_CYC) / 2", 1018 "MetricGroup": "l3_stats", 1019 "MetricName": "l3_ld_hit_frequency" 1020 }, 1021 { 1022 "BriefDescription": "Average number of cycles between L3 Load misses", 1023 "MetricExpr": "(PM_L3_LD_MISS / PM_RUN_CYC) / 2", 1024 "MetricGroup": "l3_stats", 1025 "MetricName": "l3_ld_miss_frequency" 1026 }, 1027 { 1028 "BriefDescription": "Average number of Write-in machines used. 1 of 8 WI machines is sampled every L3 cycle", 1029 "MetricExpr": "(PM_L3_WI_USAGE / PM_RUN_CYC) * 8", 1030 "MetricGroup": "l3_stats", 1031 "MetricName": "l3_wi_usage" 1032 }, 1033 { 1034 "BriefDescription": "DERAT Miss Rate (per run instruction)(%)", 1035 "MetricExpr": "PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL", 1036 "MetricGroup": "pteg_reloads_percent_per_inst", 1037 "MetricName": "derat_miss_rate_percent" 1038 }, 1039 { 1040 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Modified) per inst", 1041 "MetricExpr": "PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL", 1042 "MetricGroup": "pteg_reloads_percent_per_inst", 1043 "MetricName": "pteg_from_dl2l3_mod_rate_percent" 1044 }, 1045 { 1046 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Shared) per inst", 1047 "MetricExpr": "PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL", 1048 "MetricGroup": "pteg_reloads_percent_per_inst", 1049 "MetricName": "pteg_from_dl2l3_shr_rate_percent" 1050 }, 1051 { 1052 "BriefDescription": "% of DERAT reloads from Distant L4 per inst", 1053 "MetricExpr": "PM_DPTEG_FROM_DL4 * 100 / PM_RUN_INST_CMPL", 1054 "MetricGroup": "pteg_reloads_percent_per_inst", 1055 "MetricName": "pteg_from_dl4_rate_percent" 1056 }, 1057 { 1058 "BriefDescription": "% of DERAT reloads from Distant Memory per inst", 1059 "MetricExpr": "PM_DPTEG_FROM_DMEM * 100 / PM_RUN_INST_CMPL", 1060 "MetricGroup": "pteg_reloads_percent_per_inst", 1061 "MetricName": "pteg_from_dmem_rate_percent" 1062 }, 1063 { 1064 "BriefDescription": "% of DERAT reloads from Private L2, other core per inst", 1065 "MetricExpr": "PM_DPTEG_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL", 1066 "MetricGroup": "pteg_reloads_percent_per_inst", 1067 "MetricName": "pteg_from_l21_mod_rate_percent" 1068 }, 1069 { 1070 "BriefDescription": "% of DERAT reloads from Private L2, other core per inst", 1071 "MetricExpr": "PM_DPTEG_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL", 1072 "MetricGroup": "pteg_reloads_percent_per_inst", 1073 "MetricName": "pteg_from_l21_shr_rate_percent" 1074 }, 1075 { 1076 "BriefDescription": "% of DERAT reloads from L2 per inst", 1077 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL", 1078 "MetricGroup": "pteg_reloads_percent_per_inst", 1079 "MetricName": "pteg_from_l2_rate_percent" 1080 }, 1081 { 1082 "BriefDescription": "% of DERAT reloads from Private L3, other core per inst", 1083 "MetricExpr": "PM_DPTEG_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL", 1084 "MetricGroup": "pteg_reloads_percent_per_inst", 1085 "MetricName": "pteg_from_l31_mod_rate_percent" 1086 }, 1087 { 1088 "BriefDescription": "% of DERAT reloads from Private L3, other core per inst", 1089 "MetricExpr": "PM_DPTEG_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL", 1090 "MetricGroup": "pteg_reloads_percent_per_inst", 1091 "MetricName": "pteg_from_l31_shr_rate_percent" 1092 }, 1093 { 1094 "BriefDescription": "% of DERAT reloads from L3 per inst", 1095 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL", 1096 "MetricGroup": "pteg_reloads_percent_per_inst", 1097 "MetricName": "pteg_from_l3_rate_percent" 1098 }, 1099 { 1100 "BriefDescription": "% of DERAT reloads from Local L4 per inst", 1101 "MetricExpr": "PM_DPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL", 1102 "MetricGroup": "pteg_reloads_percent_per_inst", 1103 "MetricName": "pteg_from_ll4_rate_percent" 1104 }, 1105 { 1106 "BriefDescription": "% of DERAT reloads from Local Memory per inst", 1107 "MetricExpr": "PM_DPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 1108 "MetricGroup": "pteg_reloads_percent_per_inst", 1109 "MetricName": "pteg_from_lmem_rate_percent" 1110 }, 1111 { 1112 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Modified) per inst", 1113 "MetricExpr": "PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL", 1114 "MetricGroup": "pteg_reloads_percent_per_inst", 1115 "MetricName": "pteg_from_rl2l3_mod_rate_percent" 1116 }, 1117 { 1118 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Shared) per inst", 1119 "MetricExpr": "PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL", 1120 "MetricGroup": "pteg_reloads_percent_per_inst", 1121 "MetricName": "pteg_from_rl2l3_shr_rate_percent" 1122 }, 1123 { 1124 "BriefDescription": "% of DERAT reloads from Remote L4 per inst", 1125 "MetricExpr": "PM_DPTEG_FROM_RL4 * 100 / PM_RUN_INST_CMPL", 1126 "MetricGroup": "pteg_reloads_percent_per_inst", 1127 "MetricName": "pteg_from_rl4_rate_percent" 1128 }, 1129 { 1130 "BriefDescription": "% of DERAT reloads from Remote Memory per inst", 1131 "MetricExpr": "PM_DPTEG_FROM_RMEM * 100 / PM_RUN_INST_CMPL", 1132 "MetricGroup": "pteg_reloads_percent_per_inst", 1133 "MetricName": "pteg_from_rmem_rate_percent" 1134 }, 1135 { 1136 "BriefDescription": "% of DERAT misses that result in an ERAT reload", 1137 "MetricExpr": "PM_DTLB_MISS * 100 / PM_LSU_DERAT_MISS", 1138 "MetricGroup": "pteg_reloads_percent_per_ref", 1139 "MetricName": "derat_miss_reload_percent" 1140 }, 1141 { 1142 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Modified)", 1143 "MetricExpr": "PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_DTLB_MISS", 1144 "MetricGroup": "pteg_reloads_percent_per_ref", 1145 "MetricName": "pteg_from_dl2l3_mod_percent" 1146 }, 1147 { 1148 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Shared)", 1149 "MetricExpr": "PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_DTLB_MISS", 1150 "MetricGroup": "pteg_reloads_percent_per_ref", 1151 "MetricName": "pteg_from_dl2l3_shr_percent" 1152 }, 1153 { 1154 "BriefDescription": "% of DERAT reloads from Distant L4", 1155 "MetricExpr": "PM_DPTEG_FROM_DL4 * 100 / PM_DTLB_MISS", 1156 "MetricGroup": "pteg_reloads_percent_per_ref", 1157 "MetricName": "pteg_from_dl4_percent" 1158 }, 1159 { 1160 "BriefDescription": "% of DERAT reloads from Distant Memory", 1161 "MetricExpr": "PM_DPTEG_FROM_DMEM * 100 / PM_DTLB_MISS", 1162 "MetricGroup": "pteg_reloads_percent_per_ref", 1163 "MetricName": "pteg_from_dmem_percent" 1164 }, 1165 { 1166 "BriefDescription": "% of DERAT reloads from Private L2, other core", 1167 "MetricExpr": "PM_DPTEG_FROM_L21_MOD * 100 / PM_DTLB_MISS", 1168 "MetricGroup": "pteg_reloads_percent_per_ref", 1169 "MetricName": "pteg_from_l21_mod_percent" 1170 }, 1171 { 1172 "BriefDescription": "% of DERAT reloads from Private L2, other core", 1173 "MetricExpr": "PM_DPTEG_FROM_L21_SHR * 100 / PM_DTLB_MISS", 1174 "MetricGroup": "pteg_reloads_percent_per_ref", 1175 "MetricName": "pteg_from_l21_shr_percent" 1176 }, 1177 { 1178 "BriefDescription": "% of DERAT reloads from L2", 1179 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_DTLB_MISS", 1180 "MetricGroup": "pteg_reloads_percent_per_ref", 1181 "MetricName": "pteg_from_l2_percent" 1182 }, 1183 { 1184 "BriefDescription": "% of DERAT reloads from Private L3, other core", 1185 "MetricExpr": "PM_DPTEG_FROM_L31_MOD * 100 / PM_DTLB_MISS", 1186 "MetricGroup": "pteg_reloads_percent_per_ref", 1187 "MetricName": "pteg_from_l31_mod_percent" 1188 }, 1189 { 1190 "BriefDescription": "% of DERAT reloads from Private L3, other core", 1191 "MetricExpr": "PM_DPTEG_FROM_L31_SHR * 100 / PM_DTLB_MISS", 1192 "MetricGroup": "pteg_reloads_percent_per_ref", 1193 "MetricName": "pteg_from_l31_shr_percent" 1194 }, 1195 { 1196 "BriefDescription": "% of DERAT reloads from L3", 1197 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_DTLB_MISS", 1198 "MetricGroup": "pteg_reloads_percent_per_ref", 1199 "MetricName": "pteg_from_l3_percent" 1200 }, 1201 { 1202 "BriefDescription": "% of DERAT reloads from Local L4", 1203 "MetricExpr": "PM_DPTEG_FROM_LL4 * 100 / PM_DTLB_MISS", 1204 "MetricGroup": "pteg_reloads_percent_per_ref", 1205 "MetricName": "pteg_from_ll4_percent" 1206 }, 1207 { 1208 "BriefDescription": "% of DERAT reloads from Local Memory", 1209 "MetricExpr": "PM_DPTEG_FROM_LMEM * 100 / PM_DTLB_MISS", 1210 "MetricGroup": "pteg_reloads_percent_per_ref", 1211 "MetricName": "pteg_from_lmem_percent" 1212 }, 1213 { 1214 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Modified)", 1215 "MetricExpr": "PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_DTLB_MISS", 1216 "MetricGroup": "pteg_reloads_percent_per_ref", 1217 "MetricName": "pteg_from_rl2l3_mod_percent" 1218 }, 1219 { 1220 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Shared)", 1221 "MetricExpr": "PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_DTLB_MISS", 1222 "MetricGroup": "pteg_reloads_percent_per_ref", 1223 "MetricName": "pteg_from_rl2l3_shr_percent" 1224 }, 1225 { 1226 "BriefDescription": "% of DERAT reloads from Remote L4", 1227 "MetricExpr": "PM_DPTEG_FROM_RL4 * 100 / PM_DTLB_MISS", 1228 "MetricGroup": "pteg_reloads_percent_per_ref", 1229 "MetricName": "pteg_from_rl4_percent" 1230 }, 1231 { 1232 "BriefDescription": "% of DERAT reloads from Remote Memory", 1233 "MetricExpr": "PM_DPTEG_FROM_RMEM * 100 / PM_DTLB_MISS", 1234 "MetricGroup": "pteg_reloads_percent_per_ref", 1235 "MetricName": "pteg_from_rmem_percent" 1236 } 1237] 1238