1[
2  {
3    "EventCode": "0x100FE",
4    "EventName": "PM_INST_CMPL",
5    "BriefDescription": "PowerPC instructions completed."
6  },
7  {
8    "EventCode": "0x1000C",
9    "EventName": "PM_LSU_LD0_FIN",
10    "BriefDescription": "LSU Finished an internal operation in LD0 port."
11  },
12  {
13    "EventCode": "0x1000E",
14    "EventName": "PM_MMA_ISSUED",
15    "BriefDescription": "MMA instructions issued."
16  },
17  {
18    "EventCode": "0x10012",
19    "EventName": "PM_LSU_ST0_FIN",
20    "BriefDescription": "LSU Finished an internal operation in ST0 port."
21  },
22  {
23    "EventCode": "0x10014",
24    "EventName": "PM_LSU_ST4_FIN",
25    "BriefDescription": "LSU Finished an internal operation in ST4 port."
26  },
27  {
28    "EventCode": "0x10018",
29    "EventName": "PM_IC_DEMAND_CYC",
30    "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
31  },
32  {
33    "EventCode": "0x10022",
34    "EventName": "PM_PMC2_SAVED",
35    "BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
36  },
37  {
38    "EventCode": "0x10024",
39    "EventName": "PM_PMC5_OVERFLOW",
40    "BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
41  },
42  {
43    "EventCode": "0x10058",
44    "EventName": "PM_EXEC_STALL_FIN_AT_DISP",
45    "BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
46  },
47  {
48    "EventCode": "0x1005A",
49    "EventName": "PM_FLUSH_MPRED",
50    "BriefDescription": "A flush occurred due to a mispredicted branch. Includes target and direction."
51  },
52  {
53    "EventCode": "0x1C05A",
54    "EventName": "PM_DERAT_MISS_2M",
55    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
56  },
57  {
58    "EventCode": "0x1E05A",
59    "EventName": "PM_CMPL_STALL_LWSYNC",
60    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete."
61  },
62  {
63    "EventCode": "0x10068",
64    "EventName": "PM_BR_FIN",
65    "BriefDescription": "A branch instruction finished. Includes predicted/mispredicted/unconditional."
66  },
67  {
68    "EventCode": "0x1006A",
69    "EventName": "PM_FX_LSU_FIN",
70    "BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish time."
71  },
72  {
73    "EventCode": "0x1006C",
74    "EventName": "PM_RUN_CYC_ST_MODE",
75    "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
76  },
77  {
78    "EventCode": "0x20004",
79    "EventName": "PM_ISSUE_STALL",
80    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet."
81  },
82  {
83    "EventCode": "0x2000A",
84    "EventName": "PM_HYPERVISOR_CYC",
85    "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
86  },
87  {
88    "EventCode": "0x2000E",
89    "EventName": "PM_LSU_LD1_FIN",
90    "BriefDescription": "LSU Finished an internal operation in LD1 port."
91  },
92  {
93    "EventCode": "0x2C014",
94    "EventName": "PM_CMPL_STALL_SPECIAL",
95    "BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handling before completing."
96  },
97  {
98    "EventCode": "0x2C018",
99    "EventName": "PM_EXEC_STALL_DMISS_L3MISS",
100    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
101  },
102  {
103    "EventCode": "0x2D010",
104    "EventName": "PM_LSU_ST1_FIN",
105    "BriefDescription": "LSU Finished an internal operation in ST1 port."
106  },
107  {
108    "EventCode": "0x2D012",
109    "EventName": "PM_VSU1_ISSUE",
110    "BriefDescription": "VSU instructions issued to VSU pipe 1."
111  },
112  {
113    "EventCode": "0x2D018",
114    "EventName": "PM_EXEC_STALL_VSU",
115    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU)."
116  },
117  {
118    "EventCode": "0x2D01C",
119    "EventName": "PM_CMPL_STALL_STCX",
120    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
121  },
122  {
123    "EventCode": "0x2E01E",
124    "EventName": "PM_EXEC_STALL_NTC_FLUSH",
125    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children. This event will also count cycles when the previous NTF instruction is still completing and the new NTF instruction is stalled at dispatch."
126  },
127  {
128    "EventCode": "0x2013C",
129    "EventName": "PM_MRK_FX_LSU_FIN",
130    "BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
131  },
132  {
133    "EventCode": "0x2405A",
134    "EventName": "PM_NTC_FIN",
135    "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
136  },
137  {
138    "EventCode": "0x201E2",
139    "EventName": "PM_MRK_LD_MISS_L1",
140    "BriefDescription": "Marked DL1 Demand Miss counted at finish time."
141  },
142  {
143    "EventCode": "0x200F4",
144    "EventName": "PM_RUN_CYC",
145    "BriefDescription": "Processor cycles gated by the run latch."
146  },
147  {
148    "EventCode": "0x30008",
149    "EventName": "PM_EXEC_STALL",
150    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
151  },
152  {
153    "EventCode": "0x3001A",
154    "EventName": "PM_LSU_ST2_FIN",
155    "BriefDescription": "LSU Finished an internal operation in ST2 port."
156  },
157  {
158    "EventCode": "0x30020",
159    "EventName": "PM_PMC2_REWIND",
160    "BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
161  },
162  {
163    "EventCode": "0x30022",
164    "EventName": "PM_PMC4_SAVED",
165    "BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
166  },
167  {
168    "EventCode": "0x30024",
169    "EventName": "PM_PMC6_OVERFLOW",
170    "BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
171  },
172  {
173    "EventCode": "0x30028",
174    "EventName": "PM_CMPL_STALL_MEM_ECC",
175    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC."
176  },
177  {
178    "EventCode": "0x30036",
179    "EventName": "PM_EXEC_STALL_SIMPLE_FX",
180    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit."
181  },
182  {
183    "EventCode": "0x3003A",
184    "EventName": "PM_CMPL_STALL_EXCEPTION",
185    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete."
186  },
187  {
188    "EventCode": "0x3F044",
189    "EventName": "PM_VSU2_ISSUE",
190    "BriefDescription": "VSU instructions issued to VSU pipe 2."
191  },
192  {
193    "EventCode": "0x30058",
194    "EventName": "PM_TLBIE_FIN",
195    "BriefDescription": "TLBIE instructions finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
196  },
197  {
198    "EventCode": "0x3D058",
199    "EventName": "PM_SCALAR_FSQRT_FDIV_ISSUE",
200    "BriefDescription": "Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)."
201  },
202  {
203    "EventCode": "0x30066",
204    "EventName": "PM_LSU_FIN",
205    "BriefDescription": "LSU Finished an internal operation (up to 4 per cycle)."
206  },
207  {
208    "EventCode": "0x40004",
209    "EventName": "PM_FXU_ISSUE",
210    "BriefDescription": "A fixed point instruction was issued to the VSU."
211  },
212  {
213    "EventCode": "0x40008",
214    "EventName": "PM_NTC_ALL_FIN",
215    "BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
216  },
217  {
218    "EventCode": "0x40010",
219    "EventName": "PM_PMC3_OVERFLOW",
220    "BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
221  },
222  {
223    "EventCode": "0x4C012",
224    "EventName": "PM_EXEC_STALL_DERAT_ONLY_MISS",
225    "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve."
226  },
227  {
228    "EventCode": "0x4C018",
229    "EventName": "PM_CMPL_STALL",
230    "BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason."
231  },
232  {
233    "EventCode": "0x4C01E",
234    "EventName": "PM_LSU_ST3_FIN",
235    "BriefDescription": "LSU Finished an internal operation in ST3 port."
236  },
237  {
238    "EventCode": "0x4D018",
239    "EventName": "PM_EXEC_STALL_BRU",
240    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Branch unit."
241  },
242  {
243    "EventCode": "0x4D01A",
244    "EventName": "PM_CMPL_STALL_HWSYNC",
245    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing."
246  },
247  {
248    "EventCode": "0x4D01C",
249    "EventName": "PM_EXEC_STALL_TLBIEL",
250    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
251  },
252  {
253    "EventCode": "0x4E012",
254    "EventName": "PM_EXEC_STALL_UNKNOWN",
255    "BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the NTF finishes and completions came too close together."
256  },
257  {
258    "EventCode": "0x4D020",
259    "EventName": "PM_VSU3_ISSUE",
260    "BriefDescription": "VSU instruction was issued to VSU pipe 3."
261  },
262  {
263    "EventCode": "0x40132",
264    "EventName": "PM_MRK_LSU_FIN",
265    "BriefDescription": "LSU marked instruction finish."
266  },
267  {
268    "EventCode": "0x45058",
269    "EventName": "PM_IC_MISS_CMPL",
270    "BriefDescription": "Non-speculative icache miss, counted at completion."
271  },
272  {
273    "EventCode": "0x4D050",
274    "EventName": "PM_VSU_NON_FLOP_CMPL",
275    "BriefDescription": "Non-floating point VSU instructions completed."
276  },
277  {
278    "EventCode": "0x4D052",
279    "EventName": "PM_2FLOP_CMPL",
280    "BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
281  },
282  {
283    "EventCode": "0x400F2",
284    "EventName": "PM_1PLUS_PPC_DISP",
285    "BriefDescription": "Cycles at least one Instr Dispatched."
286  },
287  {
288    "EventCode": "0x400F8",
289    "EventName": "PM_FLUSH",
290    "BriefDescription": "Flush (any type)."
291  }
292]
293