1[
2  {
3    "EventCode": "0x10016",
4    "EventName": "PM_VSU0_ISSUE",
5    "BriefDescription": "VSU instruction issued to VSU pipe 0."
6  },
7  {
8    "EventCode": "0x1001C",
9    "EventName": "PM_ULTRAVISOR_INST_CMPL",
10    "BriefDescription": "PowerPC instruction completed while the thread was in ultravisor state."
11  },
12  {
13    "EventCode": "0x100F0",
14    "EventName": "PM_CYC",
15    "BriefDescription": "Processor cycles."
16  },
17  {
18    "EventCode": "0x10134",
19    "EventName": "PM_MRK_ST_DONE_L2",
20    "BriefDescription": "Marked store completed in L2."
21  },
22  {
23    "EventCode": "0x1505E",
24    "EventName": "PM_LD_HIT_L1",
25    "BriefDescription": "Load finished without experiencing an L1 miss."
26  },
27  {
28    "EventCode": "0x1F056",
29    "EventName": "PM_DISP_SS0_2_INSTR_CYC",
30    "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
31  },
32  {
33    "EventCode": "0x10066",
34    "EventName": "PM_ADJUNCT_CYC",
35    "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
36  },
37  {
38    "EventCode": "0x101E4",
39    "EventName": "PM_MRK_L1_ICACHE_MISS",
40    "BriefDescription": "Marked instruction suffered an instruction cache miss."
41  },
42  {
43    "EventCode": "0x101EA",
44    "EventName": "PM_MRK_L1_RELOAD_VALID",
45    "BriefDescription": "Marked demand reload."
46  },
47  {
48    "EventCode": "0x100F4",
49    "EventName": "PM_FLOP_CMPL",
50    "BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
51  },
52  {
53    "EventCode": "0x100FA",
54    "EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
55    "BriefDescription": "Cycles when at least one thread has the run latch set."
56  },
57  {
58    "EventCode": "0x100FC",
59    "EventName": "PM_LD_REF_L1",
60    "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
61  },
62  {
63    "EventCode": "0x2000C",
64    "EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
65    "BriefDescription": "Cycles when the run latch is set for all threads."
66  },
67  {
68    "EventCode": "0x2E010",
69    "EventName": "PM_ADJUNCT_INST_CMPL",
70    "BriefDescription": "PowerPC instruction completed while the thread was in Adjunct state."
71  },
72  {
73    "EventCode": "0x2E014",
74    "EventName": "PM_STCX_FIN",
75    "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
76  },
77  {
78    "EventCode": "0x20130",
79    "EventName": "PM_MRK_INST_DECODED",
80    "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
81  },
82  {
83    "EventCode": "0x20132",
84    "EventName": "PM_MRK_DFU_ISSUE",
85    "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
86  },
87  {
88    "EventCode": "0x20134",
89    "EventName": "PM_MRK_FXU_ISSUE",
90    "BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
91  },
92  {
93    "EventCode": "0x2505C",
94    "EventName": "PM_VSU_ISSUE",
95    "BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
96  },
97  {
98    "EventCode": "0x2F054",
99    "EventName": "PM_DISP_SS1_2_INSTR_CYC",
100    "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."
101  },
102  {
103    "EventCode": "0x2F056",
104    "EventName": "PM_DISP_SS1_4_INSTR_CYC",
105    "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
106  },
107  {
108    "EventCode": "0x2006C",
109    "EventName": "PM_RUN_CYC_SMT4_MODE",
110    "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
111  },
112  {
113    "EventCode": "0x201E0",
114    "EventName": "PM_MRK_DATA_FROM_MEMORY",
115    "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
116  },
117  {
118    "EventCode": "0x201E4",
119    "EventName": "PM_MRK_DATA_FROM_L3MISS",
120    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
121  },
122  {
123    "EventCode": "0x201E8",
124    "EventName": "PM_THRESH_EXC_512",
125    "BriefDescription": "Threshold counter exceeded a value of 512."
126  },
127  {
128    "EventCode": "0x200F2",
129    "EventName": "PM_INST_DISP",
130    "BriefDescription": "PowerPC instruction dispatched."
131  },
132  {
133    "EventCode": "0x30132",
134    "EventName": "PM_MRK_VSU_FIN",
135    "BriefDescription": "VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit."
136  },
137  {
138    "EventCode": "0x30038",
139    "EventName": "PM_EXEC_STALL_DMISS_LMEM",
140    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCAPI cache, or local OpenCAPI memory."
141  },
142  {
143    "EventCode": "0x3F04A",
144    "EventName": "PM_LSU_ST5_FIN",
145    "BriefDescription": "LSU Finished an internal operation in ST2 port."
146  },
147  {
148    "EventCode": "0x3405A",
149    "EventName": "PM_PRIVILEGED_INST_CMPL",
150    "BriefDescription": "PowerPC instruction completed while the thread was in Privileged state."
151  },
152  {
153    "EventCode": "0x3F150",
154    "EventName": "PM_MRK_ST_DRAIN_CYC",
155    "BriefDescription": "Cycles in which the marked store drained from the core to the L2."
156  },
157  {
158    "EventCode": "0x3F054",
159    "EventName": "PM_DISP_SS0_4_INSTR_CYC",
160    "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."
161  },
162  {
163    "EventCode": "0x3F056",
164    "EventName": "PM_DISP_SS0_8_INSTR_CYC",
165    "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
166  },
167  {
168    "EventCode": "0x30162",
169    "EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
170    "BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
171  },
172  {
173    "EventCode": "0x40114",
174    "EventName": "PM_MRK_START_PROBE_NOP_DISP",
175    "BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
176  },
177  {
178    "EventCode": "0x4001C",
179    "EventName": "PM_VSU_FIN",
180    "BriefDescription": "VSU instruction finished."
181  },
182  {
183    "EventCode": "0x4C01A",
184    "EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
185    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
186  },
187  {
188    "EventCode": "0x4D012",
189    "EventName": "PM_PMC3_SAVED",
190    "BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
191  },
192  {
193    "EventCode": "0x4D022",
194    "EventName": "PM_HYPERVISOR_INST_CMPL",
195    "BriefDescription": "PowerPC instruction completed while the thread was in hypervisor state."
196  },
197  {
198    "EventCode": "0x4D026",
199    "EventName": "PM_ULTRAVISOR_CYC",
200    "BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
201  },
202  {
203    "EventCode": "0x4D028",
204    "EventName": "PM_PRIVILEGED_CYC",
205    "BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
206  },
207  {
208    "EventCode": "0x40030",
209    "EventName": "PM_INST_FIN",
210    "BriefDescription": "Instruction finished."
211  },
212  {
213    "EventCode": "0x44146",
214    "EventName": "PM_MRK_STCX_CORE_CYC",
215    "BriefDescription": "Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
216  },
217  {
218    "EventCode": "0x44054",
219    "EventName": "PM_VECTOR_LD_CMPL",
220    "BriefDescription": "Vector load instruction completed."
221  },
222  {
223    "EventCode": "0x45054",
224    "EventName": "PM_FMA_CMPL",
225    "BriefDescription": "Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
226  },
227  {
228    "EventCode": "0x45056",
229    "EventName": "PM_SCALAR_FLOP_CMPL",
230    "BriefDescription": "Scalar floating point instruction completed."
231  },
232  {
233    "EventCode": "0x4505C",
234    "EventName": "PM_MATH_FLOP_CMPL",
235    "BriefDescription": "Math floating point instruction completed."
236  },
237  {
238    "EventCode": "0x4D05E",
239    "EventName": "PM_BR_CMPL",
240    "BriefDescription": "A branch completed. All branches are included."
241  },
242  {
243    "EventCode": "0x4E15E",
244    "EventName": "PM_MRK_INST_FLUSHED",
245    "BriefDescription": "The marked instruction was flushed."
246  },
247  {
248    "EventCode": "0x401E6",
249    "EventName": "PM_MRK_INST_FROM_L3MISS",
250    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
251  },
252  {
253    "EventCode": "0x401E8",
254    "EventName": "PM_MRK_DATA_FROM_L2MISS",
255    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
256  },
257  {
258    "EventCode": "0x400F0",
259    "EventName": "PM_LD_DEMAND_MISS_L1_FIN",
260    "BriefDescription": "Load missed L1, counted at finish time."
261  },
262  {
263    "EventCode": "0x500FA",
264    "EventName": "PM_RUN_INST_CMPL",
265    "BriefDescription": "PowerPC instruction completed while the run latch is set."
266  }
267]
268