1[ 2 { 3 "EventCode": "0x1002C", 4 "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS", 5 "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request." 6 }, 7 { 8 "EventCode": "0x1505E", 9 "EventName": "PM_LD_HIT_L1", 10 "BriefDescription": "Load finished without experiencing an L1 miss." 11 }, 12 { 13 "EventCode": "0x1F056", 14 "EventName": "PM_DISP_SS0_2_INSTR_CYC", 15 "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions." 16 }, 17 { 18 "EventCode": "0x10066", 19 "EventName": "PM_ADJUNCT_CYC", 20 "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011." 21 }, 22 { 23 "EventCode": "0x100FC", 24 "EventName": "PM_LD_REF_L1", 25 "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included." 26 }, 27 { 28 "EventCode": "0x2E010", 29 "EventName": "PM_ADJUNCT_INST_CMPL", 30 "BriefDescription": "PowerPC instruction completed while the thread was in Adjunct state." 31 }, 32 { 33 "EventCode": "0x2E014", 34 "EventName": "PM_STCX_FIN", 35 "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock." 36 }, 37 { 38 "EventCode": "0x2F054", 39 "EventName": "PM_DISP_SS1_2_INSTR_CYC", 40 "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions." 41 }, 42 { 43 "EventCode": "0x2F056", 44 "EventName": "PM_DISP_SS1_4_INSTR_CYC", 45 "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions." 46 }, 47 { 48 "EventCode": "0x200F2", 49 "EventName": "PM_INST_DISP", 50 "BriefDescription": "PowerPC instruction dispatched." 51 }, 52 { 53 "EventCode": "0x200FD", 54 "EventName": "PM_L1_ICACHE_MISS", 55 "BriefDescription": "Demand instruction cache miss." 56 }, 57 { 58 "EventCode": "0x3F04A", 59 "EventName": "PM_LSU_ST5_FIN", 60 "BriefDescription": "LSU Finished an internal operation in ST2 port." 61 }, 62 { 63 "EventCode": "0x3405A", 64 "EventName": "PM_PRIVILEGED_INST_CMPL", 65 "BriefDescription": "PowerPC instruction completed while the thread was in Privileged state." 66 }, 67 { 68 "EventCode": "0x3F054", 69 "EventName": "PM_DISP_SS0_4_INSTR_CYC", 70 "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions." 71 }, 72 { 73 "EventCode": "0x3F056", 74 "EventName": "PM_DISP_SS0_8_INSTR_CYC", 75 "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions." 76 }, 77 { 78 "EventCode": "0x30068", 79 "EventName": "PM_L1_ICACHE_RELOADED_PREF", 80 "BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)." 81 }, 82 { 83 "EventCode": "0x300F6", 84 "EventName": "PM_LD_DEMAND_MISS_L1", 85 "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish." 86 }, 87 { 88 "EventCode": "0x300FE", 89 "EventName": "PM_DATA_FROM_L3MISS", 90 "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss." 91 }, 92 { 93 "EventCode": "0x40012", 94 "EventName": "PM_L1_ICACHE_RELOADED_ALL", 95 "BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch." 96 }, 97 { 98 "EventCode": "0x44054", 99 "EventName": "PM_VECTOR_LD_CMPL", 100 "BriefDescription": "Vector load instruction completed." 101 }, 102 { 103 "EventCode": "0x4D05E", 104 "EventName": "PM_BR_CMPL", 105 "BriefDescription": "A branch completed. All branches are included." 106 }, 107 { 108 "EventCode": "0x400F0", 109 "EventName": "PM_LD_DEMAND_MISS_L1_FIN", 110 "BriefDescription": "Load missed L1, counted at finish time." 111 }, 112 { 113 "EventCode": "0x400FE", 114 "EventName": "PM_DATA_FROM_MEMORY", 115 "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 116 } 117] 118