132daa5d7SKajol Jain[ 232daa5d7SKajol Jain { 3*7d473f47SKajol Jain "EventCode": "0x1002C", 4*7d473f47SKajol Jain "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS", 5*7d473f47SKajol Jain "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request." 632daa5d7SKajol Jain }, 732daa5d7SKajol Jain { 88fc4e4aaSKajol Jain "EventCode": "0x1505E", 932daa5d7SKajol Jain "EventName": "PM_LD_HIT_L1", 103286f88fSKajol Jain "BriefDescription": "Load finished without experiencing an L1 miss." 1132daa5d7SKajol Jain }, 1232daa5d7SKajol Jain { 138fc4e4aaSKajol Jain "EventCode": "0x1F056", 1432daa5d7SKajol Jain "EventName": "PM_DISP_SS0_2_INSTR_CYC", 1532daa5d7SKajol Jain "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions." 1632daa5d7SKajol Jain }, 1732daa5d7SKajol Jain { 188fc4e4aaSKajol Jain "EventCode": "0x10066", 1932daa5d7SKajol Jain "EventName": "PM_ADJUNCT_CYC", 2032daa5d7SKajol Jain "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011." 2132daa5d7SKajol Jain }, 2232daa5d7SKajol Jain { 238fc4e4aaSKajol Jain "EventCode": "0x100FC", 2432daa5d7SKajol Jain "EventName": "PM_LD_REF_L1", 2532daa5d7SKajol Jain "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included." 2632daa5d7SKajol Jain }, 2732daa5d7SKajol Jain { 288fc4e4aaSKajol Jain "EventCode": "0x2E010", 2932daa5d7SKajol Jain "EventName": "PM_ADJUNCT_INST_CMPL", 303286f88fSKajol Jain "BriefDescription": "PowerPC instruction completed while the thread was in Adjunct state." 3132daa5d7SKajol Jain }, 3232daa5d7SKajol Jain { 338fc4e4aaSKajol Jain "EventCode": "0x2E014", 3432daa5d7SKajol Jain "EventName": "PM_STCX_FIN", 3532daa5d7SKajol Jain "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock." 3632daa5d7SKajol Jain }, 3732daa5d7SKajol Jain { 388fc4e4aaSKajol Jain "EventCode": "0x2F054", 3932daa5d7SKajol Jain "EventName": "PM_DISP_SS1_2_INSTR_CYC", 4032daa5d7SKajol Jain "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions." 4132daa5d7SKajol Jain }, 4232daa5d7SKajol Jain { 438fc4e4aaSKajol Jain "EventCode": "0x2F056", 4432daa5d7SKajol Jain "EventName": "PM_DISP_SS1_4_INSTR_CYC", 4532daa5d7SKajol Jain "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions." 4632daa5d7SKajol Jain }, 4732daa5d7SKajol Jain { 488fc4e4aaSKajol Jain "EventCode": "0x200F2", 4932daa5d7SKajol Jain "EventName": "PM_INST_DISP", 503286f88fSKajol Jain "BriefDescription": "PowerPC instruction dispatched." 5132daa5d7SKajol Jain }, 5232daa5d7SKajol Jain { 53*7d473f47SKajol Jain "EventCode": "0x200FD", 54*7d473f47SKajol Jain "EventName": "PM_L1_ICACHE_MISS", 55*7d473f47SKajol Jain "BriefDescription": "Demand instruction cache miss." 5632daa5d7SKajol Jain }, 5732daa5d7SKajol Jain { 588fc4e4aaSKajol Jain "EventCode": "0x3F04A", 5932daa5d7SKajol Jain "EventName": "PM_LSU_ST5_FIN", 6032daa5d7SKajol Jain "BriefDescription": "LSU Finished an internal operation in ST2 port." 6132daa5d7SKajol Jain }, 6232daa5d7SKajol Jain { 638fc4e4aaSKajol Jain "EventCode": "0x3405A", 6432daa5d7SKajol Jain "EventName": "PM_PRIVILEGED_INST_CMPL", 653286f88fSKajol Jain "BriefDescription": "PowerPC instruction completed while the thread was in Privileged state." 6632daa5d7SKajol Jain }, 6732daa5d7SKajol Jain { 688fc4e4aaSKajol Jain "EventCode": "0x3F054", 6932daa5d7SKajol Jain "EventName": "PM_DISP_SS0_4_INSTR_CYC", 7032daa5d7SKajol Jain "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions." 7132daa5d7SKajol Jain }, 7232daa5d7SKajol Jain { 738fc4e4aaSKajol Jain "EventCode": "0x3F056", 7432daa5d7SKajol Jain "EventName": "PM_DISP_SS0_8_INSTR_CYC", 7532daa5d7SKajol Jain "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions." 7632daa5d7SKajol Jain }, 7732daa5d7SKajol Jain { 78*7d473f47SKajol Jain "EventCode": "0x30068", 79*7d473f47SKajol Jain "EventName": "PM_L1_ICACHE_RELOADED_PREF", 80*7d473f47SKajol Jain "BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)." 8132daa5d7SKajol Jain }, 8232daa5d7SKajol Jain { 83*7d473f47SKajol Jain "EventCode": "0x300F6", 84*7d473f47SKajol Jain "EventName": "PM_LD_DEMAND_MISS_L1", 85*7d473f47SKajol Jain "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish." 8632daa5d7SKajol Jain }, 8732daa5d7SKajol Jain { 88*7d473f47SKajol Jain "EventCode": "0x300FE", 89*7d473f47SKajol Jain "EventName": "PM_DATA_FROM_L3MISS", 90*7d473f47SKajol Jain "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss." 9132daa5d7SKajol Jain }, 9232daa5d7SKajol Jain { 93*7d473f47SKajol Jain "EventCode": "0x40012", 94*7d473f47SKajol Jain "EventName": "PM_L1_ICACHE_RELOADED_ALL", 95*7d473f47SKajol Jain "BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch." 9632daa5d7SKajol Jain }, 9732daa5d7SKajol Jain { 988fc4e4aaSKajol Jain "EventCode": "0x44054", 9932daa5d7SKajol Jain "EventName": "PM_VECTOR_LD_CMPL", 1003286f88fSKajol Jain "BriefDescription": "Vector load instruction completed." 10132daa5d7SKajol Jain }, 10232daa5d7SKajol Jain { 1038fc4e4aaSKajol Jain "EventCode": "0x4D05E", 10432daa5d7SKajol Jain "EventName": "PM_BR_CMPL", 10532daa5d7SKajol Jain "BriefDescription": "A branch completed. All branches are included." 10632daa5d7SKajol Jain }, 10732daa5d7SKajol Jain { 1088fc4e4aaSKajol Jain "EventCode": "0x400F0", 10932daa5d7SKajol Jain "EventName": "PM_LD_DEMAND_MISS_L1_FIN", 1103286f88fSKajol Jain "BriefDescription": "Load missed L1, counted at finish time." 11132daa5d7SKajol Jain }, 11232daa5d7SKajol Jain { 113*7d473f47SKajol Jain "EventCode": "0x400FE", 114*7d473f47SKajol Jain "EventName": "PM_DATA_FROM_MEMORY", 115*7d473f47SKajol Jain "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 11632daa5d7SKajol Jain } 11732daa5d7SKajol Jain] 118