1[
2  {
3    "EventCode": "0x1000A",
4    "EventName": "PM_PMC3_REWIND",
5    "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
6  },
7  {
8    "EventCode": "0x1C040",
9    "EventName": "PM_XFER_FROM_SRC_PMC1",
10    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
11  },
12  {
13    "EventCode": "0x1C142",
14    "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
15    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
16  },
17  {
18    "EventCode": "0x1C144",
19    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
20    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
21  },
22  {
23    "EventCode": "0x1C056",
24    "EventName": "PM_DERAT_MISS_4K",
25    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
26  },
27  {
28    "EventCode": "0x1C058",
29    "EventName": "PM_DTLB_MISS_16G",
30    "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
31  },
32  {
33    "EventCode": "0x1C05C",
34    "EventName": "PM_DTLB_MISS_2M",
35    "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
36  },
37  {
38    "EventCode": "0x1E056",
39    "EventName": "PM_EXEC_STALL_STORE_PIPE",
40    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
41  },
42  {
43    "EventCode": "0x1F150",
44    "EventName": "PM_MRK_ST_L2_CYC",
45    "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
46  },
47  {
48    "EventCode": "0x10062",
49    "EventName": "PM_LD_L3MISS_PEND_CYC",
50    "BriefDescription": "Cycles L3 miss was pending for this thread."
51  },
52  {
53    "EventCode": "0x20010",
54    "EventName": "PM_PMC1_OVERFLOW",
55    "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
56  },
57  {
58    "EventCode": "0x2001A",
59    "EventName": "PM_ITLB_HIT",
60    "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
61  },
62  {
63    "EventCode": "0x2003E",
64    "EventName": "PM_PTESYNC_FIN",
65    "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
66  },
67  {
68    "EventCode": "0x2C040",
69    "EventName": "PM_XFER_FROM_SRC_PMC2",
70    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
71  },
72  {
73    "EventCode": "0x2C054",
74    "EventName": "PM_DERAT_MISS_64K",
75    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
76  },
77  {
78    "EventCode": "0x2C056",
79    "EventName": "PM_DTLB_MISS_4K",
80    "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
81  },
82  {
83    "EventCode": "0x2D154",
84    "EventName": "PM_MRK_DERAT_MISS_64K",
85    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
86  },
87  {
88    "EventCode": "0x200F6",
89    "EventName": "PM_DERAT_MISS",
90    "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
91  },
92  {
93    "EventCode": "0x30016",
94    "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
95    "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
96  },
97  {
98    "EventCode": "0x3C040",
99    "EventName": "PM_XFER_FROM_SRC_PMC3",
100    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
101  },
102  {
103    "EventCode": "0x3C142",
104    "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
105    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
106  },
107  {
108    "EventCode": "0x3C144",
109    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
110    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
111  },
112  {
113    "EventCode": "0x3C054",
114    "EventName": "PM_DERAT_MISS_16M",
115    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
116  },
117  {
118    "EventCode": "0x3C056",
119    "EventName": "PM_DTLB_MISS_64K",
120    "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
121  },
122  {
123    "EventCode": "0x3C058",
124    "EventName": "PM_LARX_FIN",
125    "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
126  },
127  {
128    "EventCode": "0x301E2",
129    "EventName": "PM_MRK_ST_CMPL",
130    "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
131  },
132  {
133    "EventCode": "0x300FC",
134    "EventName": "PM_DTLB_MISS",
135    "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity."
136  },
137  {
138    "EventCode": "0x4D02C",
139    "EventName": "PM_PMC1_REWIND",
140    "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
141  },
142  {
143    "EventCode": "0x4003E",
144    "EventName": "PM_LD_CMPL",
145    "BriefDescription": "Loads completed."
146  },
147  {
148    "EventCode": "0x4C040",
149    "EventName": "PM_XFER_FROM_SRC_PMC4",
150    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
151  },
152  {
153    "EventCode": "0x4C142",
154    "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
155    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
156  },
157  {
158    "EventCode": "0x4C144",
159    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
160    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
161  },
162  {
163    "EventCode": "0x4C056",
164    "EventName": "PM_DTLB_MISS_16M",
165    "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
166  },
167  {
168    "EventCode": "0x4C05A",
169    "EventName": "PM_DTLB_MISS_1G",
170    "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
171  },
172  {
173    "EventCode": "0x4C15E",
174    "EventName": "PM_MRK_DTLB_MISS_64K",
175    "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
176  },
177  {
178    "EventCode": "0x4D056",
179    "EventName": "PM_NON_FMA_FLOP_CMPL",
180    "BriefDescription": "Non FMA instruction completed."
181  },
182  {
183    "EventCode": "0x40164",
184    "EventName": "PM_MRK_DERAT_MISS_2M",
185    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
186  }
187]
188