132daa5d7SKajol Jain[ 232daa5d7SKajol Jain { 3*8fc4e4aaSKajol Jain "EventCode": "0x1000A", 432daa5d7SKajol Jain "EventName": "PM_PMC3_REWIND", 532daa5d7SKajol Jain "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged." 632daa5d7SKajol Jain }, 732daa5d7SKajol Jain { 8*8fc4e4aaSKajol Jain "EventCode": "0x1C040", 932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC1", 1032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 1132daa5d7SKajol Jain }, 1232daa5d7SKajol Jain { 13*8fc4e4aaSKajol Jain "EventCode": "0x1C142", 1432daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_PMC1", 1532daa5d7SKajol Jain "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 1632daa5d7SKajol Jain }, 1732daa5d7SKajol Jain { 18*8fc4e4aaSKajol Jain "EventCode": "0x1C144", 1932daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1", 2032daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]." 2132daa5d7SKajol Jain }, 2232daa5d7SKajol Jain { 23*8fc4e4aaSKajol Jain "EventCode": "0x1C056", 2432daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_4K", 2532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 2632daa5d7SKajol Jain }, 2732daa5d7SKajol Jain { 28*8fc4e4aaSKajol Jain "EventCode": "0x1C058", 2932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_16G", 3032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 3132daa5d7SKajol Jain }, 3232daa5d7SKajol Jain { 33*8fc4e4aaSKajol Jain "EventCode": "0x1C05C", 3432daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_2M", 3532daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 3632daa5d7SKajol Jain }, 3732daa5d7SKajol Jain { 38*8fc4e4aaSKajol Jain "EventCode": "0x1E056", 3932daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_STORE_PIPE", 4032daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions." 4132daa5d7SKajol Jain }, 4232daa5d7SKajol Jain { 43*8fc4e4aaSKajol Jain "EventCode": "0x1F150", 4432daa5d7SKajol Jain "EventName": "PM_MRK_ST_L2_CYC", 4532daa5d7SKajol Jain "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion." 4632daa5d7SKajol Jain }, 4732daa5d7SKajol Jain { 48*8fc4e4aaSKajol Jain "EventCode": "0x10062", 4932daa5d7SKajol Jain "EventName": "PM_LD_L3MISS_PEND_CYC", 5032daa5d7SKajol Jain "BriefDescription": "Cycles L3 miss was pending for this thread." 5132daa5d7SKajol Jain }, 5232daa5d7SKajol Jain { 53*8fc4e4aaSKajol Jain "EventCode": "0x20010", 5432daa5d7SKajol Jain "EventName": "PM_PMC1_OVERFLOW", 5532daa5d7SKajol Jain "BriefDescription": "The event selected for PMC1 caused the event counter to overflow." 5632daa5d7SKajol Jain }, 5732daa5d7SKajol Jain { 58*8fc4e4aaSKajol Jain "EventCode": "0x2001A", 5932daa5d7SKajol Jain "EventName": "PM_ITLB_HIT", 6032daa5d7SKajol Jain "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches." 6132daa5d7SKajol Jain }, 6232daa5d7SKajol Jain { 63*8fc4e4aaSKajol Jain "EventCode": "0x2003E", 6432daa5d7SKajol Jain "EventName": "PM_PTESYNC_FIN", 6532daa5d7SKajol Jain "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time." 6632daa5d7SKajol Jain }, 6732daa5d7SKajol Jain { 68*8fc4e4aaSKajol Jain "EventCode": "0x2C040", 6932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC2", 7032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 7132daa5d7SKajol Jain }, 7232daa5d7SKajol Jain { 73*8fc4e4aaSKajol Jain "EventCode": "0x2C054", 7432daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_64K", 7532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 7632daa5d7SKajol Jain }, 7732daa5d7SKajol Jain { 78*8fc4e4aaSKajol Jain "EventCode": "0x2C056", 7932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_4K", 8032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 8132daa5d7SKajol Jain }, 8232daa5d7SKajol Jain { 83*8fc4e4aaSKajol Jain "EventCode": "0x2D154", 8432daa5d7SKajol Jain "EventName": "PM_MRK_DERAT_MISS_64K", 8532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 8632daa5d7SKajol Jain }, 8732daa5d7SKajol Jain { 88*8fc4e4aaSKajol Jain "EventCode": "0x200F6", 8932daa5d7SKajol Jain "EventName": "PM_DERAT_MISS", 9032daa5d7SKajol Jain "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 9132daa5d7SKajol Jain }, 9232daa5d7SKajol Jain { 93*8fc4e4aaSKajol Jain "EventCode": "0x30016", 9432daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS", 9532daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve." 9632daa5d7SKajol Jain }, 9732daa5d7SKajol Jain { 98*8fc4e4aaSKajol Jain "EventCode": "0x3C040", 9932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC3", 10032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 10132daa5d7SKajol Jain }, 10232daa5d7SKajol Jain { 103*8fc4e4aaSKajol Jain "EventCode": "0x3C142", 10432daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_PMC3", 10532daa5d7SKajol Jain "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 10632daa5d7SKajol Jain }, 10732daa5d7SKajol Jain { 108*8fc4e4aaSKajol Jain "EventCode": "0x3C144", 10932daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3", 11032daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]." 11132daa5d7SKajol Jain }, 11232daa5d7SKajol Jain { 113*8fc4e4aaSKajol Jain "EventCode": "0x3C054", 11432daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_16M", 11532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 11632daa5d7SKajol Jain }, 11732daa5d7SKajol Jain { 118*8fc4e4aaSKajol Jain "EventCode": "0x3C056", 11932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_64K", 12032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 12132daa5d7SKajol Jain }, 12232daa5d7SKajol Jain { 123*8fc4e4aaSKajol Jain "EventCode": "0x3C058", 12432daa5d7SKajol Jain "EventName": "PM_LARX_FIN", 12532daa5d7SKajol Jain "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock." 12632daa5d7SKajol Jain }, 12732daa5d7SKajol Jain { 128*8fc4e4aaSKajol Jain "EventCode": "0x301E2", 12932daa5d7SKajol Jain "EventName": "PM_MRK_ST_CMPL", 13032daa5d7SKajol Jain "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores." 13132daa5d7SKajol Jain }, 13232daa5d7SKajol Jain { 133*8fc4e4aaSKajol Jain "EventCode": "0x300FC", 13432daa5d7SKajol Jain "EventName": "PM_DTLB_MISS", 13532daa5d7SKajol Jain "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity." 13632daa5d7SKajol Jain }, 13732daa5d7SKajol Jain { 138*8fc4e4aaSKajol Jain "EventCode": "0x4D02C", 13932daa5d7SKajol Jain "EventName": "PM_PMC1_REWIND", 14032daa5d7SKajol Jain "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged." 14132daa5d7SKajol Jain }, 14232daa5d7SKajol Jain { 143*8fc4e4aaSKajol Jain "EventCode": "0x4003E", 14432daa5d7SKajol Jain "EventName": "PM_LD_CMPL", 14532daa5d7SKajol Jain "BriefDescription": "Loads completed." 14632daa5d7SKajol Jain }, 14732daa5d7SKajol Jain { 148*8fc4e4aaSKajol Jain "EventCode": "0x4C040", 14932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC4", 15032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 15132daa5d7SKajol Jain }, 15232daa5d7SKajol Jain { 153*8fc4e4aaSKajol Jain "EventCode": "0x4C142", 15432daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_PMC4", 15532daa5d7SKajol Jain "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 15632daa5d7SKajol Jain }, 15732daa5d7SKajol Jain { 158*8fc4e4aaSKajol Jain "EventCode": "0x4C144", 15932daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4", 16032daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]." 16132daa5d7SKajol Jain }, 16232daa5d7SKajol Jain { 163*8fc4e4aaSKajol Jain "EventCode": "0x4C056", 16432daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_16M", 16532daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 16632daa5d7SKajol Jain }, 16732daa5d7SKajol Jain { 168*8fc4e4aaSKajol Jain "EventCode": "0x4C05A", 16932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_1G", 17032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 17132daa5d7SKajol Jain }, 17232daa5d7SKajol Jain { 173*8fc4e4aaSKajol Jain "EventCode": "0x4C15E", 17432daa5d7SKajol Jain "EventName": "PM_MRK_DTLB_MISS_64K", 17532daa5d7SKajol Jain "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 17632daa5d7SKajol Jain }, 17732daa5d7SKajol Jain { 178*8fc4e4aaSKajol Jain "EventCode": "0x4D056", 17932daa5d7SKajol Jain "EventName": "PM_NON_FMA_FLOP_CMPL", 18032daa5d7SKajol Jain "BriefDescription": "Non FMA instruction completed." 18132daa5d7SKajol Jain }, 18232daa5d7SKajol Jain { 183*8fc4e4aaSKajol Jain "EventCode": "0x40164", 18432daa5d7SKajol Jain "EventName": "PM_MRK_DERAT_MISS_2M", 18532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 18632daa5d7SKajol Jain } 18732daa5d7SKajol Jain] 188