1*32daa5d7SKajol Jain[ 2*32daa5d7SKajol Jain { 3*32daa5d7SKajol Jain "EventCode": "1000A", 4*32daa5d7SKajol Jain "EventName": "PM_PMC3_REWIND", 5*32daa5d7SKajol Jain "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged." 6*32daa5d7SKajol Jain }, 7*32daa5d7SKajol Jain { 8*32daa5d7SKajol Jain "EventCode": "1C040", 9*32daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC1", 10*32daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 11*32daa5d7SKajol Jain }, 12*32daa5d7SKajol Jain { 13*32daa5d7SKajol Jain "EventCode": "1C142", 14*32daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_PMC1", 15*32daa5d7SKajol Jain "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 16*32daa5d7SKajol Jain }, 17*32daa5d7SKajol Jain { 18*32daa5d7SKajol Jain "EventCode": "1C144", 19*32daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1", 20*32daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]." 21*32daa5d7SKajol Jain }, 22*32daa5d7SKajol Jain { 23*32daa5d7SKajol Jain "EventCode": "1C056", 24*32daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_4K", 25*32daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 26*32daa5d7SKajol Jain }, 27*32daa5d7SKajol Jain { 28*32daa5d7SKajol Jain "EventCode": "1C058", 29*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_16G", 30*32daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 31*32daa5d7SKajol Jain }, 32*32daa5d7SKajol Jain { 33*32daa5d7SKajol Jain "EventCode": "1C05C", 34*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_2M", 35*32daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 36*32daa5d7SKajol Jain }, 37*32daa5d7SKajol Jain { 38*32daa5d7SKajol Jain "EventCode": "1E056", 39*32daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_STORE_PIPE", 40*32daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions." 41*32daa5d7SKajol Jain }, 42*32daa5d7SKajol Jain { 43*32daa5d7SKajol Jain "EventCode": "1F150", 44*32daa5d7SKajol Jain "EventName": "PM_MRK_ST_L2_CYC", 45*32daa5d7SKajol Jain "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion." 46*32daa5d7SKajol Jain }, 47*32daa5d7SKajol Jain { 48*32daa5d7SKajol Jain "EventCode": "10062", 49*32daa5d7SKajol Jain "EventName": "PM_LD_L3MISS_PEND_CYC", 50*32daa5d7SKajol Jain "BriefDescription": "Cycles L3 miss was pending for this thread." 51*32daa5d7SKajol Jain }, 52*32daa5d7SKajol Jain { 53*32daa5d7SKajol Jain "EventCode": "20010", 54*32daa5d7SKajol Jain "EventName": "PM_PMC1_OVERFLOW", 55*32daa5d7SKajol Jain "BriefDescription": "The event selected for PMC1 caused the event counter to overflow." 56*32daa5d7SKajol Jain }, 57*32daa5d7SKajol Jain { 58*32daa5d7SKajol Jain "EventCode": "2001A", 59*32daa5d7SKajol Jain "EventName": "PM_ITLB_HIT", 60*32daa5d7SKajol Jain "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches." 61*32daa5d7SKajol Jain }, 62*32daa5d7SKajol Jain { 63*32daa5d7SKajol Jain "EventCode": "2003E", 64*32daa5d7SKajol Jain "EventName": "PM_PTESYNC_FIN", 65*32daa5d7SKajol Jain "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time." 66*32daa5d7SKajol Jain }, 67*32daa5d7SKajol Jain { 68*32daa5d7SKajol Jain "EventCode": "2C040", 69*32daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC2", 70*32daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 71*32daa5d7SKajol Jain }, 72*32daa5d7SKajol Jain { 73*32daa5d7SKajol Jain "EventCode": "2C054", 74*32daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_64K", 75*32daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 76*32daa5d7SKajol Jain }, 77*32daa5d7SKajol Jain { 78*32daa5d7SKajol Jain "EventCode": "2C056", 79*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_4K", 80*32daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 81*32daa5d7SKajol Jain }, 82*32daa5d7SKajol Jain { 83*32daa5d7SKajol Jain "EventCode": "2D154", 84*32daa5d7SKajol Jain "EventName": "PM_MRK_DERAT_MISS_64K", 85*32daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 86*32daa5d7SKajol Jain }, 87*32daa5d7SKajol Jain { 88*32daa5d7SKajol Jain "EventCode": "200F6", 89*32daa5d7SKajol Jain "EventName": "PM_DERAT_MISS", 90*32daa5d7SKajol Jain "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 91*32daa5d7SKajol Jain }, 92*32daa5d7SKajol Jain { 93*32daa5d7SKajol Jain "EventCode": "3000A", 94*32daa5d7SKajol Jain "EventName": "PM_DISP_STALL_ITLB_MISS", 95*32daa5d7SKajol Jain "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss." 96*32daa5d7SKajol Jain }, 97*32daa5d7SKajol Jain { 98*32daa5d7SKajol Jain "EventCode": "30016", 99*32daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS", 100*32daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve." 101*32daa5d7SKajol Jain }, 102*32daa5d7SKajol Jain { 103*32daa5d7SKajol Jain "EventCode": "3C040", 104*32daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC3", 105*32daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 106*32daa5d7SKajol Jain }, 107*32daa5d7SKajol Jain { 108*32daa5d7SKajol Jain "EventCode": "3C142", 109*32daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_PMC3", 110*32daa5d7SKajol Jain "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 111*32daa5d7SKajol Jain }, 112*32daa5d7SKajol Jain { 113*32daa5d7SKajol Jain "EventCode": "3C144", 114*32daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3", 115*32daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]." 116*32daa5d7SKajol Jain }, 117*32daa5d7SKajol Jain { 118*32daa5d7SKajol Jain "EventCode": "3C054", 119*32daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_16M", 120*32daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 121*32daa5d7SKajol Jain }, 122*32daa5d7SKajol Jain { 123*32daa5d7SKajol Jain "EventCode": "3C056", 124*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_64K", 125*32daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 126*32daa5d7SKajol Jain }, 127*32daa5d7SKajol Jain { 128*32daa5d7SKajol Jain "EventCode": "3C058", 129*32daa5d7SKajol Jain "EventName": "PM_LARX_FIN", 130*32daa5d7SKajol Jain "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock." 131*32daa5d7SKajol Jain }, 132*32daa5d7SKajol Jain { 133*32daa5d7SKajol Jain "EventCode": "301E2", 134*32daa5d7SKajol Jain "EventName": "PM_MRK_ST_CMPL", 135*32daa5d7SKajol Jain "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores." 136*32daa5d7SKajol Jain }, 137*32daa5d7SKajol Jain { 138*32daa5d7SKajol Jain "EventCode": "300FC", 139*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS", 140*32daa5d7SKajol Jain "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity." 141*32daa5d7SKajol Jain }, 142*32daa5d7SKajol Jain { 143*32daa5d7SKajol Jain "EventCode": "4D02C", 144*32daa5d7SKajol Jain "EventName": "PM_PMC1_REWIND", 145*32daa5d7SKajol Jain "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged." 146*32daa5d7SKajol Jain }, 147*32daa5d7SKajol Jain { 148*32daa5d7SKajol Jain "EventCode": "4003E", 149*32daa5d7SKajol Jain "EventName": "PM_LD_CMPL", 150*32daa5d7SKajol Jain "BriefDescription": "Loads completed." 151*32daa5d7SKajol Jain }, 152*32daa5d7SKajol Jain { 153*32daa5d7SKajol Jain "EventCode": "4C040", 154*32daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC4", 155*32daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 156*32daa5d7SKajol Jain }, 157*32daa5d7SKajol Jain { 158*32daa5d7SKajol Jain "EventCode": "4C142", 159*32daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_PMC4", 160*32daa5d7SKajol Jain "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 161*32daa5d7SKajol Jain }, 162*32daa5d7SKajol Jain { 163*32daa5d7SKajol Jain "EventCode": "4C144", 164*32daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4", 165*32daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]." 166*32daa5d7SKajol Jain }, 167*32daa5d7SKajol Jain { 168*32daa5d7SKajol Jain "EventCode": "4C056", 169*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_16M", 170*32daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 171*32daa5d7SKajol Jain }, 172*32daa5d7SKajol Jain { 173*32daa5d7SKajol Jain "EventCode": "4C05A", 174*32daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_1G", 175*32daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 176*32daa5d7SKajol Jain }, 177*32daa5d7SKajol Jain { 178*32daa5d7SKajol Jain "EventCode": "4C15E", 179*32daa5d7SKajol Jain "EventName": "PM_MRK_DTLB_MISS_64K", 180*32daa5d7SKajol Jain "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 181*32daa5d7SKajol Jain }, 182*32daa5d7SKajol Jain { 183*32daa5d7SKajol Jain "EventCode": "4D056", 184*32daa5d7SKajol Jain "EventName": "PM_NON_FMA_FLOP_CMPL", 185*32daa5d7SKajol Jain "BriefDescription": "Non FMA instruction completed." 186*32daa5d7SKajol Jain }, 187*32daa5d7SKajol Jain { 188*32daa5d7SKajol Jain "EventCode": "40164", 189*32daa5d7SKajol Jain "EventName": "PM_MRK_DERAT_MISS_2M", 190*32daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 191*32daa5d7SKajol Jain } 192*32daa5d7SKajol Jain] 193