132daa5d7SKajol Jain[ 232daa5d7SKajol Jain { 38fc4e4aaSKajol Jain "EventCode": "0x1002C", 432daa5d7SKajol Jain "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS", 532daa5d7SKajol Jain "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request." 632daa5d7SKajol Jain }, 732daa5d7SKajol Jain { 88fc4e4aaSKajol Jain "EventCode": "0x10132", 932daa5d7SKajol Jain "EventName": "PM_MRK_INST_ISSUED", 1032daa5d7SKajol Jain "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction." 1132daa5d7SKajol Jain }, 1232daa5d7SKajol Jain { 138fc4e4aaSKajol Jain "EventCode": "0x101E0", 1432daa5d7SKajol Jain "EventName": "PM_MRK_INST_DISP", 1532daa5d7SKajol Jain "BriefDescription": "The thread has dispatched a randomly sampled marked instruction." 1632daa5d7SKajol Jain }, 1732daa5d7SKajol Jain { 188fc4e4aaSKajol Jain "EventCode": "0x101E2", 1932daa5d7SKajol Jain "EventName": "PM_MRK_BR_TAKEN_CMPL", 2032daa5d7SKajol Jain "BriefDescription": "Marked Branch Taken instruction completed." 2132daa5d7SKajol Jain }, 2232daa5d7SKajol Jain { 238fc4e4aaSKajol Jain "EventCode": "0x20112", 2432daa5d7SKajol Jain "EventName": "PM_MRK_NTF_FIN", 2532daa5d7SKajol Jain "BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch." 2632daa5d7SKajol Jain }, 2732daa5d7SKajol Jain { 288fc4e4aaSKajol Jain "EventCode": "0x2C01C", 2932daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP", 3032daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip." 3132daa5d7SKajol Jain }, 3232daa5d7SKajol Jain { 338fc4e4aaSKajol Jain "EventCode": "0x20138", 3432daa5d7SKajol Jain "EventName": "PM_MRK_ST_NEST", 3532daa5d7SKajol Jain "BriefDescription": "A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2." 3632daa5d7SKajol Jain }, 3732daa5d7SKajol Jain { 388fc4e4aaSKajol Jain "EventCode": "0x2013A", 3932daa5d7SKajol Jain "EventName": "PM_MRK_BRU_FIN", 4032daa5d7SKajol Jain "BriefDescription": "Marked Branch instruction finished." 4132daa5d7SKajol Jain }, 4232daa5d7SKajol Jain { 438fc4e4aaSKajol Jain "EventCode": "0x2C144", 4432daa5d7SKajol Jain "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2", 4532daa5d7SKajol Jain "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]." 4632daa5d7SKajol Jain }, 4732daa5d7SKajol Jain { 488fc4e4aaSKajol Jain "EventCode": "0x24156", 4932daa5d7SKajol Jain "EventName": "PM_MRK_STCX_FIN", 5032daa5d7SKajol Jain "BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock." 5132daa5d7SKajol Jain }, 5232daa5d7SKajol Jain { 538fc4e4aaSKajol Jain "EventCode": "0x24158", 5432daa5d7SKajol Jain "EventName": "PM_MRK_INST", 5532daa5d7SKajol Jain "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens." 5632daa5d7SKajol Jain }, 5732daa5d7SKajol Jain { 588fc4e4aaSKajol Jain "EventCode": "0x2415C", 5932daa5d7SKajol Jain "EventName": "PM_MRK_BR_CMPL", 6032daa5d7SKajol Jain "BriefDescription": "A marked branch completed. All branches are included." 6132daa5d7SKajol Jain }, 6232daa5d7SKajol Jain { 638fc4e4aaSKajol Jain "EventCode": "0x200FD", 6432daa5d7SKajol Jain "EventName": "PM_L1_ICACHE_MISS", 65*3286f88fSKajol Jain "BriefDescription": "Demand instruction cache miss." 6632daa5d7SKajol Jain }, 6732daa5d7SKajol Jain { 688fc4e4aaSKajol Jain "EventCode": "0x30130", 6932daa5d7SKajol Jain "EventName": "PM_MRK_INST_FIN", 7032daa5d7SKajol Jain "BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU." 7132daa5d7SKajol Jain }, 7232daa5d7SKajol Jain { 738fc4e4aaSKajol Jain "EventCode": "0x34146", 7432daa5d7SKajol Jain "EventName": "PM_MRK_LD_CMPL", 75*3286f88fSKajol Jain "BriefDescription": "Marked load instruction completed." 7632daa5d7SKajol Jain }, 7732daa5d7SKajol Jain { 788fc4e4aaSKajol Jain "EventCode": "0x3E158", 7932daa5d7SKajol Jain "EventName": "PM_MRK_STCX_FAIL", 8032daa5d7SKajol Jain "BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock." 8132daa5d7SKajol Jain }, 8232daa5d7SKajol Jain { 838fc4e4aaSKajol Jain "EventCode": "0x3E15A", 8432daa5d7SKajol Jain "EventName": "PM_MRK_ST_FIN", 85*3286f88fSKajol Jain "BriefDescription": "Marked store instruction finished." 8632daa5d7SKajol Jain }, 8732daa5d7SKajol Jain { 888fc4e4aaSKajol Jain "EventCode": "0x30068", 8932daa5d7SKajol Jain "EventName": "PM_L1_ICACHE_RELOADED_PREF", 90*3286f88fSKajol Jain "BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)." 9132daa5d7SKajol Jain }, 9232daa5d7SKajol Jain { 938fc4e4aaSKajol Jain "EventCode": "0x301E4", 9432daa5d7SKajol Jain "EventName": "PM_MRK_BR_MPRED_CMPL", 9532daa5d7SKajol Jain "BriefDescription": "Marked Branch Mispredicted. Includes direction and target." 9632daa5d7SKajol Jain }, 9732daa5d7SKajol Jain { 988fc4e4aaSKajol Jain "EventCode": "0x300F6", 9932daa5d7SKajol Jain "EventName": "PM_LD_DEMAND_MISS_L1", 10032daa5d7SKajol Jain "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish." 10132daa5d7SKajol Jain }, 10232daa5d7SKajol Jain { 1038fc4e4aaSKajol Jain "EventCode": "0x300FE", 10432daa5d7SKajol Jain "EventName": "PM_DATA_FROM_L3MISS", 105*3286f88fSKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss." 10632daa5d7SKajol Jain }, 10732daa5d7SKajol Jain { 1088fc4e4aaSKajol Jain "EventCode": "0x40012", 10932daa5d7SKajol Jain "EventName": "PM_L1_ICACHE_RELOADED_ALL", 110*3286f88fSKajol Jain "BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch." 11132daa5d7SKajol Jain }, 11232daa5d7SKajol Jain { 1138fc4e4aaSKajol Jain "EventCode": "0x40134", 11432daa5d7SKajol Jain "EventName": "PM_MRK_INST_TIMEO", 11532daa5d7SKajol Jain "BriefDescription": "Marked instruction finish timeout (instruction was lost)." 11632daa5d7SKajol Jain }, 11732daa5d7SKajol Jain { 1188fc4e4aaSKajol Jain "EventCode": "0x4505A", 11932daa5d7SKajol Jain "EventName": "PM_SP_FLOP_CMPL", 120*3286f88fSKajol Jain "BriefDescription": "Single Precision floating point instruction completed." 12132daa5d7SKajol Jain }, 12232daa5d7SKajol Jain { 1238fc4e4aaSKajol Jain "EventCode": "0x4D058", 12432daa5d7SKajol Jain "EventName": "PM_VECTOR_FLOP_CMPL", 125*3286f88fSKajol Jain "BriefDescription": "Vector floating point instruction completed." 12632daa5d7SKajol Jain }, 12732daa5d7SKajol Jain { 1288fc4e4aaSKajol Jain "EventCode": "0x4D05A", 12932daa5d7SKajol Jain "EventName": "PM_NON_MATH_FLOP_CMPL", 130*3286f88fSKajol Jain "BriefDescription": "Non Math instruction completed." 13132daa5d7SKajol Jain }, 13232daa5d7SKajol Jain { 1338fc4e4aaSKajol Jain "EventCode": "0x401E0", 13432daa5d7SKajol Jain "EventName": "PM_MRK_INST_CMPL", 135*3286f88fSKajol Jain "BriefDescription": "Marked instruction completed." 13632daa5d7SKajol Jain }, 13732daa5d7SKajol Jain { 1388fc4e4aaSKajol Jain "EventCode": "0x400FE", 13932daa5d7SKajol Jain "EventName": "PM_DATA_FROM_MEMORY", 14032daa5d7SKajol Jain "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 14132daa5d7SKajol Jain } 14232daa5d7SKajol Jain] 143