132daa5d7SKajol Jain[ 232daa5d7SKajol Jain { 3*8fc4e4aaSKajol Jain "EventCode": "0x1003C", 432daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_DMISS_L2L3", 532daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3." 632daa5d7SKajol Jain }, 732daa5d7SKajol Jain { 8*8fc4e4aaSKajol Jain "EventCode": "0x1E054", 9*8fc4e4aaSKajol Jain "EventName": "PM_EXEC_STALL_DMISS_L21_L31", 10*8fc4e4aaSKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip." 1132daa5d7SKajol Jain }, 1232daa5d7SKajol Jain { 13*8fc4e4aaSKajol Jain "EventCode": "0x34054", 14*8fc4e4aaSKajol Jain "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT", 15*8fc4e4aaSKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict." 16*8fc4e4aaSKajol Jain }, 17*8fc4e4aaSKajol Jain { 18*8fc4e4aaSKajol Jain "EventCode": "0x34056", 19*8fc4e4aaSKajol Jain "EventName": "PM_EXEC_STALL_LOAD_FINISH", 20*8fc4e4aaSKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction." 21*8fc4e4aaSKajol Jain }, 22*8fc4e4aaSKajol Jain { 23*8fc4e4aaSKajol Jain "EventCode": "0x3006C", 2432daa5d7SKajol Jain "EventName": "PM_RUN_CYC_SMT2_MODE", 2532daa5d7SKajol Jain "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode." 2632daa5d7SKajol Jain }, 2732daa5d7SKajol Jain { 28*8fc4e4aaSKajol Jain "EventCode": "0x300F4", 2932daa5d7SKajol Jain "EventName": "PM_RUN_INST_CMPL_CONC", 3032daa5d7SKajol Jain "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set." 3132daa5d7SKajol Jain }, 3232daa5d7SKajol Jain { 33*8fc4e4aaSKajol Jain "EventCode": "0x4C016", 3432daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT", 3532daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict." 3632daa5d7SKajol Jain }, 3732daa5d7SKajol Jain { 38*8fc4e4aaSKajol Jain "EventCode": "0x4D014", 3932daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_LOAD", 4032daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit." 4132daa5d7SKajol Jain }, 4232daa5d7SKajol Jain { 43*8fc4e4aaSKajol Jain "EventCode": "0x4D016", 4432daa5d7SKajol Jain "EventName": "PM_EXEC_STALL_PTESYNC", 4532daa5d7SKajol Jain "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit." 4632daa5d7SKajol Jain }, 4732daa5d7SKajol Jain { 48*8fc4e4aaSKajol Jain "EventCode": "0x401EA", 4932daa5d7SKajol Jain "EventName": "PM_THRESH_EXC_128", 5032daa5d7SKajol Jain "BriefDescription": "Threshold counter exceeded a value of 128." 5132daa5d7SKajol Jain }, 5232daa5d7SKajol Jain { 53*8fc4e4aaSKajol Jain "EventCode": "0x400F6", 5432daa5d7SKajol Jain "EventName": "PM_BR_MPRED_CMPL", 5532daa5d7SKajol Jain "BriefDescription": "A mispredicted branch completed. Includes direction and target." 5632daa5d7SKajol Jain } 5732daa5d7SKajol Jain] 58