13d4caec1SJohn Garry[ 23d4caec1SJohn Garry { 33d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_RD", 43d4caec1SJohn Garry }, 53d4caec1SJohn Garry { 63d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_WR", 73d4caec1SJohn Garry }, 83d4caec1SJohn Garry { 93d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_REFILL_RD", 103d4caec1SJohn Garry }, 113d4caec1SJohn Garry { 123d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_REFILL_WR", 133d4caec1SJohn Garry }, 143d4caec1SJohn Garry { 153d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_WB_VICTIM", 163d4caec1SJohn Garry }, 173d4caec1SJohn Garry { 183d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_WB_CLEAN", 193d4caec1SJohn Garry }, 203d4caec1SJohn Garry { 213d4caec1SJohn Garry "ArchStdEvent": "L1D_CACHE_INVAL", 223d4caec1SJohn Garry }, 233d4caec1SJohn Garry { 243d4caec1SJohn Garry "ArchStdEvent": "L1D_TLB_REFILL_RD", 253d4caec1SJohn Garry }, 263d4caec1SJohn Garry { 273d4caec1SJohn Garry "ArchStdEvent": "L1D_TLB_REFILL_WR", 283d4caec1SJohn Garry }, 293d4caec1SJohn Garry { 303d4caec1SJohn Garry "ArchStdEvent": "L1D_TLB_RD", 313d4caec1SJohn Garry }, 323d4caec1SJohn Garry { 333d4caec1SJohn Garry "ArchStdEvent": "L1D_TLB_WR", 343d4caec1SJohn Garry }, 353d4caec1SJohn Garry { 363d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_RD", 373d4caec1SJohn Garry }, 383d4caec1SJohn Garry { 393d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_WR", 403d4caec1SJohn Garry }, 413d4caec1SJohn Garry { 423d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_REFILL_RD", 433d4caec1SJohn Garry }, 443d4caec1SJohn Garry { 453d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_REFILL_WR", 463d4caec1SJohn Garry }, 473d4caec1SJohn Garry { 483d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_WB_VICTIM", 493d4caec1SJohn Garry }, 503d4caec1SJohn Garry { 513d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_WB_CLEAN", 523d4caec1SJohn Garry }, 533d4caec1SJohn Garry { 543d4caec1SJohn Garry "ArchStdEvent": "L2D_CACHE_INVAL", 553d4caec1SJohn Garry }, 563d4caec1SJohn Garry { 573d4caec1SJohn Garry "PublicDescription": "Level 1 instruction cache prefetch access count", 583d4caec1SJohn Garry "EventCode": "0x102e", 593d4caec1SJohn Garry "EventName": "L1I_CACHE_PRF", 603d4caec1SJohn Garry "BriefDescription": "L1I cache prefetch access count", 613d4caec1SJohn Garry }, 623d4caec1SJohn Garry { 633d4caec1SJohn Garry "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", 643d4caec1SJohn Garry "EventCode": "0x102f", 653d4caec1SJohn Garry "EventName": "L1I_CACHE_PRF_REFILL", 663d4caec1SJohn Garry "BriefDescription": "L1I cache miss due to prefetch access count", 673d4caec1SJohn Garry }, 683d4caec1SJohn Garry { 693d4caec1SJohn Garry "PublicDescription": "Instruction queue is empty", 703d4caec1SJohn Garry "EventCode": "0x1043", 713d4caec1SJohn Garry "EventName": "IQ_IS_EMPTY", 723d4caec1SJohn Garry "BriefDescription": "Instruction queue is empty", 733d4caec1SJohn Garry }, 743d4caec1SJohn Garry { 753d4caec1SJohn Garry "PublicDescription": "Instruction fetch stall cycles", 763d4caec1SJohn Garry "EventCode": "0x1044", 773d4caec1SJohn Garry "EventName": "IF_IS_STALL", 783d4caec1SJohn Garry "BriefDescription": "Instruction fetch stall cycles", 793d4caec1SJohn Garry }, 803d4caec1SJohn Garry { 813d4caec1SJohn Garry "PublicDescription": "Instructions can receive, but not send", 823d4caec1SJohn Garry "EventCode": "0x2014", 833d4caec1SJohn Garry "EventName": "FETCH_BUBBLE", 843d4caec1SJohn Garry "BriefDescription": "Instructions can receive, but not send", 853d4caec1SJohn Garry }, 863d4caec1SJohn Garry { 873d4caec1SJohn Garry "PublicDescription": "Prefetch request from LSU", 883d4caec1SJohn Garry "EventCode": "0x6013", 893d4caec1SJohn Garry "EventName": "PRF_REQ", 903d4caec1SJohn Garry "BriefDescription": "Prefetch request from LSU", 913d4caec1SJohn Garry }, 923d4caec1SJohn Garry { 933d4caec1SJohn Garry "PublicDescription": "Hit on prefetched data", 943d4caec1SJohn Garry "EventCode": "0x6014", 953d4caec1SJohn Garry "EventName": "HIT_ON_PRF", 963d4caec1SJohn Garry "BriefDescription": "Hit on prefetched data", 973d4caec1SJohn Garry }, 983d4caec1SJohn Garry { 993d4caec1SJohn Garry "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", 1003d4caec1SJohn Garry "EventCode": "0x7001", 1013d4caec1SJohn Garry "EventName": "EXE_STALL_CYCLE", 1023d4caec1SJohn Garry "BriefDescription": "Cycles of that the number of issue ups are less than 4", 1033d4caec1SJohn Garry }, 1043d4caec1SJohn Garry { 1053d4caec1SJohn Garry "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", 1063d4caec1SJohn Garry "EventCode": "0x7004", 1073d4caec1SJohn Garry "EventName": "MEM_STALL_ANYLOAD", 1083d4caec1SJohn Garry "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", 1093d4caec1SJohn Garry }, 1103d4caec1SJohn Garry { 1113d4caec1SJohn Garry "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", 1123d4caec1SJohn Garry "EventCode": "0x7006", 1133d4caec1SJohn Garry "EventName": "MEM_STALL_L1MISS", 1143d4caec1SJohn Garry "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", 1153d4caec1SJohn Garry }, 1163d4caec1SJohn Garry { 1173d4caec1SJohn Garry "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", 1183d4caec1SJohn Garry "EventCode": "0x7007", 1193d4caec1SJohn Garry "EventName": "MEM_STALL_L2MISS", 1203d4caec1SJohn Garry "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", 1213d4caec1SJohn Garry }, 1223d4caec1SJohn Garry] 123