1[
2   {
3           "BriefDescription": "ddr cycles event",
4           "EventCode": "0x00",
5           "EventName": "imx8mm_ddr.cycles",
6           "Unit": "imx8_ddr",
7           "Compat": "i.MX8MM"
8   },
9   {
10           "BriefDescription": "ddr read-cycles event",
11           "EventCode": "0x2a",
12           "EventName": "imx8mm_ddr.read_cycles",
13           "Unit": "imx8_ddr",
14           "Compat": "i.MX8MM"
15   },
16   {
17           "BriefDescription": "ddr write-cycles event",
18           "EventCode": "0x2b",
19           "EventName": "imx8mm_ddr.write_cycles",
20           "Unit": "imx8_ddr",
21           "Compat": "i.MX8MM"
22   },
23   {
24           "BriefDescription": "ddr read event",
25           "EventCode": "0x35",
26           "EventName": "imx8mm_ddr.read",
27           "Unit": "imx8_ddr",
28           "Compat": "i.MX8MM"
29   },
30   {
31           "BriefDescription": "ddr write event",
32           "EventCode": "0x38",
33           "EventName": "imx8mm_ddr.write",
34           "Unit": "imx8_ddr",
35           "Compat": "i.MX8MM"
36   }
37]
38
39
40