1*44739490SJames Clark[ 2*44739490SJames Clark { 3*44739490SJames Clark "ArchStdEvent": "L3D_CACHE_ALLOCATE", 4*44739490SJames Clark "PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores." 5*44739490SJames Clark }, 6*44739490SJames Clark { 7*44739490SJames Clark "ArchStdEvent": "L3D_CACHE_REFILL", 8*44739490SJames Clark "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." 9*44739490SJames Clark }, 10*44739490SJames Clark { 11*44739490SJames Clark "ArchStdEvent": "L3D_CACHE", 12*44739490SJames Clark "PublicDescription": "Counts level 3 cache accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." 13*44739490SJames Clark }, 14*44739490SJames Clark { 15*44739490SJames Clark "ArchStdEvent": "L3D_CACHE_RD", 16*44739490SJames Clark "PublicDescription": "TBD" 17*44739490SJames Clark }, 18*44739490SJames Clark { 19*44739490SJames Clark "ArchStdEvent": "L3D_CACHE_LMISS_RD", 20*44739490SJames Clark "PublicDescription": "Counts any cache line refill into the level 3 cache from memory read operations that incurred additional latency." 21*44739490SJames Clark } 22*44739490SJames Clark] 23