1*612a5337SJames Clark[
2*612a5337SJames Clark    {
3*612a5337SJames Clark        "ArchStdEvent": "CPU_CYCLES"
4*612a5337SJames Clark    },
5*612a5337SJames Clark    {
6*612a5337SJames Clark        "ArchStdEvent": "BUS_ACCESS"
7*612a5337SJames Clark    },
8*612a5337SJames Clark    {
9*612a5337SJames Clark        "ArchStdEvent": "BUS_CYCLES"
10*612a5337SJames Clark    },
11*612a5337SJames Clark    {
12*612a5337SJames Clark        "ArchStdEvent": "BUS_ACCESS_RD"
13*612a5337SJames Clark    },
14*612a5337SJames Clark    {
15*612a5337SJames Clark        "ArchStdEvent": "BUS_ACCESS_WR"
16*612a5337SJames Clark    },
17*612a5337SJames Clark    {
18*612a5337SJames Clark        "ArchStdEvent": "CNT_CYCLES"
19*612a5337SJames Clark    }
20*612a5337SJames Clark]
21