1*fbb6b31aSNick Forrington[ 2*fbb6b31aSNick Forrington { 3*fbb6b31aSNick Forrington "ArchStdEvent": "STALL_FRONTEND" 4*fbb6b31aSNick Forrington }, 5*fbb6b31aSNick Forrington { 6*fbb6b31aSNick Forrington "ArchStdEvent": "STALL_BACKEND" 7*fbb6b31aSNick Forrington }, 8*fbb6b31aSNick Forrington { 9*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed", 10*fbb6b31aSNick Forrington "EventCode": "0xE1", 11*fbb6b31aSNick Forrington "EventName": "STALL_FRONTEND_CACHE", 12*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed" 13*fbb6b31aSNick Forrington }, 14*fbb6b31aSNick Forrington { 15*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed", 16*fbb6b31aSNick Forrington "EventCode": "0xE2", 17*fbb6b31aSNick Forrington "EventName": "STALL_FRONTEND_TLB", 18*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed" 19*fbb6b31aSNick Forrington }, 20*fbb6b31aSNick Forrington { 21*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed", 22*fbb6b31aSNick Forrington "EventCode": "0xE3", 23*fbb6b31aSNick Forrington "EventName": "STALL_FRONTEND_PDERR", 24*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed" 25*fbb6b31aSNick Forrington }, 26*fbb6b31aSNick Forrington { 27*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded", 28*fbb6b31aSNick Forrington "EventCode": "0xE4", 29*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_ILOCK", 30*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded" 31*fbb6b31aSNick Forrington }, 32*fbb6b31aSNick Forrington { 33*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded", 34*fbb6b31aSNick Forrington "EventCode": "0xE5", 35*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_ILOCK_AGU", 36*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded" 37*fbb6b31aSNick Forrington }, 38*fbb6b31aSNick Forrington { 39*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded", 40*fbb6b31aSNick Forrington "EventCode": "0xE6", 41*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_ILOCK_FPU", 42*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded" 43*fbb6b31aSNick Forrington }, 44*fbb6b31aSNick Forrington { 45*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load", 46*fbb6b31aSNick Forrington "EventCode": "0xE7", 47*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_LD", 48*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load" 49*fbb6b31aSNick Forrington }, 50*fbb6b31aSNick Forrington { 51*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store", 52*fbb6b31aSNick Forrington "EventCode": "0xE8", 53*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_ST", 54*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store" 55*fbb6b31aSNick Forrington }, 56*fbb6b31aSNick Forrington { 57*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)", 58*fbb6b31aSNick Forrington "EventCode": "0xE9", 59*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_LD_CACHE", 60*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)" 61*fbb6b31aSNick Forrington }, 62*fbb6b31aSNick Forrington { 63*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB", 64*fbb6b31aSNick Forrington "EventCode": "0xEA", 65*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_LD_TLB", 66*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB" 67*fbb6b31aSNick Forrington }, 68*fbb6b31aSNick Forrington { 69*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full", 70*fbb6b31aSNick Forrington "EventCode": "0xEB", 71*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_ST_STB", 72*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full" 73*fbb6b31aSNick Forrington }, 74*fbb6b31aSNick Forrington { 75*fbb6b31aSNick Forrington "PublicDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB", 76*fbb6b31aSNick Forrington "EventCode": "0xEC", 77*fbb6b31aSNick Forrington "EventName": "STALL_BACKEND_ST_TLB", 78*fbb6b31aSNick Forrington "BriefDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB" 79*fbb6b31aSNick Forrington } 80*fbb6b31aSNick Forrington] 81