1*3935c302SNick Forrington[
2*3935c302SNick Forrington    {
3*3935c302SNick Forrington        "ArchStdEvent": "MEM_ACCESS"
4*3935c302SNick Forrington    },
5*3935c302SNick Forrington    {
6*3935c302SNick Forrington        "ArchStdEvent": "REMOTE_ACCESS_RD"
7*3935c302SNick Forrington    },
8*3935c302SNick Forrington    {
9*3935c302SNick Forrington        "ArchStdEvent": "MEM_ACCESS_RD"
10*3935c302SNick Forrington    },
11*3935c302SNick Forrington    {
12*3935c302SNick Forrington        "ArchStdEvent": "MEM_ACCESS_WR"
13*3935c302SNick Forrington    },
14*3935c302SNick Forrington    {
15*3935c302SNick Forrington        "ArchStdEvent": "LDST_ALIGN_LAT"
16*3935c302SNick Forrington    },
17*3935c302SNick Forrington    {
18*3935c302SNick Forrington        "ArchStdEvent": "LD_ALIGN_LAT"
19*3935c302SNick Forrington    },
20*3935c302SNick Forrington    {
21*3935c302SNick Forrington        "ArchStdEvent": "ST_ALIGN_LAT"
22*3935c302SNick Forrington    },
23*3935c302SNick Forrington    {
24*3935c302SNick Forrington        "ArchStdEvent": "MEM_ACCESS_CHECKED"
25*3935c302SNick Forrington    },
26*3935c302SNick Forrington    {
27*3935c302SNick Forrington        "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
28*3935c302SNick Forrington    },
29*3935c302SNick Forrington    {
30*3935c302SNick Forrington        "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
31*3935c302SNick Forrington    }
32*3935c302SNick Forrington]
33