1*3935c302SNick Forrington[ 2*3935c302SNick Forrington { 3*3935c302SNick Forrington "ArchStdEvent": "LD_RETIRED" 4*3935c302SNick Forrington }, 5*3935c302SNick Forrington { 6*3935c302SNick Forrington "ArchStdEvent": "ST_RETIRED" 7*3935c302SNick Forrington }, 8*3935c302SNick Forrington { 9*3935c302SNick Forrington "ArchStdEvent": "INST_RETIRED" 10*3935c302SNick Forrington }, 11*3935c302SNick Forrington { 12*3935c302SNick Forrington "ArchStdEvent": "EXC_RETURN" 13*3935c302SNick Forrington }, 14*3935c302SNick Forrington { 15*3935c302SNick Forrington "ArchStdEvent": "CID_WRITE_RETIRED" 16*3935c302SNick Forrington }, 17*3935c302SNick Forrington { 18*3935c302SNick Forrington "ArchStdEvent": "PC_WRITE_RETIRED" 19*3935c302SNick Forrington }, 20*3935c302SNick Forrington { 21*3935c302SNick Forrington "ArchStdEvent": "BR_IMMED_RETIRED" 22*3935c302SNick Forrington }, 23*3935c302SNick Forrington { 24*3935c302SNick Forrington "ArchStdEvent": "BR_RETURN_RETIRED" 25*3935c302SNick Forrington }, 26*3935c302SNick Forrington { 27*3935c302SNick Forrington "ArchStdEvent": "INST_SPEC" 28*3935c302SNick Forrington }, 29*3935c302SNick Forrington { 30*3935c302SNick Forrington "ArchStdEvent": "TTBR_WRITE_RETIRED" 31*3935c302SNick Forrington }, 32*3935c302SNick Forrington { 33*3935c302SNick Forrington "ArchStdEvent": "BR_RETIRED" 34*3935c302SNick Forrington }, 35*3935c302SNick Forrington { 36*3935c302SNick Forrington "ArchStdEvent": "BR_MIS_PRED_RETIRED" 37*3935c302SNick Forrington }, 38*3935c302SNick Forrington { 39*3935c302SNick Forrington "ArchStdEvent": "OP_RETIRED" 40*3935c302SNick Forrington }, 41*3935c302SNick Forrington { 42*3935c302SNick Forrington "ArchStdEvent": "OP_SPEC" 43*3935c302SNick Forrington }, 44*3935c302SNick Forrington { 45*3935c302SNick Forrington "ArchStdEvent": "LD_SPEC" 46*3935c302SNick Forrington }, 47*3935c302SNick Forrington { 48*3935c302SNick Forrington "ArchStdEvent": "ST_SPEC" 49*3935c302SNick Forrington }, 50*3935c302SNick Forrington { 51*3935c302SNick Forrington "ArchStdEvent": "LDST_SPEC" 52*3935c302SNick Forrington }, 53*3935c302SNick Forrington { 54*3935c302SNick Forrington "ArchStdEvent": "DP_SPEC" 55*3935c302SNick Forrington }, 56*3935c302SNick Forrington { 57*3935c302SNick Forrington "ArchStdEvent": "ASE_SPEC" 58*3935c302SNick Forrington }, 59*3935c302SNick Forrington { 60*3935c302SNick Forrington "ArchStdEvent": "VFP_SPEC" 61*3935c302SNick Forrington }, 62*3935c302SNick Forrington { 63*3935c302SNick Forrington "ArchStdEvent": "PC_WRITE_SPEC" 64*3935c302SNick Forrington }, 65*3935c302SNick Forrington { 66*3935c302SNick Forrington "ArchStdEvent": "CRYPTO_SPEC" 67*3935c302SNick Forrington }, 68*3935c302SNick Forrington { 69*3935c302SNick Forrington "ArchStdEvent": "SVE_INST_RETIRED" 70*3935c302SNick Forrington }, 71*3935c302SNick Forrington { 72*3935c302SNick Forrington "ArchStdEvent": "SVE_INST_SPEC" 73*3935c302SNick Forrington }, 74*3935c302SNick Forrington { 75*3935c302SNick Forrington "ArchStdEvent": "FP_HP_SPEC" 76*3935c302SNick Forrington }, 77*3935c302SNick Forrington { 78*3935c302SNick Forrington "ArchStdEvent": "FP_SP_SPEC" 79*3935c302SNick Forrington }, 80*3935c302SNick Forrington { 81*3935c302SNick Forrington "ArchStdEvent": "FP_DP_SPEC" 82*3935c302SNick Forrington }, 83*3935c302SNick Forrington { 84*3935c302SNick Forrington "ArchStdEvent": "ASE_SVE_INT8_SPEC" 85*3935c302SNick Forrington }, 86*3935c302SNick Forrington { 87*3935c302SNick Forrington "ArchStdEvent": "ASE_SVE_INT16_SPEC" 88*3935c302SNick Forrington }, 89*3935c302SNick Forrington { 90*3935c302SNick Forrington "ArchStdEvent": "ASE_SVE_INT32_SPEC" 91*3935c302SNick Forrington }, 92*3935c302SNick Forrington { 93*3935c302SNick Forrington "ArchStdEvent": "ASE_SVE_INT64_SPEC" 94*3935c302SNick Forrington } 95*3935c302SNick Forrington] 96