1*ee240951SNick Forrington[
2*ee240951SNick Forrington    {
3*ee240951SNick Forrington        "ArchStdEvent": "L1I_CACHE_REFILL"
4*ee240951SNick Forrington    },
5*ee240951SNick Forrington    {
6*ee240951SNick Forrington        "ArchStdEvent": "L1I_TLB_REFILL"
7*ee240951SNick Forrington    },
8*ee240951SNick Forrington    {
9*ee240951SNick Forrington        "ArchStdEvent": "L1D_CACHE_REFILL"
10*ee240951SNick Forrington    },
11*ee240951SNick Forrington    {
12*ee240951SNick Forrington        "ArchStdEvent": "L1D_CACHE"
13*ee240951SNick Forrington    },
14*ee240951SNick Forrington    {
15*ee240951SNick Forrington        "ArchStdEvent": "L1D_TLB_REFILL"
16*ee240951SNick Forrington    },
17*ee240951SNick Forrington    {
18*ee240951SNick Forrington        "ArchStdEvent": "L1I_CACHE"
19*ee240951SNick Forrington    },
20*ee240951SNick Forrington    {
21*ee240951SNick Forrington        "ArchStdEvent": "L1D_CACHE_WB"
22*ee240951SNick Forrington    },
23*ee240951SNick Forrington    {
24*ee240951SNick Forrington        "ArchStdEvent": "L2D_CACHE"
25*ee240951SNick Forrington    },
26*ee240951SNick Forrington    {
27*ee240951SNick Forrington        "ArchStdEvent": "L2D_CACHE_REFILL"
28*ee240951SNick Forrington    },
29*ee240951SNick Forrington    {
30*ee240951SNick Forrington        "ArchStdEvent": "L2D_CACHE_WB"
31*ee240951SNick Forrington    }
32*ee240951SNick Forrington]
33