1[
2    {
3	"MetricExpr": "BR_MIS_PRED / BR_PRED",
4	"BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch",
5	"MetricGroup": "Branch Prediction",
6	"MetricName": "Misprediction"
7    },
8    {
9	"MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED",
10	"BriefDescription": "Branch predictor misprediction rate",
11	"MetricGroup": "Branch Prediction",
12	"MetricName": "Misprediction (retired)"
13    },
14    {
15	"MetricExpr": "BUS_ACCESS / ( BUS_CYCLES * 1)",
16	"BriefDescription": "Core-to-uncore bus utilization",
17	"MetricGroup": "Bus",
18	"MetricName": "Bus utilization"
19    },
20    {
21	"MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
22	"BriefDescription": "L1D cache miss rate",
23	"MetricGroup": "Cache",
24	"MetricName": "L1D cache miss"
25    },
26    {
27	"MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD",
28	"BriefDescription": "L1D cache read miss rate",
29	"MetricGroup": "Cache",
30	"MetricName": "L1D cache read miss"
31    },
32    {
33	"MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
34	"BriefDescription": "L1I cache miss rate",
35	"MetricGroup": "Cache",
36	"MetricName": "L1I cache miss"
37    },
38    {
39	"MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
40	"BriefDescription": "L2 cache miss rate",
41	"MetricGroup": "Cache",
42	"MetricName": "L2 cache miss"
43    },
44    {
45	"MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE",
46	"BriefDescription": "L1I cache read miss rate",
47	"MetricGroup": "Cache",
48	"MetricName": "L1I cache read miss"
49    },
50    {
51	"MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD",
52	"BriefDescription": "L2 cache read miss rate",
53	"MetricGroup": "Cache",
54	"MetricName": "L2 cache read miss"
55    },
56    {
57	"MetricExpr": "(L1D_CACHE_LMISS_RD * 1000) / INST_RETIRED",
58	"BriefDescription": "Misses per thousand instructions (data)",
59	"MetricGroup": "Cache",
60	"MetricName": "MPKI data"
61    },
62    {
63	"MetricExpr": "(L1I_CACHE_LMISS * 1000) / INST_RETIRED",
64	"BriefDescription": "Misses per thousand instructions (instruction)",
65	"MetricGroup": "Cache",
66	"MetricName": "MPKI instruction"
67    },
68    {
69	"MetricExpr": "ASE_SPEC / OP_SPEC",
70	"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) operations",
71	"MetricGroup": "Instruction",
72	"MetricName": "ASE mix"
73    },
74    {
75	"MetricExpr": "CRYPTO_SPEC / OP_SPEC",
76	"BriefDescription": "Proportion of crypto data processing operations",
77	"MetricGroup": "Instruction",
78	"MetricName": "Crypto mix"
79    },
80    {
81	"MetricExpr": "VFP_SPEC / (duration_time *1000000000)",
82	"BriefDescription": "Giga-floating point operations per second",
83	"MetricGroup": "Instruction",
84	"MetricName": "GFLOPS_ISSUED"
85    },
86    {
87	"MetricExpr": "DP_SPEC / OP_SPEC",
88	"BriefDescription": "Proportion of integer data processing operations",
89	"MetricGroup": "Instruction",
90	"MetricName": "Integer mix"
91    },
92    {
93	"MetricExpr": "INST_RETIRED / CPU_CYCLES",
94	"BriefDescription": "Instructions per cycle",
95	"MetricGroup": "Instruction",
96	"MetricName": "IPC"
97    },
98    {
99	"MetricExpr": "LD_SPEC / OP_SPEC",
100	"BriefDescription": "Proportion of load operations",
101	"MetricGroup": "Instruction",
102	"MetricName": "Load mix"
103    },
104    {
105	"MetricExpr": "LDST_SPEC/ OP_SPEC",
106	"BriefDescription": "Proportion of load & store operations",
107	"MetricGroup": "Instruction",
108	"MetricName": "Load-store mix"
109    },
110    {
111	"MetricExpr": "INST_RETIRED / (duration_time * 1000000)",
112	"BriefDescription": "Millions of instructions per second",
113	"MetricGroup": "Instruction",
114	"MetricName": "MIPS_RETIRED"
115    },
116    {
117	"MetricExpr": "INST_SPEC / (duration_time * 1000000)",
118	"BriefDescription": "Millions of instructions per second",
119	"MetricGroup": "Instruction",
120	"MetricName": "MIPS_UTILIZATION"
121    },
122    {
123	"MetricExpr": "PC_WRITE_SPEC / OP_SPEC",
124	"BriefDescription": "Proportion of software change of PC operations",
125	"MetricGroup": "Instruction",
126	"MetricName": "PC write mix"
127    },
128    {
129	"MetricExpr": "ST_SPEC / OP_SPEC",
130	"BriefDescription": "Proportion of store operations",
131	"MetricGroup": "Instruction",
132	"MetricName": "Store mix"
133    },
134    {
135	"MetricExpr": "VFP_SPEC / OP_SPEC",
136	"BriefDescription": "Proportion of FP operations",
137	"MetricGroup": "Instruction",
138	"MetricName": "VFP mix"
139    },
140    {
141	"MetricExpr": "1 - (OP_RETIRED/ (CPU_CYCLES * 4))",
142	"BriefDescription": "Proportion of slots lost",
143	"MetricGroup": "Speculation / TDA",
144	"MetricName": "CPU lost"
145    },
146    {
147	"MetricExpr": "OP_RETIRED/ (CPU_CYCLES * 4)",
148	"BriefDescription": "Proportion of slots retiring",
149	"MetricGroup": "Speculation / TDA",
150	"MetricName": "CPU utilization"
151    },
152    {
153	"MetricExpr": "OP_RETIRED - OP_SPEC",
154	"BriefDescription": "Operations lost due to misspeculation",
155	"MetricGroup": "Speculation / TDA",
156	"MetricName": "Operations lost"
157    },
158    {
159	"MetricExpr": "1 - (OP_RETIRED / OP_SPEC)",
160	"BriefDescription": "Proportion of operations lost",
161	"MetricGroup": "Speculation / TDA",
162	"MetricName": "Operations lost (ratio)"
163    },
164    {
165	"MetricExpr": "OP_RETIRED / OP_SPEC",
166	"BriefDescription": "Proportion of operations retired",
167	"MetricGroup": "Speculation / TDA",
168	"MetricName": "Operations retired"
169    },
170    {
171	"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
172	"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss",
173	"MetricGroup": "Stall",
174	"MetricName": "Stall backend cache cycles"
175    },
176    {
177	"MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
178	"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full",
179	"MetricGroup": "Stall",
180	"MetricName": "Stall backend resource cycles"
181    },
182    {
183	"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
184	"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
185	"MetricGroup": "Stall",
186	"MetricName": "Stall backend tlb cycles"
187    },
188    {
189	"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
190	"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss",
191	"MetricGroup": "Stall",
192	"MetricName": "Stall frontend cache cycles"
193    },
194    {
195	"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
196	"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
197	"MetricGroup": "Stall",
198	"MetricName": "Stall frontend tlb cycles"
199    },
200    {
201	"MetricExpr": "DTLB_WALK / L1D_TLB",
202	"BriefDescription": "D-side walk per d-side translation request",
203	"MetricGroup": "TLB",
204	"MetricName": "DTLB walks"
205    },
206    {
207	"MetricExpr": "ITLB_WALK / L1I_TLB",
208	"BriefDescription": "I-side walk per i-side translation request",
209	"MetricGroup": "TLB",
210	"MetricName": "ITLB walks"
211    },
212    {
213        "MetricExpr": "STALL_SLOT_BACKEND / (CPU_CYCLES * 4)",
214        "BriefDescription": "Fraction of slots backend bound",
215        "MetricGroup": "TopDownL1",
216        "MetricName": "backend"
217    },
218    {
219        "MetricExpr": "1 - (retiring + lost + backend)",
220        "BriefDescription": "Fraction of slots frontend bound",
221        "MetricGroup": "TopDownL1",
222        "MetricName": "frontend"
223    },
224    {
225        "MetricExpr": "((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * 4))",
226        "BriefDescription": "Fraction of slots lost due to misspeculation",
227        "MetricGroup": "TopDownL1",
228        "MetricName": "lost"
229    },
230    {
231        "MetricExpr": "(OP_RETIRED / (CPU_CYCLES * 4))",
232        "BriefDescription": "Fraction of slots retiring, useful work",
233        "MetricGroup": "TopDownL1",
234        "MetricName": "retiring"
235    },
236    {
237        "MetricExpr": "backend - backend_memory",
238        "BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues",
239        "MetricGroup": "TopDownL2",
240        "MetricName": "backend_core"
241    },
242    {
243        "MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE + STALL_BACKEND_MEM) / CPU_CYCLES ",
244        "BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)",
245        "MetricGroup": "TopDownL2",
246        "MetricName": "backend_memory"
247    },
248    {
249        "MetricExpr": " (BR_MIS_PRED_RETIRED / GPC_FLUSH) * lost",
250        "BriefDescription": "Fraction of slots lost due to branch misprediciton",
251        "MetricGroup": "TopDownL2",
252        "MetricName": "branch_mispredict"
253    },
254    {
255        "MetricExpr": "frontend - frontend_latency",
256        "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)",
257        "MetricGroup": "TopDownL2",
258        "MetricName": "frontend_bandwidth"
259    },
260    {
261        "MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - (frontend * CPU_CYCLES * 4)) / 4)) / CPU_CYCLES",
262        "BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch",
263        "MetricGroup": "TopDownL2",
264        "MetricName": "frontend_latency"
265    },
266    {
267        "MetricExpr": "lost - branch_mispredict",
268        "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
269        "MetricGroup": "TopDownL2",
270        "MetricName": "other_clears"
271    },
272    {
273        "MetricExpr": "(IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6)",
274        "BriefDescription": "Fraction of execute slots utilized",
275        "MetricGroup": "TopDownL2",
276        "MetricName": "pipe_utilization"
277    },
278    {
279        "MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES",
280        "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
281        "MetricGroup": "TopDownL3",
282        "MetricName": "d_cache_l2_miss"
283    },
284    {
285        "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
286        "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
287        "MetricGroup": "TopDownL3",
288        "MetricName": "d_cache_miss"
289    },
290    {
291        "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
292        "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
293        "MetricGroup": "TopDownL3",
294        "MetricName": "d_tlb_miss"
295    },
296    {
297        "MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)",
298        "BriefDescription": "Fraction of FSU execute slots utilized",
299        "MetricGroup": "TopDownL3",
300        "MetricName": "fsu_pipe_utilization"
301    },
302    {
303        "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
304        "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
305        "MetricGroup": "TopDownL3",
306        "MetricName": "i_cache_miss"
307    },
308    {
309        "MetricExpr": " STALL_FRONTEND_TLB / CPU_CYCLES ",
310        "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
311        "MetricGroup": "TopDownL3",
312        "MetricName": "i_tlb_miss"
313    },
314    {
315        "MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES / 4)",
316        "BriefDescription": "Fraction of IXU execute slots utilized",
317        "MetricGroup": "TopDownL3",
318        "MetricName": "ixu_pipe_utilization"
319    },
320    {
321        "MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES",
322        "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
323        "MetricGroup": "TopDownL3",
324        "MetricName": "recovery"
325    },
326    {
327        "MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
328        "BriefDescription": "Fraction of cycles the CPU was stalled due to core resource shortage",
329        "MetricGroup": "TopDownL3",
330        "MetricName": "resource"
331    },
332    {
333        "MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES ",
334        "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
335        "MetricGroup": "TopDownL4",
336        "MetricName": "stall_fsu_sched"
337    },
338    {
339        "MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES ",
340        "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
341        "MetricGroup": "TopDownL4",
342        "MetricName": "stall_ixu_sched"
343    },
344    {
345        "MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES ",
346        "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
347        "MetricGroup": "TopDownL4",
348        "MetricName": "stall_lob_id"
349    },
350    {
351        "MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES",
352        "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
353        "MetricGroup": "TopDownL4",
354        "MetricName": "stall_rob_id"
355    },
356    {
357        "MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES ",
358        "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
359        "MetricGroup": "TopDownL4",
360        "MetricName": "stall_sob_id"
361    }
362]
363