1705ed549SIlkka Koskinen[ 2705ed549SIlkka Koskinen { 3*fe9d8c08SIlkka Koskinen "MetricName": "branch_miss_pred_rate", 4705ed549SIlkka Koskinen "MetricExpr": "BR_MIS_PRED / BR_PRED", 5705ed549SIlkka Koskinen "BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch", 6*fe9d8c08SIlkka Koskinen "MetricGroup": "branch", 7*fe9d8c08SIlkka Koskinen "ScaleUnit": "100%" 8705ed549SIlkka Koskinen }, 9705ed549SIlkka Koskinen { 10*fe9d8c08SIlkka Koskinen "MetricName": "bus_utilization", 11*fe9d8c08SIlkka Koskinen "MetricExpr": "((BUS_ACCESS / (BUS_CYCLES * 1)) * 100)", 12705ed549SIlkka Koskinen "BriefDescription": "Core-to-uncore bus utilization", 13705ed549SIlkka Koskinen "MetricGroup": "Bus", 14*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of bus cycles" 15705ed549SIlkka Koskinen }, 16705ed549SIlkka Koskinen { 17*fe9d8c08SIlkka Koskinen "MetricName": "l1d_cache_miss_ratio", 18*fe9d8c08SIlkka Koskinen "MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)", 19*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", 20*fe9d8c08SIlkka Koskinen "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", 21*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cache access" 22705ed549SIlkka Koskinen }, 23705ed549SIlkka Koskinen { 24*fe9d8c08SIlkka Koskinen "MetricName": "l1i_cache_miss_ratio", 25*fe9d8c08SIlkka Koskinen "MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)", 26*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", 27*fe9d8c08SIlkka Koskinen "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", 28*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cache access" 29*fe9d8c08SIlkka Koskinen }, 30*fe9d8c08SIlkka Koskinen { 31*fe9d8c08SIlkka Koskinen "MetricName": "Miss_Ratio;l1d_cache_read_miss", 32705ed549SIlkka Koskinen "MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD", 33705ed549SIlkka Koskinen "BriefDescription": "L1D cache read miss rate", 34705ed549SIlkka Koskinen "MetricGroup": "Cache", 35*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cache read access" 36705ed549SIlkka Koskinen }, 37705ed549SIlkka Koskinen { 38*fe9d8c08SIlkka Koskinen "MetricName": "l2_cache_miss_ratio", 39*fe9d8c08SIlkka Koskinen "MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)", 40*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", 41*fe9d8c08SIlkka Koskinen "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", 42*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cache access" 43705ed549SIlkka Koskinen }, 44705ed549SIlkka Koskinen { 45*fe9d8c08SIlkka Koskinen "MetricName": "l1i_cache_read_miss_rate", 46705ed549SIlkka Koskinen "MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE", 47705ed549SIlkka Koskinen "BriefDescription": "L1I cache read miss rate", 48705ed549SIlkka Koskinen "MetricGroup": "Cache", 49*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cache access" 50705ed549SIlkka Koskinen }, 51705ed549SIlkka Koskinen { 52*fe9d8c08SIlkka Koskinen "MetricName": "l2d_cache_read_miss_rate", 53705ed549SIlkka Koskinen "MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD", 54705ed549SIlkka Koskinen "BriefDescription": "L2 cache read miss rate", 55705ed549SIlkka Koskinen "MetricGroup": "Cache", 56*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cache read access" 57705ed549SIlkka Koskinen }, 58705ed549SIlkka Koskinen { 59*fe9d8c08SIlkka Koskinen "MetricName": "l1d_cache_miss_mpki", 60*fe9d8c08SIlkka Koskinen "MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED", 61705ed549SIlkka Koskinen "BriefDescription": "Misses per thousand instructions (data)", 62705ed549SIlkka Koskinen "MetricGroup": "Cache", 63*fe9d8c08SIlkka Koskinen "ScaleUnit": "1MPKI" 64705ed549SIlkka Koskinen }, 65705ed549SIlkka Koskinen { 66*fe9d8c08SIlkka Koskinen "MetricName": "l1i_cache_miss_mpki", 67*fe9d8c08SIlkka Koskinen "MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED", 68705ed549SIlkka Koskinen "BriefDescription": "Misses per thousand instructions (instruction)", 69705ed549SIlkka Koskinen "MetricGroup": "Cache", 70*fe9d8c08SIlkka Koskinen "ScaleUnit": "1MPKI" 71705ed549SIlkka Koskinen }, 72705ed549SIlkka Koskinen { 73*fe9d8c08SIlkka Koskinen "MetricName": "simd_percentage", 74*fe9d8c08SIlkka Koskinen "MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)", 75*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", 76*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 77*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 78705ed549SIlkka Koskinen }, 79705ed549SIlkka Koskinen { 80*fe9d8c08SIlkka Koskinen "MetricName": "crypto_percentage", 81*fe9d8c08SIlkka Koskinen "MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)", 82*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", 83*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 84*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 85705ed549SIlkka Koskinen }, 86705ed549SIlkka Koskinen { 87*fe9d8c08SIlkka Koskinen "MetricName": "gflops", 88*fe9d8c08SIlkka Koskinen "MetricExpr": "VFP_SPEC / (duration_time * 1e9)", 89705ed549SIlkka Koskinen "BriefDescription": "Giga-floating point operations per second", 90*fe9d8c08SIlkka Koskinen "MetricGroup": "InstructionMix" 91705ed549SIlkka Koskinen }, 92705ed549SIlkka Koskinen { 93*fe9d8c08SIlkka Koskinen "MetricName": "integer_dp_percentage", 94*fe9d8c08SIlkka Koskinen "MetricExpr": "((DP_SPEC / INST_SPEC) * 100)", 95*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", 96*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 97*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 98705ed549SIlkka Koskinen }, 99705ed549SIlkka Koskinen { 100*fe9d8c08SIlkka Koskinen "MetricName": "ipc", 101*fe9d8c08SIlkka Koskinen "MetricExpr": "(INST_RETIRED / CPU_CYCLES)", 102*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures the number of instructions retired per cycle.", 103*fe9d8c08SIlkka Koskinen "MetricGroup": "General", 104*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per cycle" 105705ed549SIlkka Koskinen }, 106705ed549SIlkka Koskinen { 107*fe9d8c08SIlkka Koskinen "MetricName": "load_percentage", 108*fe9d8c08SIlkka Koskinen "MetricExpr": "((LD_SPEC / INST_SPEC) * 100)", 109*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", 110*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 111*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 112705ed549SIlkka Koskinen }, 113705ed549SIlkka Koskinen { 114*fe9d8c08SIlkka Koskinen "MetricName": "load_store_spec_rate", 115*fe9d8c08SIlkka Koskinen "MetricExpr": "((LDST_SPEC / INST_SPEC) * 100)", 116*fe9d8c08SIlkka Koskinen "BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speclatively executed", 117*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 118*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 119705ed549SIlkka Koskinen }, 120705ed549SIlkka Koskinen { 121*fe9d8c08SIlkka Koskinen "MetricName": "retired_mips", 122*fe9d8c08SIlkka Koskinen "MetricExpr": "INST_RETIRED / (duration_time * 1e6)", 123705ed549SIlkka Koskinen "BriefDescription": "Millions of instructions per second", 124*fe9d8c08SIlkka Koskinen "MetricGroup": "InstructionMix" 125705ed549SIlkka Koskinen }, 126705ed549SIlkka Koskinen { 127*fe9d8c08SIlkka Koskinen "MetricName": "spec_utilization_mips", 128*fe9d8c08SIlkka Koskinen "MetricExpr": "INST_SPEC / (duration_time * 1e6)", 129705ed549SIlkka Koskinen "BriefDescription": "Millions of instructions per second", 130*fe9d8c08SIlkka Koskinen "MetricGroup": "PEutilization" 131705ed549SIlkka Koskinen }, 132705ed549SIlkka Koskinen { 133*fe9d8c08SIlkka Koskinen "MetricName": "pc_write_spec_rate", 134*fe9d8c08SIlkka Koskinen "MetricExpr": "((PC_WRITE_SPEC / INST_SPEC) * 100)", 135*fe9d8c08SIlkka Koskinen "BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speclatively executed", 136*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 137*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 138705ed549SIlkka Koskinen }, 139705ed549SIlkka Koskinen { 140*fe9d8c08SIlkka Koskinen "MetricName": "store_percentage", 141*fe9d8c08SIlkka Koskinen "MetricExpr": "((ST_SPEC / INST_SPEC) * 100)", 142*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", 143*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 144*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 145705ed549SIlkka Koskinen }, 146705ed549SIlkka Koskinen { 147*fe9d8c08SIlkka Koskinen "MetricName": "scalar_fp_percentage", 148*fe9d8c08SIlkka Koskinen "MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)", 149*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", 150*fe9d8c08SIlkka Koskinen "MetricGroup": "Operation_Mix", 151*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of operations" 152705ed549SIlkka Koskinen }, 153705ed549SIlkka Koskinen { 154*fe9d8c08SIlkka Koskinen "MetricName": "retired_rate", 155705ed549SIlkka Koskinen "MetricExpr": "OP_RETIRED / OP_SPEC", 156*fe9d8c08SIlkka Koskinen "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)", 157*fe9d8c08SIlkka Koskinen "MetricGroup": "General", 158*fe9d8c08SIlkka Koskinen "ScaleUnit": "100%" 159705ed549SIlkka Koskinen }, 160705ed549SIlkka Koskinen { 161*fe9d8c08SIlkka Koskinen "MetricName": "wasted", 162*fe9d8c08SIlkka Koskinen "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))", 163*fe9d8c08SIlkka Koskinen "BriefDescription": "Of all the micro-operations issued, what proportion are lost", 164*fe9d8c08SIlkka Koskinen "MetricGroup": "General", 165*fe9d8c08SIlkka Koskinen "ScaleUnit": "100%" 166*fe9d8c08SIlkka Koskinen }, 167*fe9d8c08SIlkka Koskinen { 168*fe9d8c08SIlkka Koskinen "MetricName": "wasted_rate", 169*fe9d8c08SIlkka Koskinen "MetricExpr": "1 - OP_RETIRED / OP_SPEC", 170*fe9d8c08SIlkka Koskinen "BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)", 171*fe9d8c08SIlkka Koskinen "MetricGroup": "General", 172*fe9d8c08SIlkka Koskinen "ScaleUnit": "100%" 173*fe9d8c08SIlkka Koskinen }, 174*fe9d8c08SIlkka Koskinen { 175*fe9d8c08SIlkka Koskinen "MetricName": "stall_backend_cache_rate", 176*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_BACKEND_CACHE / CPU_CYCLES) * 100)", 177705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss", 178705ed549SIlkka Koskinen "MetricGroup": "Stall", 179*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 180705ed549SIlkka Koskinen }, 181705ed549SIlkka Koskinen { 182*fe9d8c08SIlkka Koskinen "MetricName": "stall_backend_resource_rate", 183*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_BACKEND_RESOURCE / CPU_CYCLES) * 100)", 184705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full", 185705ed549SIlkka Koskinen "MetricGroup": "Stall", 186*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 187705ed549SIlkka Koskinen }, 188705ed549SIlkka Koskinen { 189*fe9d8c08SIlkka Koskinen "MetricName": "stall_backend_tlb_rate", 190*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_BACKEND_TLB / CPU_CYCLES) * 100)", 191705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss", 192705ed549SIlkka Koskinen "MetricGroup": "Stall", 193*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 194705ed549SIlkka Koskinen }, 195705ed549SIlkka Koskinen { 196*fe9d8c08SIlkka Koskinen "MetricName": "stall_frontend_cache_rate", 197*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_FRONTEND_CACHE / CPU_CYCLES) * 100)", 198705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss", 199705ed549SIlkka Koskinen "MetricGroup": "Stall", 200*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 201705ed549SIlkka Koskinen }, 202705ed549SIlkka Koskinen { 203*fe9d8c08SIlkka Koskinen "MetricName": "stall_frontend_tlb_rate", 204*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_FRONTEND_TLB / CPU_CYCLES) * 100)", 205705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss", 206705ed549SIlkka Koskinen "MetricGroup": "Stall", 207*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 208705ed549SIlkka Koskinen }, 209705ed549SIlkka Koskinen { 210*fe9d8c08SIlkka Koskinen "MetricName": "dtlb_walk_ratio", 211*fe9d8c08SIlkka Koskinen "MetricExpr": "(DTLB_WALK / L1D_TLB)", 212*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", 213*fe9d8c08SIlkka Koskinen "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", 214*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per TLB access" 215705ed549SIlkka Koskinen }, 216705ed549SIlkka Koskinen { 217*fe9d8c08SIlkka Koskinen "MetricName": "itlb_walk_ratio", 218*fe9d8c08SIlkka Koskinen "MetricExpr": "(ITLB_WALK / L1I_TLB)", 219*fe9d8c08SIlkka Koskinen "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", 220*fe9d8c08SIlkka Koskinen "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", 221*fe9d8c08SIlkka Koskinen "ScaleUnit": "1per TLB access" 222705ed549SIlkka Koskinen }, 223705ed549SIlkka Koskinen { 224*fe9d8c08SIlkka Koskinen "ArchStdEvent": "backend_bound" 225705ed549SIlkka Koskinen }, 226705ed549SIlkka Koskinen { 227*fe9d8c08SIlkka Koskinen "ArchStdEvent": "frontend_bound", 228*fe9d8c08SIlkka Koskinen "MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)" 229705ed549SIlkka Koskinen }, 230705ed549SIlkka Koskinen { 231*fe9d8c08SIlkka Koskinen "MetricName": "slots_lost_misspeculation_fraction", 232*fe9d8c08SIlkka Koskinen "MetricExpr": "100 * ((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots))", 233705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots lost due to misspeculation", 234*fe9d8c08SIlkka Koskinen "MetricGroup": "Default;TopdownL1", 235*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 236705ed549SIlkka Koskinen }, 237705ed549SIlkka Koskinen { 238*fe9d8c08SIlkka Koskinen "MetricName": "retired_fraction", 239*fe9d8c08SIlkka Koskinen "MetricExpr": "100 * (OP_RETIRED / (CPU_CYCLES * #slots))", 240705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots retiring, useful work", 241*fe9d8c08SIlkka Koskinen "MetricGroup": "Default;TopdownL1", 242*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 243705ed549SIlkka Koskinen }, 244705ed549SIlkka Koskinen { 245*fe9d8c08SIlkka Koskinen "MetricName": "backend_core", 246*fe9d8c08SIlkka Koskinen "MetricExpr": "(backend_bound / 100) - backend_memory", 247705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues", 248*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 249*fe9d8c08SIlkka Koskinen "ScaleUnit": "100%" 250705ed549SIlkka Koskinen }, 251705ed549SIlkka Koskinen { 252*fe9d8c08SIlkka Koskinen "MetricName": "backend_memory", 253*fe9d8c08SIlkka Koskinen "MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES", 254705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)", 255*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 256*fe9d8c08SIlkka Koskinen "ScaleUnit": "100%" 257705ed549SIlkka Koskinen }, 258705ed549SIlkka Koskinen { 259*fe9d8c08SIlkka Koskinen "MetricName": "branch_mispredict", 260*fe9d8c08SIlkka Koskinen "MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction", 261705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots lost due to branch misprediciton", 262*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 263*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 264705ed549SIlkka Koskinen }, 265705ed549SIlkka Koskinen { 266*fe9d8c08SIlkka Koskinen "MetricName": "frontend_bandwidth", 267*fe9d8c08SIlkka Koskinen "MetricExpr": "frontend_bound - frontend_latency", 268705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)", 269*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 270*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 271705ed549SIlkka Koskinen }, 272705ed549SIlkka Koskinen { 273*fe9d8c08SIlkka Koskinen "MetricName": "frontend_latency", 274*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES) * 100", 275705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch", 276*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 277*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 278705ed549SIlkka Koskinen }, 279705ed549SIlkka Koskinen { 280*fe9d8c08SIlkka Koskinen "MetricName": "other_miss_pred", 281*fe9d8c08SIlkka Koskinen "MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict", 282705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation", 283*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 284*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 285705ed549SIlkka Koskinen }, 286705ed549SIlkka Koskinen { 287*fe9d8c08SIlkka Koskinen "MetricName": "pipe_utilization", 288*fe9d8c08SIlkka Koskinen "MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))", 289705ed549SIlkka Koskinen "BriefDescription": "Fraction of execute slots utilized", 290*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL2", 291*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 292705ed549SIlkka Koskinen }, 293705ed549SIlkka Koskinen { 294*fe9d8c08SIlkka Koskinen "MetricName": "d_cache_l2_miss_rate", 295*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_BACKEND_MEM / CPU_CYCLES) * 100)", 296705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss", 297*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 298*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 299705ed549SIlkka Koskinen }, 300705ed549SIlkka Koskinen { 301*fe9d8c08SIlkka Koskinen "MetricName": "d_cache_miss_rate", 302*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_BACKEND_CACHE / CPU_CYCLES) * 100)", 303705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss", 304*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 305*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 306705ed549SIlkka Koskinen }, 307705ed549SIlkka Koskinen { 308*fe9d8c08SIlkka Koskinen "MetricName": "d_tlb_miss_rate", 309*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_BACKEND_TLB / CPU_CYCLES) * 100)", 310705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss", 311*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 312*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 313705ed549SIlkka Koskinen }, 314705ed549SIlkka Koskinen { 315*fe9d8c08SIlkka Koskinen "MetricName": "fsu_pipe_utilization", 316*fe9d8c08SIlkka Koskinen "MetricExpr": "((FSU_ISSUED / (CPU_CYCLES * 2)) * 100)", 317705ed549SIlkka Koskinen "BriefDescription": "Fraction of FSU execute slots utilized", 318*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 319*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 320705ed549SIlkka Koskinen }, 321705ed549SIlkka Koskinen { 322*fe9d8c08SIlkka Koskinen "MetricName": "i_cache_miss_rate", 323*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_FRONTEND_CACHE / CPU_CYCLES) * 100)", 324705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss", 325*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 326*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 327705ed549SIlkka Koskinen }, 328705ed549SIlkka Koskinen { 329*fe9d8c08SIlkka Koskinen "MetricName": "i_tlb_miss_rate", 330*fe9d8c08SIlkka Koskinen "MetricExpr": "((STALL_FRONTEND_TLB / CPU_CYCLES) * 100)", 331705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss", 332*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 333*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 334705ed549SIlkka Koskinen }, 335705ed549SIlkka Koskinen { 336*fe9d8c08SIlkka Koskinen "MetricName": "ixu_pipe_utilization", 337*fe9d8c08SIlkka Koskinen "MetricExpr": "((IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)) * 100)", 338705ed549SIlkka Koskinen "BriefDescription": "Fraction of IXU execute slots utilized", 339*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 340*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 341705ed549SIlkka Koskinen }, 342705ed549SIlkka Koskinen { 343*fe9d8c08SIlkka Koskinen "MetricName": "stall_recovery_rate", 344*fe9d8c08SIlkka Koskinen "MetricExpr": "((IDR_STALL_FLUSH / CPU_CYCLES) * 100)", 345705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery", 346*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL3", 347*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of slots" 348705ed549SIlkka Koskinen }, 349705ed549SIlkka Koskinen { 350*fe9d8c08SIlkka Koskinen "MetricName": "stall_fsu_sched_rate", 351*fe9d8c08SIlkka Koskinen "MetricExpr": "((IDR_STALL_FSU_SCHED / CPU_CYCLES) * 100)", 352705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full", 353*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL4", 354*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 355705ed549SIlkka Koskinen }, 356705ed549SIlkka Koskinen { 357*fe9d8c08SIlkka Koskinen "MetricName": "stall_ixu_sched_rate", 358*fe9d8c08SIlkka Koskinen "MetricExpr": "((IDR_STALL_IXU_SCHED / CPU_CYCLES) * 100)", 359705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full", 360*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL4", 361*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 362705ed549SIlkka Koskinen }, 363705ed549SIlkka Koskinen { 364*fe9d8c08SIlkka Koskinen "MetricName": "stall_lob_id_rate", 365*fe9d8c08SIlkka Koskinen "MetricExpr": "((IDR_STALL_LOB_ID / CPU_CYCLES) * 100)", 366705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full", 367*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL4", 368*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 369705ed549SIlkka Koskinen }, 370705ed549SIlkka Koskinen { 371*fe9d8c08SIlkka Koskinen "MetricName": "stall_rob_id_rate", 372*fe9d8c08SIlkka Koskinen "MetricExpr": "((IDR_STALL_ROB_ID / CPU_CYCLES) * 100)", 373705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full", 374*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL4", 375*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 376705ed549SIlkka Koskinen }, 377705ed549SIlkka Koskinen { 378*fe9d8c08SIlkka Koskinen "MetricName": "stall_sob_id_rate", 379*fe9d8c08SIlkka Koskinen "MetricExpr": "((IDR_STALL_SOB_ID / CPU_CYCLES) * 100)", 380705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full", 381*fe9d8c08SIlkka Koskinen "MetricGroup": "TopdownL4", 382*fe9d8c08SIlkka Koskinen "ScaleUnit": "1percent of cycles" 383705ed549SIlkka Koskinen } 384705ed549SIlkka Koskinen] 385