1*705ed549SIlkka Koskinen[ 2*705ed549SIlkka Koskinen { 3*705ed549SIlkka Koskinen "MetricExpr": "BR_MIS_PRED / BR_PRED", 4*705ed549SIlkka Koskinen "BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch", 5*705ed549SIlkka Koskinen "MetricGroup": "Branch Prediction", 6*705ed549SIlkka Koskinen "MetricName": "Misprediction" 7*705ed549SIlkka Koskinen }, 8*705ed549SIlkka Koskinen { 9*705ed549SIlkka Koskinen "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", 10*705ed549SIlkka Koskinen "BriefDescription": "Branch predictor misprediction rate", 11*705ed549SIlkka Koskinen "MetricGroup": "Branch Prediction", 12*705ed549SIlkka Koskinen "MetricName": "Misprediction (retired)" 13*705ed549SIlkka Koskinen }, 14*705ed549SIlkka Koskinen { 15*705ed549SIlkka Koskinen "MetricExpr": "BUS_ACCESS / ( BUS_CYCLES * 1)", 16*705ed549SIlkka Koskinen "BriefDescription": "Core-to-uncore bus utilization", 17*705ed549SIlkka Koskinen "MetricGroup": "Bus", 18*705ed549SIlkka Koskinen "MetricName": "Bus utilization" 19*705ed549SIlkka Koskinen }, 20*705ed549SIlkka Koskinen { 21*705ed549SIlkka Koskinen "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", 22*705ed549SIlkka Koskinen "BriefDescription": "L1D cache miss rate", 23*705ed549SIlkka Koskinen "MetricGroup": "Cache", 24*705ed549SIlkka Koskinen "MetricName": "L1D cache miss" 25*705ed549SIlkka Koskinen }, 26*705ed549SIlkka Koskinen { 27*705ed549SIlkka Koskinen "MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD", 28*705ed549SIlkka Koskinen "BriefDescription": "L1D cache read miss rate", 29*705ed549SIlkka Koskinen "MetricGroup": "Cache", 30*705ed549SIlkka Koskinen "MetricName": "L1D cache read miss" 31*705ed549SIlkka Koskinen }, 32*705ed549SIlkka Koskinen { 33*705ed549SIlkka Koskinen "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", 34*705ed549SIlkka Koskinen "BriefDescription": "L1I cache miss rate", 35*705ed549SIlkka Koskinen "MetricGroup": "Cache", 36*705ed549SIlkka Koskinen "MetricName": "L1I cache miss" 37*705ed549SIlkka Koskinen }, 38*705ed549SIlkka Koskinen { 39*705ed549SIlkka Koskinen "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", 40*705ed549SIlkka Koskinen "BriefDescription": "L2 cache miss rate", 41*705ed549SIlkka Koskinen "MetricGroup": "Cache", 42*705ed549SIlkka Koskinen "MetricName": "L2 cache miss" 43*705ed549SIlkka Koskinen }, 44*705ed549SIlkka Koskinen { 45*705ed549SIlkka Koskinen "MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE", 46*705ed549SIlkka Koskinen "BriefDescription": "L1I cache read miss rate", 47*705ed549SIlkka Koskinen "MetricGroup": "Cache", 48*705ed549SIlkka Koskinen "MetricName": "L1I cache read miss" 49*705ed549SIlkka Koskinen }, 50*705ed549SIlkka Koskinen { 51*705ed549SIlkka Koskinen "MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD", 52*705ed549SIlkka Koskinen "BriefDescription": "L2 cache read miss rate", 53*705ed549SIlkka Koskinen "MetricGroup": "Cache", 54*705ed549SIlkka Koskinen "MetricName": "L2 cache read miss" 55*705ed549SIlkka Koskinen }, 56*705ed549SIlkka Koskinen { 57*705ed549SIlkka Koskinen "MetricExpr": "(L1D_CACHE_LMISS_RD * 1000) / INST_RETIRED", 58*705ed549SIlkka Koskinen "BriefDescription": "Misses per thousand instructions (data)", 59*705ed549SIlkka Koskinen "MetricGroup": "Cache", 60*705ed549SIlkka Koskinen "MetricName": "MPKI data" 61*705ed549SIlkka Koskinen }, 62*705ed549SIlkka Koskinen { 63*705ed549SIlkka Koskinen "MetricExpr": "(L1I_CACHE_LMISS * 1000) / INST_RETIRED", 64*705ed549SIlkka Koskinen "BriefDescription": "Misses per thousand instructions (instruction)", 65*705ed549SIlkka Koskinen "MetricGroup": "Cache", 66*705ed549SIlkka Koskinen "MetricName": "MPKI instruction" 67*705ed549SIlkka Koskinen }, 68*705ed549SIlkka Koskinen { 69*705ed549SIlkka Koskinen "MetricExpr": "ASE_SPEC / OP_SPEC", 70*705ed549SIlkka Koskinen "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) operations", 71*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 72*705ed549SIlkka Koskinen "MetricName": "ASE mix" 73*705ed549SIlkka Koskinen }, 74*705ed549SIlkka Koskinen { 75*705ed549SIlkka Koskinen "MetricExpr": "CRYPTO_SPEC / OP_SPEC", 76*705ed549SIlkka Koskinen "BriefDescription": "Proportion of crypto data processing operations", 77*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 78*705ed549SIlkka Koskinen "MetricName": "Crypto mix" 79*705ed549SIlkka Koskinen }, 80*705ed549SIlkka Koskinen { 81*705ed549SIlkka Koskinen "MetricExpr": "VFP_SPEC / (duration_time *1000000000)", 82*705ed549SIlkka Koskinen "BriefDescription": "Giga-floating point operations per second", 83*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 84*705ed549SIlkka Koskinen "MetricName": "GFLOPS_ISSUED" 85*705ed549SIlkka Koskinen }, 86*705ed549SIlkka Koskinen { 87*705ed549SIlkka Koskinen "MetricExpr": "DP_SPEC / OP_SPEC", 88*705ed549SIlkka Koskinen "BriefDescription": "Proportion of integer data processing operations", 89*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 90*705ed549SIlkka Koskinen "MetricName": "Integer mix" 91*705ed549SIlkka Koskinen }, 92*705ed549SIlkka Koskinen { 93*705ed549SIlkka Koskinen "MetricExpr": "INST_RETIRED / CPU_CYCLES", 94*705ed549SIlkka Koskinen "BriefDescription": "Instructions per cycle", 95*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 96*705ed549SIlkka Koskinen "MetricName": "IPC" 97*705ed549SIlkka Koskinen }, 98*705ed549SIlkka Koskinen { 99*705ed549SIlkka Koskinen "MetricExpr": "LD_SPEC / OP_SPEC", 100*705ed549SIlkka Koskinen "BriefDescription": "Proportion of load operations", 101*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 102*705ed549SIlkka Koskinen "MetricName": "Load mix" 103*705ed549SIlkka Koskinen }, 104*705ed549SIlkka Koskinen { 105*705ed549SIlkka Koskinen "MetricExpr": "LDST_SPEC/ OP_SPEC", 106*705ed549SIlkka Koskinen "BriefDescription": "Proportion of load & store operations", 107*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 108*705ed549SIlkka Koskinen "MetricName": "Load-store mix" 109*705ed549SIlkka Koskinen }, 110*705ed549SIlkka Koskinen { 111*705ed549SIlkka Koskinen "MetricExpr": "INST_RETIRED / (duration_time * 1000000)", 112*705ed549SIlkka Koskinen "BriefDescription": "Millions of instructions per second", 113*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 114*705ed549SIlkka Koskinen "MetricName": "MIPS_RETIRED" 115*705ed549SIlkka Koskinen }, 116*705ed549SIlkka Koskinen { 117*705ed549SIlkka Koskinen "MetricExpr": "INST_SPEC / (duration_time * 1000000)", 118*705ed549SIlkka Koskinen "BriefDescription": "Millions of instructions per second", 119*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 120*705ed549SIlkka Koskinen "MetricName": "MIPS_UTILIZATION" 121*705ed549SIlkka Koskinen }, 122*705ed549SIlkka Koskinen { 123*705ed549SIlkka Koskinen "MetricExpr": "PC_WRITE_SPEC / OP_SPEC", 124*705ed549SIlkka Koskinen "BriefDescription": "Proportion of software change of PC operations", 125*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 126*705ed549SIlkka Koskinen "MetricName": "PC write mix" 127*705ed549SIlkka Koskinen }, 128*705ed549SIlkka Koskinen { 129*705ed549SIlkka Koskinen "MetricExpr": "ST_SPEC / OP_SPEC", 130*705ed549SIlkka Koskinen "BriefDescription": "Proportion of store operations", 131*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 132*705ed549SIlkka Koskinen "MetricName": "Store mix" 133*705ed549SIlkka Koskinen }, 134*705ed549SIlkka Koskinen { 135*705ed549SIlkka Koskinen "MetricExpr": "VFP_SPEC / OP_SPEC", 136*705ed549SIlkka Koskinen "BriefDescription": "Proportion of FP operations", 137*705ed549SIlkka Koskinen "MetricGroup": "Instruction", 138*705ed549SIlkka Koskinen "MetricName": "VFP mix" 139*705ed549SIlkka Koskinen }, 140*705ed549SIlkka Koskinen { 141*705ed549SIlkka Koskinen "MetricExpr": "1 - (OP_RETIRED/ (CPU_CYCLES * 4))", 142*705ed549SIlkka Koskinen "BriefDescription": "Proportion of slots lost", 143*705ed549SIlkka Koskinen "MetricGroup": "Speculation / TDA", 144*705ed549SIlkka Koskinen "MetricName": "CPU lost" 145*705ed549SIlkka Koskinen }, 146*705ed549SIlkka Koskinen { 147*705ed549SIlkka Koskinen "MetricExpr": "OP_RETIRED/ (CPU_CYCLES * 4)", 148*705ed549SIlkka Koskinen "BriefDescription": "Proportion of slots retiring", 149*705ed549SIlkka Koskinen "MetricGroup": "Speculation / TDA", 150*705ed549SIlkka Koskinen "MetricName": "CPU utilization" 151*705ed549SIlkka Koskinen }, 152*705ed549SIlkka Koskinen { 153*705ed549SIlkka Koskinen "MetricExpr": "OP_RETIRED - OP_SPEC", 154*705ed549SIlkka Koskinen "BriefDescription": "Operations lost due to misspeculation", 155*705ed549SIlkka Koskinen "MetricGroup": "Speculation / TDA", 156*705ed549SIlkka Koskinen "MetricName": "Operations lost" 157*705ed549SIlkka Koskinen }, 158*705ed549SIlkka Koskinen { 159*705ed549SIlkka Koskinen "MetricExpr": "1 - (OP_RETIRED / OP_SPEC)", 160*705ed549SIlkka Koskinen "BriefDescription": "Proportion of operations lost", 161*705ed549SIlkka Koskinen "MetricGroup": "Speculation / TDA", 162*705ed549SIlkka Koskinen "MetricName": "Operations lost (ratio)" 163*705ed549SIlkka Koskinen }, 164*705ed549SIlkka Koskinen { 165*705ed549SIlkka Koskinen "MetricExpr": "OP_RETIRED / OP_SPEC", 166*705ed549SIlkka Koskinen "BriefDescription": "Proportion of operations retired", 167*705ed549SIlkka Koskinen "MetricGroup": "Speculation / TDA", 168*705ed549SIlkka Koskinen "MetricName": "Operations retired" 169*705ed549SIlkka Koskinen }, 170*705ed549SIlkka Koskinen { 171*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES", 172*705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss", 173*705ed549SIlkka Koskinen "MetricGroup": "Stall", 174*705ed549SIlkka Koskinen "MetricName": "Stall backend cache cycles" 175*705ed549SIlkka Koskinen }, 176*705ed549SIlkka Koskinen { 177*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES", 178*705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full", 179*705ed549SIlkka Koskinen "MetricGroup": "Stall", 180*705ed549SIlkka Koskinen "MetricName": "Stall backend resource cycles" 181*705ed549SIlkka Koskinen }, 182*705ed549SIlkka Koskinen { 183*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES", 184*705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss", 185*705ed549SIlkka Koskinen "MetricGroup": "Stall", 186*705ed549SIlkka Koskinen "MetricName": "Stall backend tlb cycles" 187*705ed549SIlkka Koskinen }, 188*705ed549SIlkka Koskinen { 189*705ed549SIlkka Koskinen "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", 190*705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss", 191*705ed549SIlkka Koskinen "MetricGroup": "Stall", 192*705ed549SIlkka Koskinen "MetricName": "Stall frontend cache cycles" 193*705ed549SIlkka Koskinen }, 194*705ed549SIlkka Koskinen { 195*705ed549SIlkka Koskinen "MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES", 196*705ed549SIlkka Koskinen "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss", 197*705ed549SIlkka Koskinen "MetricGroup": "Stall", 198*705ed549SIlkka Koskinen "MetricName": "Stall frontend tlb cycles" 199*705ed549SIlkka Koskinen }, 200*705ed549SIlkka Koskinen { 201*705ed549SIlkka Koskinen "MetricExpr": "DTLB_WALK / L1D_TLB", 202*705ed549SIlkka Koskinen "BriefDescription": "D-side walk per d-side translation request", 203*705ed549SIlkka Koskinen "MetricGroup": "TLB", 204*705ed549SIlkka Koskinen "MetricName": "DTLB walks" 205*705ed549SIlkka Koskinen }, 206*705ed549SIlkka Koskinen { 207*705ed549SIlkka Koskinen "MetricExpr": "ITLB_WALK / L1I_TLB", 208*705ed549SIlkka Koskinen "BriefDescription": "I-side walk per i-side translation request", 209*705ed549SIlkka Koskinen "MetricGroup": "TLB", 210*705ed549SIlkka Koskinen "MetricName": "ITLB walks" 211*705ed549SIlkka Koskinen }, 212*705ed549SIlkka Koskinen { 213*705ed549SIlkka Koskinen "MetricExpr": "STALL_SLOT_BACKEND / (CPU_CYCLES * 4)", 214*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots backend bound", 215*705ed549SIlkka Koskinen "MetricGroup": "TopDownL1", 216*705ed549SIlkka Koskinen "MetricName": "backend" 217*705ed549SIlkka Koskinen }, 218*705ed549SIlkka Koskinen { 219*705ed549SIlkka Koskinen "MetricExpr": "1 - (retiring + lost + backend)", 220*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots frontend bound", 221*705ed549SIlkka Koskinen "MetricGroup": "TopDownL1", 222*705ed549SIlkka Koskinen "MetricName": "frontend" 223*705ed549SIlkka Koskinen }, 224*705ed549SIlkka Koskinen { 225*705ed549SIlkka Koskinen "MetricExpr": "((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * 4))", 226*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots lost due to misspeculation", 227*705ed549SIlkka Koskinen "MetricGroup": "TopDownL1", 228*705ed549SIlkka Koskinen "MetricName": "lost" 229*705ed549SIlkka Koskinen }, 230*705ed549SIlkka Koskinen { 231*705ed549SIlkka Koskinen "MetricExpr": "(OP_RETIRED / (CPU_CYCLES * 4))", 232*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots retiring, useful work", 233*705ed549SIlkka Koskinen "MetricGroup": "TopDownL1", 234*705ed549SIlkka Koskinen "MetricName": "retiring" 235*705ed549SIlkka Koskinen }, 236*705ed549SIlkka Koskinen { 237*705ed549SIlkka Koskinen "MetricExpr": "backend - backend_memory", 238*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues", 239*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 240*705ed549SIlkka Koskinen "MetricName": "backend_core" 241*705ed549SIlkka Koskinen }, 242*705ed549SIlkka Koskinen { 243*705ed549SIlkka Koskinen "MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE + STALL_BACKEND_MEM) / CPU_CYCLES ", 244*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)", 245*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 246*705ed549SIlkka Koskinen "MetricName": "backend_memory" 247*705ed549SIlkka Koskinen }, 248*705ed549SIlkka Koskinen { 249*705ed549SIlkka Koskinen "MetricExpr": " (BR_MIS_PRED_RETIRED / GPC_FLUSH) * lost", 250*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots lost due to branch misprediciton", 251*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 252*705ed549SIlkka Koskinen "MetricName": "branch_mispredict" 253*705ed549SIlkka Koskinen }, 254*705ed549SIlkka Koskinen { 255*705ed549SIlkka Koskinen "MetricExpr": "frontend - frontend_latency", 256*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)", 257*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 258*705ed549SIlkka Koskinen "MetricName": "frontend_bandwidth" 259*705ed549SIlkka Koskinen }, 260*705ed549SIlkka Koskinen { 261*705ed549SIlkka Koskinen "MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - (frontend * CPU_CYCLES * 4)) / 4)) / CPU_CYCLES", 262*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch", 263*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 264*705ed549SIlkka Koskinen "MetricName": "frontend_latency" 265*705ed549SIlkka Koskinen }, 266*705ed549SIlkka Koskinen { 267*705ed549SIlkka Koskinen "MetricExpr": "lost - branch_mispredict", 268*705ed549SIlkka Koskinen "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation", 269*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 270*705ed549SIlkka Koskinen "MetricName": "other_clears" 271*705ed549SIlkka Koskinen }, 272*705ed549SIlkka Koskinen { 273*705ed549SIlkka Koskinen "MetricExpr": "(IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6)", 274*705ed549SIlkka Koskinen "BriefDescription": "Fraction of execute slots utilized", 275*705ed549SIlkka Koskinen "MetricGroup": "TopDownL2", 276*705ed549SIlkka Koskinen "MetricName": "pipe_utilization" 277*705ed549SIlkka Koskinen }, 278*705ed549SIlkka Koskinen { 279*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES", 280*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss", 281*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 282*705ed549SIlkka Koskinen "MetricName": "d_cache_l2_miss" 283*705ed549SIlkka Koskinen }, 284*705ed549SIlkka Koskinen { 285*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES", 286*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss", 287*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 288*705ed549SIlkka Koskinen "MetricName": "d_cache_miss" 289*705ed549SIlkka Koskinen }, 290*705ed549SIlkka Koskinen { 291*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES", 292*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss", 293*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 294*705ed549SIlkka Koskinen "MetricName": "d_tlb_miss" 295*705ed549SIlkka Koskinen }, 296*705ed549SIlkka Koskinen { 297*705ed549SIlkka Koskinen "MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)", 298*705ed549SIlkka Koskinen "BriefDescription": "Fraction of FSU execute slots utilized", 299*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 300*705ed549SIlkka Koskinen "MetricName": "fsu_pipe_utilization" 301*705ed549SIlkka Koskinen }, 302*705ed549SIlkka Koskinen { 303*705ed549SIlkka Koskinen "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", 304*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss", 305*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 306*705ed549SIlkka Koskinen "MetricName": "i_cache_miss" 307*705ed549SIlkka Koskinen }, 308*705ed549SIlkka Koskinen { 309*705ed549SIlkka Koskinen "MetricExpr": " STALL_FRONTEND_TLB / CPU_CYCLES ", 310*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss", 311*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 312*705ed549SIlkka Koskinen "MetricName": "i_tlb_miss" 313*705ed549SIlkka Koskinen }, 314*705ed549SIlkka Koskinen { 315*705ed549SIlkka Koskinen "MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES / 4)", 316*705ed549SIlkka Koskinen "BriefDescription": "Fraction of IXU execute slots utilized", 317*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 318*705ed549SIlkka Koskinen "MetricName": "ixu_pipe_utilization" 319*705ed549SIlkka Koskinen }, 320*705ed549SIlkka Koskinen { 321*705ed549SIlkka Koskinen "MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES", 322*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery", 323*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 324*705ed549SIlkka Koskinen "MetricName": "recovery" 325*705ed549SIlkka Koskinen }, 326*705ed549SIlkka Koskinen { 327*705ed549SIlkka Koskinen "MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES", 328*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled due to core resource shortage", 329*705ed549SIlkka Koskinen "MetricGroup": "TopDownL3", 330*705ed549SIlkka Koskinen "MetricName": "resource" 331*705ed549SIlkka Koskinen }, 332*705ed549SIlkka Koskinen { 333*705ed549SIlkka Koskinen "MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES ", 334*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full", 335*705ed549SIlkka Koskinen "MetricGroup": "TopDownL4", 336*705ed549SIlkka Koskinen "MetricName": "stall_fsu_sched" 337*705ed549SIlkka Koskinen }, 338*705ed549SIlkka Koskinen { 339*705ed549SIlkka Koskinen "MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES ", 340*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full", 341*705ed549SIlkka Koskinen "MetricGroup": "TopDownL4", 342*705ed549SIlkka Koskinen "MetricName": "stall_ixu_sched" 343*705ed549SIlkka Koskinen }, 344*705ed549SIlkka Koskinen { 345*705ed549SIlkka Koskinen "MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES ", 346*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full", 347*705ed549SIlkka Koskinen "MetricGroup": "TopDownL4", 348*705ed549SIlkka Koskinen "MetricName": "stall_lob_id" 349*705ed549SIlkka Koskinen }, 350*705ed549SIlkka Koskinen { 351*705ed549SIlkka Koskinen "MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES", 352*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full", 353*705ed549SIlkka Koskinen "MetricGroup": "TopDownL4", 354*705ed549SIlkka Koskinen "MetricName": "stall_rob_id" 355*705ed549SIlkka Koskinen }, 356*705ed549SIlkka Koskinen { 357*705ed549SIlkka Koskinen "MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES ", 358*705ed549SIlkka Koskinen "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full", 359*705ed549SIlkka Koskinen "MetricGroup": "TopDownL4", 360*705ed549SIlkka Koskinen "MetricName": "stall_sob_id" 361*705ed549SIlkka Koskinen } 362*705ed549SIlkka Koskinen] 363