1*a9650b7fSIlkka Koskinen[
2*a9650b7fSIlkka Koskinen    {
3*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE_RD"
4*a9650b7fSIlkka Koskinen    },
5*a9650b7fSIlkka Koskinen    {
6*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE_WR"
7*a9650b7fSIlkka Koskinen    },
8*a9650b7fSIlkka Koskinen    {
9*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
10*a9650b7fSIlkka Koskinen    },
11*a9650b7fSIlkka Koskinen    {
12*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE_INVAL"
13*a9650b7fSIlkka Koskinen    },
14*a9650b7fSIlkka Koskinen    {
15*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_TLB_REFILL_RD"
16*a9650b7fSIlkka Koskinen    },
17*a9650b7fSIlkka Koskinen    {
18*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_TLB_REFILL_WR"
19*a9650b7fSIlkka Koskinen    },
20*a9650b7fSIlkka Koskinen    {
21*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_RD"
22*a9650b7fSIlkka Koskinen    },
23*a9650b7fSIlkka Koskinen    {
24*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_WR"
25*a9650b7fSIlkka Koskinen    },
26*a9650b7fSIlkka Koskinen    {
27*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
28*a9650b7fSIlkka Koskinen    },
29*a9650b7fSIlkka Koskinen    {
30*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
31*a9650b7fSIlkka Koskinen    },
32*a9650b7fSIlkka Koskinen    {
33*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
34*a9650b7fSIlkka Koskinen    },
35*a9650b7fSIlkka Koskinen    {
36*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
37*a9650b7fSIlkka Koskinen    },
38*a9650b7fSIlkka Koskinen    {
39*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_INVAL"
40*a9650b7fSIlkka Koskinen    },
41*a9650b7fSIlkka Koskinen    {
42*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1I_CACHE_REFILL"
43*a9650b7fSIlkka Koskinen    },
44*a9650b7fSIlkka Koskinen    {
45*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1I_TLB_REFILL"
46*a9650b7fSIlkka Koskinen    },
47*a9650b7fSIlkka Koskinen    {
48*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE_REFILL"
49*a9650b7fSIlkka Koskinen    },
50*a9650b7fSIlkka Koskinen    {
51*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE"
52*a9650b7fSIlkka Koskinen    },
53*a9650b7fSIlkka Koskinen    {
54*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_TLB_REFILL"
55*a9650b7fSIlkka Koskinen    },
56*a9650b7fSIlkka Koskinen    {
57*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1I_CACHE"
58*a9650b7fSIlkka Koskinen    },
59*a9650b7fSIlkka Koskinen    {
60*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE"
61*a9650b7fSIlkka Koskinen    },
62*a9650b7fSIlkka Koskinen    {
63*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_REFILL"
64*a9650b7fSIlkka Koskinen    },
65*a9650b7fSIlkka Koskinen    {
66*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_WB"
67*a9650b7fSIlkka Koskinen    },
68*a9650b7fSIlkka Koskinen    {
69*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_TLB"
70*a9650b7fSIlkka Koskinen    },
71*a9650b7fSIlkka Koskinen    {
72*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1I_TLB"
73*a9650b7fSIlkka Koskinen    },
74*a9650b7fSIlkka Koskinen    {
75*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_TLB_REFILL"
76*a9650b7fSIlkka Koskinen    },
77*a9650b7fSIlkka Koskinen    {
78*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2I_TLB_REFILL"
79*a9650b7fSIlkka Koskinen    },
80*a9650b7fSIlkka Koskinen    {
81*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_TLB"
82*a9650b7fSIlkka Koskinen    },
83*a9650b7fSIlkka Koskinen    {
84*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2I_TLB"
85*a9650b7fSIlkka Koskinen    },
86*a9650b7fSIlkka Koskinen    {
87*a9650b7fSIlkka Koskinen        "ArchStdEvent": "DTLB_WALK"
88*a9650b7fSIlkka Koskinen    },
89*a9650b7fSIlkka Koskinen    {
90*a9650b7fSIlkka Koskinen        "ArchStdEvent": "ITLB_WALK"
91*a9650b7fSIlkka Koskinen    },
92*a9650b7fSIlkka Koskinen    {
93*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
94*a9650b7fSIlkka Koskinen    },
95*a9650b7fSIlkka Koskinen    {
96*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L1I_CACHE_LMISS"
97*a9650b7fSIlkka Koskinen    },
98*a9650b7fSIlkka Koskinen    {
99*a9650b7fSIlkka Koskinen        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
100*a9650b7fSIlkka Koskinen    }
101*a9650b7fSIlkka Koskinen]
102