1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #include <stdbool.h> 8 #include <linux/coresight-pmu.h> 9 #include <linux/zalloc.h> 10 11 #include "../../util/auxtrace.h" 12 #include "../../util/evlist.h" 13 #include "../../util/pmu.h" 14 #include "cs-etm.h" 15 #include "arm-spe.h" 16 17 static struct perf_pmu **find_all_arm_spe_pmus(int *nr_spes, int *err) 18 { 19 struct perf_pmu **arm_spe_pmus = NULL; 20 int ret, i, nr_cpus = sysconf(_SC_NPROCESSORS_CONF); 21 /* arm_spe_xxxxxxxxx\0 */ 22 char arm_spe_pmu_name[sizeof(ARM_SPE_PMU_NAME) + 10]; 23 24 arm_spe_pmus = zalloc(sizeof(struct perf_pmu *) * nr_cpus); 25 if (!arm_spe_pmus) { 26 pr_err("spes alloc failed\n"); 27 *err = -ENOMEM; 28 return NULL; 29 } 30 31 for (i = 0; i < nr_cpus; i++) { 32 ret = sprintf(arm_spe_pmu_name, "%s%d", ARM_SPE_PMU_NAME, i); 33 if (ret < 0) { 34 pr_err("sprintf failed\n"); 35 *err = -ENOMEM; 36 return NULL; 37 } 38 39 arm_spe_pmus[*nr_spes] = perf_pmu__find(arm_spe_pmu_name); 40 if (arm_spe_pmus[*nr_spes]) { 41 pr_debug2("%s %d: arm_spe_pmu %d type %d name %s\n", 42 __func__, __LINE__, *nr_spes, 43 arm_spe_pmus[*nr_spes]->type, 44 arm_spe_pmus[*nr_spes]->name); 45 (*nr_spes)++; 46 } 47 } 48 49 return arm_spe_pmus; 50 } 51 52 struct auxtrace_record 53 *auxtrace_record__init(struct perf_evlist *evlist, int *err) 54 { 55 struct perf_pmu *cs_etm_pmu; 56 struct perf_evsel *evsel; 57 bool found_etm = false; 58 bool found_spe = false; 59 static struct perf_pmu **arm_spe_pmus = NULL; 60 static int nr_spes = 0; 61 int i = 0; 62 63 if (!evlist) 64 return NULL; 65 66 cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME); 67 68 if (!arm_spe_pmus) 69 arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); 70 71 evlist__for_each_entry(evlist, evsel) { 72 if (cs_etm_pmu && 73 evsel->attr.type == cs_etm_pmu->type) 74 found_etm = true; 75 76 if (!nr_spes) 77 continue; 78 79 for (i = 0; i < nr_spes; i++) { 80 if (evsel->attr.type == arm_spe_pmus[i]->type) { 81 found_spe = true; 82 break; 83 } 84 } 85 } 86 87 if (found_etm && found_spe) { 88 pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n"); 89 *err = -EOPNOTSUPP; 90 return NULL; 91 } 92 93 if (found_etm) 94 return cs_etm_record_init(err); 95 96 #if defined(__aarch64__) 97 if (found_spe) 98 return arm_spe_recording_init(err, arm_spe_pmus[i]); 99 #endif 100 101 /* 102 * Clear 'err' even if we haven't found an event - that way perf 103 * record can still be used even if tracers aren't present. The NULL 104 * return value will take care of telling the infrastructure HW tracing 105 * isn't available. 106 */ 107 *err = 0; 108 return NULL; 109 } 110