1028f12eeSStephane Eranianperf-mem(1) 2028f12eeSStephane Eranian=========== 3028f12eeSStephane Eranian 4028f12eeSStephane EranianNAME 5028f12eeSStephane Eranian---- 6028f12eeSStephane Eranianperf-mem - Profile memory accesses 7028f12eeSStephane Eranian 8028f12eeSStephane EranianSYNOPSIS 9028f12eeSStephane Eranian-------- 10028f12eeSStephane Eranian[verse] 11028f12eeSStephane Eranian'perf mem' [<options>] (record [<command>] | report) 12028f12eeSStephane Eranian 13028f12eeSStephane EranianDESCRIPTION 14028f12eeSStephane Eranian----------- 1567121f85SStephane Eranian"perf mem record" runs a command and gathers memory operation data 16028f12eeSStephane Eranianfrom it, into perf.data. Perf record options are accepted and are passed through. 17028f12eeSStephane Eranian 1867121f85SStephane Eranian"perf mem report" displays the result. It invokes perf report with the 1967121f85SStephane Eranianright set of options to display a memory access profile. By default, loads 2067121f85SStephane Eranianand stores are sampled. Use the -t option to limit to loads or stores. 21028f12eeSStephane Eranian 22b6394097SAndi KleenNote that on Intel systems the memory latency reported is the use-latency, 23b6394097SAndi Kleennot the pure load (or store latency). Use latency includes any pipeline 24b6394097SAndi Kleenqueueing delays in addition to the memory subsystem latency. 25b6394097SAndi Kleen 26028f12eeSStephane EranianOPTIONS 27028f12eeSStephane Eranian------- 28028f12eeSStephane Eranian<command>...:: 29028f12eeSStephane Eranian Any command you can specify in a shell. 30028f12eeSStephane Eranian 313138a2efSSangwon Hong-i:: 323138a2efSSangwon Hong--input=<file>:: 333138a2efSSangwon Hong Input file name. 343138a2efSSangwon Hong 357e99b197SSangwon Hong-f:: 367e99b197SSangwon Hong--force:: 377e99b197SSangwon Hong Don't do ownership validation 387e99b197SSangwon Hong 39028f12eeSStephane Eranian-t:: 403138a2efSSangwon Hong--type=<type>:: 4167121f85SStephane Eranian Select the memory operation type: load or store (default: load,store) 42028f12eeSStephane Eranian 43028f12eeSStephane Eranian-D:: 443138a2efSSangwon Hong--dump-raw-samples:: 45028f12eeSStephane Eranian Dump the raw decoded samples on the screen in a format that is easy to parse with 46028f12eeSStephane Eranian one sample per line. 47028f12eeSStephane Eranian 48028f12eeSStephane Eranian-x:: 493138a2efSSangwon Hong--field-separator=<separator>:: 50028f12eeSStephane Eranian Specify the field separator used when dump raw samples (-D option). By default, 51028f12eeSStephane Eranian The separator is the space character. 52028f12eeSStephane Eranian 53028f12eeSStephane Eranian-C:: 543138a2efSSangwon Hong--cpu=<cpu>:: 553138a2efSSangwon Hong Monitor only on the list of CPUs provided. Multiple CPUs can be provided as a 563138a2efSSangwon Hong comma-separated list with no space: 0,1. Ranges of CPUs are specified with -: 0-2. Default 573138a2efSSangwon Hong is to monitor all CPUS. 583138a2efSSangwon Hong-U:: 593138a2efSSangwon Hong--hide-unresolved:: 603138a2efSSangwon Hong Only display entries resolved to a symbol. 613138a2efSSangwon Hong 623138a2efSSangwon Hong-p:: 633138a2efSSangwon Hong--phys-data:: 643138a2efSSangwon Hong Record/Report sample physical addresses 653138a2efSSangwon Hong 6606280e3bSKan Liang--data-page-size:: 6706280e3bSKan Liang Record/Report sample data address page size 6806280e3bSKan Liang 693138a2efSSangwon HongRECORD OPTIONS 703138a2efSSangwon Hong-------------- 713138a2efSSangwon Hong-e:: 723138a2efSSangwon Hong--event <event>:: 733138a2efSSangwon Hong Event selector. Use 'perf mem record -e list' to list available events. 74028f12eeSStephane Eranian 75ad16511bSJiri Olsa-K:: 76ad16511bSJiri Olsa--all-kernel:: 77ad16511bSJiri Olsa Configure all used events to run in kernel space. 78ad16511bSJiri Olsa 79ad16511bSJiri Olsa-U:: 80ad16511bSJiri Olsa--all-user:: 81ad16511bSJiri Olsa Configure all used events to run in user space. 82ad16511bSJiri Olsa 833138a2efSSangwon Hong-v:: 843138a2efSSangwon Hong--verbose:: 853138a2efSSangwon Hong Be more verbose (show counter open errors, etc) 86b0d745b3SJiri Olsa 873138a2efSSangwon Hong--ldlat <n>:: 88*f7b58cbdSRavi Bangoria Specify desired latency for loads event. Supported on Intel and Arm64 89*f7b58cbdSRavi Bangoria processors only. Ignored on other archs. 90c35aeb9dSKan Liang 91a7e9eab3SAndi KleenIn addition, for report all perf report options are valid, and for record 92a7e9eab3SAndi Kleenall perf record options. 93a7e9eab3SAndi Kleen 94028f12eeSStephane EranianSEE ALSO 95028f12eeSStephane Eranian-------- 96028f12eeSStephane Eranianlinkperf:perf-record[1], linkperf:perf-report[1] 97