1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [--no-desc] [--long-desc] 12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] 13 14DESCRIPTION 15----------- 16This command displays the symbolic event types which can be selected in the 17various perf commands with the -e option. 18 19OPTIONS 20------- 21--no-desc:: 22Don't print descriptions. 23 24-v:: 25--long-desc:: 26Print longer event descriptions. 27 28--details:: 29Print how named events are resolved internally into perf events, and also 30any extra expressions computed by perf stat. 31 32 33[[EVENT_MODIFIERS]] 34EVENT MODIFIERS 35--------------- 36 37Events can optionally have a modifier by appending a colon and one or 38more modifiers. Modifiers allow the user to restrict the events to be 39counted. The following modifiers exist: 40 41 u - user-space counting 42 k - kernel counting 43 h - hypervisor counting 44 I - non idle counting 45 G - guest counting (in KVM guests) 46 H - host counting (not in KVM guests) 47 p - precise level 48 P - use maximum detected precise level 49 S - read sample value (PERF_SAMPLE_READ) 50 D - pin the event to the PMU 51 W - group is weak and will fallback to non-group if not schedulable, 52 only supported in 'perf stat' for now. 53 54The 'p' modifier can be used for specifying how precise the instruction 55address should be. The 'p' modifier can be specified multiple times: 56 57 0 - SAMPLE_IP can have arbitrary skid 58 1 - SAMPLE_IP must have constant skid 59 2 - SAMPLE_IP requested to have 0 skid 60 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 61 sample shadowing effects. 62 63For Intel systems precise event sampling is implemented with PEBS 64which supports up to precise-level 2, and precise level 3 for 65some special cases 66 67On AMD systems it is implemented using IBS (up to precise-level 2). 68The precise modifier works with event types 0x76 (cpu-cycles, CPU 69clocks not halted) and 0xC1 (micro-ops retired). Both events map to 70IBS execution sampling (IBS op) with the IBS Op Counter Control bit 71(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s 72Manual Volume 2: System Programming, 13.3 Instruction-Based 73Sampling). Examples to use IBS: 74 75 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 76 perf record -a -e r076:p ... # same as -e cpu-cycles:p 77 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 78 79RAW HARDWARE EVENT DESCRIPTOR 80----------------------------- 81Even when an event is not available in a symbolic form within perf right now, 82it can be encoded in a per processor specific way. 83 84For instance For x86 CPUs NNN represents the raw register encoding with the 85layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 86of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, 87Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 88 89Note: Only the following bit fields can be set in x86 counter 90registers: event, umask, edge, inv, cmask. Esp. guest/host only and 91OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 92MODIFIERS>>. 93 94Example: 95 96If the Intel docs for a QM720 Core i7 describe an event as: 97 98 Event Umask Event Mask 99 Num. Value Mnemonic Description Comment 100 101 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 102 delivered by loop stream detector invert to count 103 cycles 104 105raw encoding of 0x1A8 can be used: 106 107 perf stat -e r1a8 -a sleep 1 108 perf record -e r1a8 ... 109 110You should refer to the processor specific documentation for getting these 111details. Some of them are referenced in the SEE ALSO section below. 112 113ARBITRARY PMUS 114-------------- 115 116perf also supports an extended syntax for specifying raw parameters 117to PMUs. Using this typically requires looking up the specific event 118in the CPU vendor specific documentation. 119 120The available PMUs and their raw parameters can be listed with 121 122 ls /sys/devices/*/format 123 124For example the raw event "LSD.UOPS" core pmu event above could 125be specified as 126 127 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... 128 129 or using extended name syntax 130 131 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... 132 133PER SOCKET PMUS 134--------------- 135 136Some PMUs are not associated with a core, but with a whole CPU socket. 137Events on these PMUs generally cannot be sampled, but only counted globally 138with perf stat -a. They can be bound to one logical CPU, but will measure 139all the CPUs in the same socket. 140 141This example measures memory bandwidth every second 142on the first memory controller on socket 0 of a Intel Xeon system 143 144 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 145 146Each memory controller has its own PMU. Measuring the complete system 147bandwidth would require specifying all imc PMUs (see perf list output), 148and adding the values together. To simplify creation of multiple events, 149prefix and glob matching is supported in the PMU name, and the prefix 150'uncore_' is also ignored when performing the match. So the command above 151can be expanded to all memory controllers by using the syntaxes: 152 153 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... 154 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... 155 156This example measures the combined core power every second 157 158 perf stat -I 1000 -e power/energy-cores/ -a 159 160ACCESS RESTRICTIONS 161------------------- 162 163For non root users generally only context switched PMU events are available. 164This is normally only the events in the cpu PMU, the predefined events 165like cycles and instructions and some software events. 166 167Other PMUs and global measurements are normally root only. 168Some event qualifiers, such as "any", are also root only. 169 170This can be overriden by setting the kernel.perf_event_paranoid 171sysctl to -1, which allows non root to use these events. 172 173For accessing trace point events perf needs to have read access to 174/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed 175setting. 176 177TRACING 178------- 179 180Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 181that allows low overhead execution tracing. These are described in a separate 182intel-pt.txt document. 183 184PARAMETERIZED EVENTS 185-------------------- 186 187Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 188example: 189 190 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 191 192This means that when provided as an event, a value for '?' must 193also be supplied. For example: 194 195 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 196 197EVENT GROUPS 198------------ 199 200Perf supports time based multiplexing of events, when the number of events 201active exceeds the number of hardware performance counters. Multiplexing 202can cause measurement errors when the workload changes its execution 203profile. 204 205When metrics are computed using formulas from event counts, it is useful to 206ensure some events are always measured together as a group to minimize multiplexing 207errors. Event groups can be specified using { }. 208 209 perf stat -e '{instructions,cycles}' ... 210 211The number of available performance counters depend on the CPU. A group 212cannot contain more events than available counters. 213For example Intel Core CPUs typically have four generic performance counters 214for the core, plus three fixed counters for instructions, cycles and 215ref-cycles. Some special events have restrictions on which counter they 216can schedule, and may not support multiple instances in a single group. 217When too many events are specified in the group some of them will not 218be measured. 219 220Globally pinned events can limit the number of counters available for 221other groups. On x86 systems, the NMI watchdog pins a counter by default. 222The nmi watchdog can be disabled as root with 223 224 echo 0 > /proc/sys/kernel/nmi_watchdog 225 226Events from multiple different PMUs cannot be mixed in a group, with 227some exceptions for software events. 228 229LEADER SAMPLING 230--------------- 231 232perf also supports group leader sampling using the :S specifier. 233 234 perf record -e '{cycles,instructions}:S' ... 235 perf report --group 236 237Normally all events in a event group sample, but with :S only 238the first event (the leader) samples, and it only reads the values of the 239other events in the group. 240 241OPTIONS 242------- 243 244Without options all known events will be listed. 245 246To limit the list use: 247 248. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 249 250. 'sw' or 'software' to list software events such as context switches, etc. 251 252. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 253 254. 'tracepoint' to list all tracepoint events, alternatively use 255 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 256 block, etc. 257 258. 'pmu' to print the kernel supplied PMU events. 259 260. 'sdt' to list all Statically Defined Tracepoint events. 261 262. 'metric' to list metrics 263 264. 'metricgroup' to list metricgroups with metrics. 265 266. If none of the above is matched, it will apply the supplied glob to all 267 events, printing the ones that match. 268 269. As a last resort, it will do a substring search in all event names. 270 271One or more types can be used at the same time, listing the events for the 272types specified. 273 274Support raw format: 275 276. '--raw-dump', shows the raw-dump of all the events. 277. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 278 a certain kind of events. 279 280SEE ALSO 281-------- 282linkperf:perf-stat[1], linkperf:perf-top[1], 283linkperf:perf-record[1], 284http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 285http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] 286