1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [hw|sw|cache|tracepoint|pmu|event_glob]
12
13DESCRIPTION
14-----------
15This command displays the symbolic event types which can be selected in the
16various perf commands with the -e option.
17
18[[EVENT_MODIFIERS]]
19EVENT MODIFIERS
20---------------
21
22Events can optionally have a modifier by appending a colon and one or
23more modifiers. Modifiers allow the user to restrict the events to be
24counted. The following modifiers exist:
25
26 u - user-space counting
27 k - kernel counting
28 h - hypervisor counting
29 I - non idle counting
30 G - guest counting (in KVM guests)
31 H - host counting (not in KVM guests)
32 p - precise level
33 P - use maximum detected precise level
34 S - read sample value (PERF_SAMPLE_READ)
35 D - pin the event to the PMU
36
37The 'p' modifier can be used for specifying how precise the instruction
38address should be. The 'p' modifier can be specified multiple times:
39
40 0 - SAMPLE_IP can have arbitrary skid
41 1 - SAMPLE_IP must have constant skid
42 2 - SAMPLE_IP requested to have 0 skid
43 3 - SAMPLE_IP must have 0 skid
44
45For Intel systems precise event sampling is implemented with PEBS
46which supports up to precise-level 2.
47
48On AMD systems it is implemented using IBS (up to precise-level 2).
49The precise modifier works with event types 0x76 (cpu-cycles, CPU
50clocks not halted) and 0xC1 (micro-ops retired). Both events map to
51IBS execution sampling (IBS op) with the IBS Op Counter Control bit
52(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
53Manual Volume 2: System Programming, 13.3 Instruction-Based
54Sampling). Examples to use IBS:
55
56 perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
57 perf record -a -e r076:p ...          # same as -e cpu-cycles:p
58 perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
59
60RAW HARDWARE EVENT DESCRIPTOR
61-----------------------------
62Even when an event is not available in a symbolic form within perf right now,
63it can be encoded in a per processor specific way.
64
65For instance For x86 CPUs NNN represents the raw register encoding with the
66layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
67of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
68Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
69
70Note: Only the following bit fields can be set in x86 counter
71registers: event, umask, edge, inv, cmask. Esp. guest/host only and
72OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
73MODIFIERS>>.
74
75Example:
76
77If the Intel docs for a QM720 Core i7 describe an event as:
78
79  Event  Umask  Event Mask
80  Num.   Value  Mnemonic    Description                        Comment
81
82  A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
83                            delivered by loop stream detector  invert to count
84                                                               cycles
85
86raw encoding of 0x1A8 can be used:
87
88 perf stat -e r1a8 -a sleep 1
89 perf record -e r1a8 ...
90
91You should refer to the processor specific documentation for getting these
92details. Some of them are referenced in the SEE ALSO section below.
93
94PARAMETERIZED EVENTS
95--------------------
96
97Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
98example:
99
100  hv_gpci/dtbp_ptitc,phys_processor_idx=?/
101
102This means that when provided as an event, a value for '?' must
103also be supplied. For example:
104
105  perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
106
107OPTIONS
108-------
109
110Without options all known events will be listed.
111
112To limit the list use:
113
114. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
115
116. 'sw' or 'software' to list software events such as context switches, etc.
117
118. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
119
120. 'tracepoint' to list all tracepoint events, alternatively use
121  'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
122  block, etc.
123
124. 'pmu' to print the kernel supplied PMU events.
125
126. If none of the above is matched, it will apply the supplied glob to all
127  events, printing the ones that match.
128
129. As a last resort, it will do a substring search in all event names.
130
131One or more types can be used at the same time, listing the events for the
132types specified.
133
134Support raw format:
135
136. '--raw-dump', shows the raw-dump of all the events.
137. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
138  a certain kind of events.
139
140SEE ALSO
141--------
142linkperf:perf-stat[1], linkperf:perf-top[1],
143linkperf:perf-record[1],
144http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
145http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
146