1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [--no-desc] [--long-desc] 12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] 13 14DESCRIPTION 15----------- 16This command displays the symbolic event types which can be selected in the 17various perf commands with the -e option. 18 19OPTIONS 20------- 21-d:: 22--desc:: 23Print extra event descriptions. (default) 24 25--no-desc:: 26Don't print descriptions. 27 28-v:: 29--long-desc:: 30Print longer event descriptions. 31 32--debug:: 33Enable debugging output. 34 35--details:: 36Print how named events are resolved internally into perf events, and also 37any extra expressions computed by perf stat. 38 39--deprecated:: 40Print deprecated events. By default the deprecated events are hidden. 41 42--cputype:: 43Print events applying cpu with this type for hybrid platform 44(e.g. --cputype core or --cputype atom) 45 46[[EVENT_MODIFIERS]] 47EVENT MODIFIERS 48--------------- 49 50Events can optionally have a modifier by appending a colon and one or 51more modifiers. Modifiers allow the user to restrict the events to be 52counted. The following modifiers exist: 53 54 u - user-space counting 55 k - kernel counting 56 h - hypervisor counting 57 I - non idle counting 58 G - guest counting (in KVM guests) 59 H - host counting (not in KVM guests) 60 p - precise level 61 P - use maximum detected precise level 62 S - read sample value (PERF_SAMPLE_READ) 63 D - pin the event to the PMU 64 W - group is weak and will fallback to non-group if not schedulable, 65 e - group or event are exclusive and do not share the PMU 66 67The 'p' modifier can be used for specifying how precise the instruction 68address should be. The 'p' modifier can be specified multiple times: 69 70 0 - SAMPLE_IP can have arbitrary skid 71 1 - SAMPLE_IP must have constant skid 72 2 - SAMPLE_IP requested to have 0 skid 73 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 74 sample shadowing effects. 75 76For Intel systems precise event sampling is implemented with PEBS 77which supports up to precise-level 2, and precise level 3 for 78some special cases 79 80On AMD systems it is implemented using IBS (up to precise-level 2). 81The precise modifier works with event types 0x76 (cpu-cycles, CPU 82clocks not halted) and 0xC1 (micro-ops retired). Both events map to 83IBS execution sampling (IBS op) with the IBS Op Counter Control bit 84(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s 85Manual Volume 2: System Programming, 13.3 Instruction-Based 86Sampling). Examples to use IBS: 87 88 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 89 perf record -a -e r076:p ... # same as -e cpu-cycles:p 90 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 91 92RAW HARDWARE EVENT DESCRIPTOR 93----------------------------- 94Even when an event is not available in a symbolic form within perf right now, 95it can be encoded in a per processor specific way. 96 97For instance For x86 CPUs NNN represents the raw register encoding with the 98layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 99of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, 100Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 101 102Note: Only the following bit fields can be set in x86 counter 103registers: event, umask, edge, inv, cmask. Esp. guest/host only and 104OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 105MODIFIERS>>. 106 107Example: 108 109If the Intel docs for a QM720 Core i7 describe an event as: 110 111 Event Umask Event Mask 112 Num. Value Mnemonic Description Comment 113 114 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 115 delivered by loop stream detector invert to count 116 cycles 117 118raw encoding of 0x1A8 can be used: 119 120 perf stat -e r1a8 -a sleep 1 121 perf record -e r1a8 ... 122 123It's also possible to use pmu syntax: 124 125 perf record -e r1a8 -a sleep 1 126 perf record -e cpu/r1a8/ ... 127 perf record -e cpu/r0x1a8/ ... 128 129You should refer to the processor specific documentation for getting these 130details. Some of them are referenced in the SEE ALSO section below. 131 132ARBITRARY PMUS 133-------------- 134 135perf also supports an extended syntax for specifying raw parameters 136to PMUs. Using this typically requires looking up the specific event 137in the CPU vendor specific documentation. 138 139The available PMUs and their raw parameters can be listed with 140 141 ls /sys/devices/*/format 142 143For example the raw event "LSD.UOPS" core pmu event above could 144be specified as 145 146 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... 147 148 or using extended name syntax 149 150 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... 151 152PER SOCKET PMUS 153--------------- 154 155Some PMUs are not associated with a core, but with a whole CPU socket. 156Events on these PMUs generally cannot be sampled, but only counted globally 157with perf stat -a. They can be bound to one logical CPU, but will measure 158all the CPUs in the same socket. 159 160This example measures memory bandwidth every second 161on the first memory controller on socket 0 of a Intel Xeon system 162 163 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 164 165Each memory controller has its own PMU. Measuring the complete system 166bandwidth would require specifying all imc PMUs (see perf list output), 167and adding the values together. To simplify creation of multiple events, 168prefix and glob matching is supported in the PMU name, and the prefix 169'uncore_' is also ignored when performing the match. So the command above 170can be expanded to all memory controllers by using the syntaxes: 171 172 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... 173 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... 174 175This example measures the combined core power every second 176 177 perf stat -I 1000 -e power/energy-cores/ -a 178 179ACCESS RESTRICTIONS 180------------------- 181 182For non root users generally only context switched PMU events are available. 183This is normally only the events in the cpu PMU, the predefined events 184like cycles and instructions and some software events. 185 186Other PMUs and global measurements are normally root only. 187Some event qualifiers, such as "any", are also root only. 188 189This can be overridden by setting the kernel.perf_event_paranoid 190sysctl to -1, which allows non root to use these events. 191 192For accessing trace point events perf needs to have read access to 193/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed 194setting. 195 196TRACING 197------- 198 199Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 200that allows low overhead execution tracing. These are described in a separate 201intel-pt.txt document. 202 203PARAMETERIZED EVENTS 204-------------------- 205 206Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 207example: 208 209 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 210 211This means that when provided as an event, a value for '?' must 212also be supplied. For example: 213 214 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 215 216EVENT QUALIFIERS: 217 218It is also possible to add extra qualifiers to an event: 219 220percore: 221 222Sums up the event counts for all hardware threads in a core, e.g.: 223 224 225 perf stat -e cpu/event=0,umask=0x3,percore=1/ 226 227 228EVENT GROUPS 229------------ 230 231Perf supports time based multiplexing of events, when the number of events 232active exceeds the number of hardware performance counters. Multiplexing 233can cause measurement errors when the workload changes its execution 234profile. 235 236When metrics are computed using formulas from event counts, it is useful to 237ensure some events are always measured together as a group to minimize multiplexing 238errors. Event groups can be specified using { }. 239 240 perf stat -e '{instructions,cycles}' ... 241 242The number of available performance counters depend on the CPU. A group 243cannot contain more events than available counters. 244For example Intel Core CPUs typically have four generic performance counters 245for the core, plus three fixed counters for instructions, cycles and 246ref-cycles. Some special events have restrictions on which counter they 247can schedule, and may not support multiple instances in a single group. 248When too many events are specified in the group some of them will not 249be measured. 250 251Globally pinned events can limit the number of counters available for 252other groups. On x86 systems, the NMI watchdog pins a counter by default. 253The nmi watchdog can be disabled as root with 254 255 echo 0 > /proc/sys/kernel/nmi_watchdog 256 257Events from multiple different PMUs cannot be mixed in a group, with 258some exceptions for software events. 259 260LEADER SAMPLING 261--------------- 262 263perf also supports group leader sampling using the :S specifier. 264 265 perf record -e '{cycles,instructions}:S' ... 266 perf report --group 267 268Normally all events in an event group sample, but with :S only 269the first event (the leader) samples, and it only reads the values of the 270other events in the group. 271 272However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX 273area event must be the leader, so then the second event samples, not the first. 274 275OPTIONS 276------- 277 278Without options all known events will be listed. 279 280To limit the list use: 281 282. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 283 284. 'sw' or 'software' to list software events such as context switches, etc. 285 286. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 287 288. 'tracepoint' to list all tracepoint events, alternatively use 289 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 290 block, etc. 291 292. 'pmu' to print the kernel supplied PMU events. 293 294. 'sdt' to list all Statically Defined Tracepoint events. 295 296. 'metric' to list metrics 297 298. 'metricgroup' to list metricgroups with metrics. 299 300. If none of the above is matched, it will apply the supplied glob to all 301 events, printing the ones that match. 302 303. As a last resort, it will do a substring search in all event names. 304 305One or more types can be used at the same time, listing the events for the 306types specified. 307 308Support raw format: 309 310. '--raw-dump', shows the raw-dump of all the events. 311. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 312 a certain kind of events. 313 314SEE ALSO 315-------- 316linkperf:perf-stat[1], linkperf:perf-top[1], 317linkperf:perf-record[1], 318http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 319http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] 320