1perf-c2c(1)
2===========
3
4NAME
5----
6perf-c2c - Shared Data C2C/HITM Analyzer.
7
8SYNOPSIS
9--------
10[verse]
11'perf c2c record' [<options>] <command>
12'perf c2c record' [<options>] \-- [<record command options>] <command>
13'perf c2c report' [<options>]
14
15DESCRIPTION
16-----------
17C2C stands for Cache To Cache.
18
19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20you to track down the cacheline contentions.
21
22On Intel, the tool is based on load latency and precise store facility events
23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
25limitations, perf c2c is not supported on Zen3 cpus).
26
27These events provide:
28  - memory address of the access
29  - type of the access (load and store details)
30  - latency (in cycles) of the load access
31
32The c2c tool provide means to record this data and report back access details
33for cachelines with highest contention - highest number of HITM accesses.
34
35The basic workflow with this tool follows the standard record/report phase.
36User uses the record command to record events data and report command to
37display it.
38
39
40RECORD OPTIONS
41--------------
42-e::
43--event=::
44	Select the PMU event. Use 'perf c2c record -e list'
45	to list available events.
46
47-v::
48--verbose::
49	Be more verbose (show counter open errors, etc).
50
51-l::
52--ldlat::
53	Configure mem-loads latency. Supported on Intel and Arm64 processors
54	only. Ignored on other archs.
55
56-k::
57--all-kernel::
58	Configure all used events to run in kernel space.
59
60-u::
61--all-user::
62	Configure all used events to run in user space.
63
64REPORT OPTIONS
65--------------
66-k::
67--vmlinux=<file>::
68	vmlinux pathname
69
70-v::
71--verbose::
72	Be more verbose (show counter open errors, etc).
73
74-i::
75--input::
76	Specify the input file to process.
77
78-N::
79--node-info::
80	Show extra node info in report (see NODE INFO section)
81
82-c::
83--coalesce::
84	Specify sorting fields for single cacheline display.
85	Following fields are available: tid,pid,iaddr,dso
86	(see COALESCE)
87
88-g::
89--call-graph::
90	Setup callchains parameters.
91	Please refer to perf-report man page for details.
92
93--stdio::
94	Force the stdio output (see STDIO OUTPUT)
95
96--stats::
97	Display only statistic tables and force stdio mode.
98
99--full-symbols::
100	Display full length of symbols.
101
102--no-source::
103	Do not display Source:Line column.
104
105--show-all::
106	Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
107
108-f::
109--force::
110	Don't do ownership validation.
111
112-d::
113--display::
114	Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display
115	and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode
116	as default.
117
118--stitch-lbr::
119	Show callgraph with stitched LBRs, which may have more complete
120	callgraph. The perf.data file must have been obtained using
121	perf c2c record --call-graph lbr.
122	Disabled by default. In common cases with call stack overflows,
123	it can recreate better call stacks than the default lbr call stack
124	output. But this approach is not full proof. There can be cases
125	where it creates incorrect call stacks from incorrect matches.
126	The known limitations include exception handing such as
127	setjmp/longjmp will have calls/returns not match.
128
129C2C RECORD
130----------
131The perf c2c record command setup options related to HITM cacheline analysis
132and calls standard perf record command.
133
134Following perf record options are configured by default:
135(check perf record man page for details)
136
137  -W,-d,--phys-data,--sample-cpu
138
139Unless specified otherwise with '-e' option, following events are monitored by
140default on Intel:
141
142  cpu/mem-loads,ldlat=30/P
143  cpu/mem-stores/P
144
145following on AMD:
146
147  ibs_op//
148
149and following on PowerPC:
150
151  cpu/mem-loads/
152  cpu/mem-stores/
153
154User can pass any 'perf record' option behind '--' mark, like (to enable
155callchains and system wide monitoring):
156
157  $ perf c2c record -- -g -a
158
159Please check RECORD OPTIONS section for specific c2c record options.
160
161C2C REPORT
162----------
163The perf c2c report command displays shared data analysis.  It comes in two
164display modes: stdio and tui (default).
165
166The report command workflow is following:
167  - sort all the data based on the cacheline address
168  - store access details for each cacheline
169  - sort all cachelines based on user settings
170  - display data
171
172In general perf report output consist of 2 basic views:
173  1) most expensive cachelines list
174  2) offsets details for each cacheline
175
176For each cacheline in the 1) list we display following data:
177(Both stdio and TUI modes follow the same fields output)
178
179  Index
180  - zero based index to identify the cacheline
181
182  Cacheline
183  - cacheline address (hex number)
184
185  Rmt/Lcl Hitm (Display with HITM types)
186  - cacheline percentage of all Remote/Local HITM accesses
187
188  Peer Snoop (Display with peer type)
189  - cacheline percentage of all peer accesses
190
191  LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
192  - count of Total/Local/Remote load HITMs
193
194  Load Peer - Total, Local, Remote (For display with peer type)
195  - count of Total/Local/Remote load from peer cache or DRAM
196
197  Total records
198  - sum of all cachelines accesses
199
200  Total loads
201  - sum of all load accesses
202
203  Total stores
204  - sum of all store accesses
205
206  Store Reference - L1Hit, L1Miss, N/A
207    L1Hit - store accesses that hit L1
208    L1Miss - store accesses that missed L1
209    N/A - store accesses with memory level is not available
210
211  Core Load Hit - FB, L1, L2
212  - count of load hits in FB (Fill Buffer), L1 and L2 cache
213
214  LLC Load Hit - LlcHit, LclHitm
215  - count of LLC load accesses, includes LLC hits and LLC HITMs
216
217  RMT Load Hit - RmtHit, RmtHitm
218  - count of remote load accesses, includes remote hits and remote HITMs;
219    on Arm neoverse cores, RmtHit is used to account remote accesses,
220    includes remote DRAM or any upward cache level in remote node
221
222  Load Dram - Lcl, Rmt
223  - count of local and remote DRAM accesses
224
225For each offset in the 2) list we display following data:
226
227  HITM - Rmt, Lcl (Display with HITM types)
228  - % of Remote/Local HITM accesses for given offset within cacheline
229
230  Peer Snoop - Rmt, Lcl (Display with peer type)
231  - % of Remote/Local peer accesses for given offset within cacheline
232
233  Store Refs - L1 Hit, L1 Miss, N/A
234  - % of store accesses that hit L1, missed L1 and N/A (no available) memory
235    level for given offset within cacheline
236
237  Data address - Offset
238  - offset address
239
240  Pid
241  - pid of the process responsible for the accesses
242
243  Tid
244  - tid of the process responsible for the accesses
245
246  Code address
247  - code address responsible for the accesses
248
249  cycles - rmt hitm, lcl hitm, load (Display with HITM types)
250    - sum of cycles for given accesses - Remote/Local HITM and generic load
251
252  cycles - rmt peer, lcl peer, load (Display with peer type)
253    - sum of cycles for given accesses - Remote/Local peer load and generic load
254
255  cpu cnt
256    - number of cpus that participated on the access
257
258  Symbol
259    - code symbol related to the 'Code address' value
260
261  Shared Object
262    - shared object name related to the 'Code address' value
263
264  Source:Line
265    - source information related to the 'Code address' value
266
267  Node
268    - nodes participating on the access (see NODE INFO section)
269
270NODE INFO
271---------
272The 'Node' field displays nodes that accesses given cacheline
273offset. Its output comes in 3 flavors:
274  - node IDs separated by ','
275  - node IDs with stats for each ID, in following format:
276      Node{cpus %hitms %stores} (Display with HITM types)
277      Node{cpus %peers %stores} (Display with peer type)
278  - node IDs with list of affected CPUs in following format:
279      Node{cpu list}
280
281User can switch between above flavors with -N option or
282use 'n' key to interactively switch in TUI mode.
283
284COALESCE
285--------
286User can specify how to sort offsets for cacheline.
287
288Following fields are available and governs the final
289output fields set for cacheline offsets output:
290
291  tid   - coalesced by process TIDs
292  pid   - coalesced by process PIDs
293  iaddr - coalesced by code address, following fields are displayed:
294             Code address, Code symbol, Shared Object, Source line
295  dso   - coalesced by shared object
296
297By default the coalescing is setup with 'pid,iaddr'.
298
299STDIO OUTPUT
300------------
301The stdio output displays data on standard output.
302
303Following tables are displayed:
304  Trace Event Information
305  - overall statistics of memory accesses
306
307  Global Shared Cache Line Event Information
308  - overall statistics on shared cachelines
309
310  Shared Data Cache Line Table
311  - list of most expensive cachelines
312
313  Shared Cache Line Distribution Pareto
314  - list of all accessed offsets for each cacheline
315
316TUI OUTPUT
317----------
318The TUI output provides interactive interface to navigate
319through cachelines list and to display offset details.
320
321For details please refer to the help window by pressing '?' key.
322
323CREDITS
324-------
325Although Don Zickus, Dick Fowles and Joe Mario worked together
326to get this implemented, we got lots of early help from Arnaldo
327Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
328
329C2C BLOG
330--------
331Check Joe's blog on c2c tool for detailed use case explanation:
332  https://joemario.github.io/blog/2016/09/01/c2c-blog/
333
334SEE ALSO
335--------
336linkperf:perf-record[1], linkperf:perf-mem[1]
337