1perf-c2c(1)
2===========
3
4NAME
5----
6perf-c2c - Shared Data C2C/HITM Analyzer.
7
8SYNOPSIS
9--------
10[verse]
11'perf c2c record' [<options>] <command>
12'perf c2c record' [<options>] \-- [<record command options>] <command>
13'perf c2c report' [<options>]
14
15DESCRIPTION
16-----------
17C2C stands for Cache To Cache.
18
19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20you to track down the cacheline contentions.
21
22On x86, the tool is based on load latency and precise store facility events
23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24with thresholding feature.
25
26These events provide:
27  - memory address of the access
28  - type of the access (load and store details)
29  - latency (in cycles) of the load access
30
31The c2c tool provide means to record this data and report back access details
32for cachelines with highest contention - highest number of HITM accesses.
33
34The basic workflow with this tool follows the standard record/report phase.
35User uses the record command to record events data and report command to
36display it.
37
38
39RECORD OPTIONS
40--------------
41-e::
42--event=::
43	Select the PMU event. Use 'perf c2c record -e list'
44	to list available events.
45
46-v::
47--verbose::
48	Be more verbose (show counter open errors, etc).
49
50-l::
51--ldlat::
52	Configure mem-loads latency. (x86 only)
53
54-k::
55--all-kernel::
56	Configure all used events to run in kernel space.
57
58-u::
59--all-user::
60	Configure all used events to run in user space.
61
62REPORT OPTIONS
63--------------
64-k::
65--vmlinux=<file>::
66	vmlinux pathname
67
68-v::
69--verbose::
70	Be more verbose (show counter open errors, etc).
71
72-i::
73--input::
74	Specify the input file to process.
75
76-N::
77--node-info::
78	Show extra node info in report (see NODE INFO section)
79
80-c::
81--coalesce::
82	Specify sorting fields for single cacheline display.
83	Following fields are available: tid,pid,iaddr,dso
84	(see COALESCE)
85
86-g::
87--call-graph::
88	Setup callchains parameters.
89	Please refer to perf-report man page for details.
90
91--stdio::
92	Force the stdio output (see STDIO OUTPUT)
93
94--stats::
95	Display only statistic tables and force stdio mode.
96
97--full-symbols::
98	Display full length of symbols.
99
100--no-source::
101	Do not display Source:Line column.
102
103--show-all::
104	Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
105
106-f::
107--force::
108	Don't do ownership validation.
109
110-d::
111--display::
112	Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display
113	and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode
114	as default.
115
116--stitch-lbr::
117	Show callgraph with stitched LBRs, which may have more complete
118	callgraph. The perf.data file must have been obtained using
119	perf c2c record --call-graph lbr.
120	Disabled by default. In common cases with call stack overflows,
121	it can recreate better call stacks than the default lbr call stack
122	output. But this approach is not full proof. There can be cases
123	where it creates incorrect call stacks from incorrect matches.
124	The known limitations include exception handing such as
125	setjmp/longjmp will have calls/returns not match.
126
127C2C RECORD
128----------
129The perf c2c record command setup options related to HITM cacheline analysis
130and calls standard perf record command.
131
132Following perf record options are configured by default:
133(check perf record man page for details)
134
135  -W,-d,--phys-data,--sample-cpu
136
137Unless specified otherwise with '-e' option, following events are monitored by
138default on x86:
139
140  cpu/mem-loads,ldlat=30/P
141  cpu/mem-stores/P
142
143and following on PowerPC:
144
145  cpu/mem-loads/
146  cpu/mem-stores/
147
148User can pass any 'perf record' option behind '--' mark, like (to enable
149callchains and system wide monitoring):
150
151  $ perf c2c record -- -g -a
152
153Please check RECORD OPTIONS section for specific c2c record options.
154
155C2C REPORT
156----------
157The perf c2c report command displays shared data analysis.  It comes in two
158display modes: stdio and tui (default).
159
160The report command workflow is following:
161  - sort all the data based on the cacheline address
162  - store access details for each cacheline
163  - sort all cachelines based on user settings
164  - display data
165
166In general perf report output consist of 2 basic views:
167  1) most expensive cachelines list
168  2) offsets details for each cacheline
169
170For each cacheline in the 1) list we display following data:
171(Both stdio and TUI modes follow the same fields output)
172
173  Index
174  - zero based index to identify the cacheline
175
176  Cacheline
177  - cacheline address (hex number)
178
179  Rmt/Lcl Hitm (Display with HITM types)
180  - cacheline percentage of all Remote/Local HITM accesses
181
182  Peer Snoop (Display with peer type)
183  - cacheline percentage of all peer accesses
184
185  LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
186  - count of Total/Local/Remote load HITMs
187
188  Load Peer - Total, Local, Remote (For display with peer type)
189  - count of Total/Local/Remote load from peer cache or DRAM
190
191  Total records
192  - sum of all cachelines accesses
193
194  Total loads
195  - sum of all load accesses
196
197  Total stores
198  - sum of all store accesses
199
200  Store Reference - L1Hit, L1Miss, N/A
201    L1Hit - store accesses that hit L1
202    L1Miss - store accesses that missed L1
203    N/A - store accesses with memory level is not available
204
205  Core Load Hit - FB, L1, L2
206  - count of load hits in FB (Fill Buffer), L1 and L2 cache
207
208  LLC Load Hit - LlcHit, LclHitm
209  - count of LLC load accesses, includes LLC hits and LLC HITMs
210
211  RMT Load Hit - RmtHit, RmtHitm
212  - count of remote load accesses, includes remote hits and remote HITMs;
213    on Arm neoverse cores, RmtHit is used to account remote accesses,
214    includes remote DRAM or any upward cache level in remote node
215
216  Load Dram - Lcl, Rmt
217  - count of local and remote DRAM accesses
218
219For each offset in the 2) list we display following data:
220
221  HITM - Rmt, Lcl (Display with HITM types)
222  - % of Remote/Local HITM accesses for given offset within cacheline
223
224  Peer Snoop - Rmt, Lcl (Display with peer type)
225  - % of Remote/Local peer accesses for given offset within cacheline
226
227  Store Refs - L1 Hit, L1 Miss, N/A
228  - % of store accesses that hit L1, missed L1 and N/A (no available) memory
229    level for given offset within cacheline
230
231  Data address - Offset
232  - offset address
233
234  Pid
235  - pid of the process responsible for the accesses
236
237  Tid
238  - tid of the process responsible for the accesses
239
240  Code address
241  - code address responsible for the accesses
242
243  cycles - rmt hitm, lcl hitm, load (Display with HITM types)
244    - sum of cycles for given accesses - Remote/Local HITM and generic load
245
246  cycles - rmt peer, lcl peer, load (Display with peer type)
247    - sum of cycles for given accesses - Remote/Local peer load and generic load
248
249  cpu cnt
250    - number of cpus that participated on the access
251
252  Symbol
253    - code symbol related to the 'Code address' value
254
255  Shared Object
256    - shared object name related to the 'Code address' value
257
258  Source:Line
259    - source information related to the 'Code address' value
260
261  Node
262    - nodes participating on the access (see NODE INFO section)
263
264NODE INFO
265---------
266The 'Node' field displays nodes that accesses given cacheline
267offset. Its output comes in 3 flavors:
268  - node IDs separated by ','
269  - node IDs with stats for each ID, in following format:
270      Node{cpus %hitms %stores} (Display with HITM types)
271      Node{cpus %peers %stores} (Display with peer type)
272  - node IDs with list of affected CPUs in following format:
273      Node{cpu list}
274
275User can switch between above flavors with -N option or
276use 'n' key to interactively switch in TUI mode.
277
278COALESCE
279--------
280User can specify how to sort offsets for cacheline.
281
282Following fields are available and governs the final
283output fields set for cacheline offsets output:
284
285  tid   - coalesced by process TIDs
286  pid   - coalesced by process PIDs
287  iaddr - coalesced by code address, following fields are displayed:
288             Code address, Code symbol, Shared Object, Source line
289  dso   - coalesced by shared object
290
291By default the coalescing is setup with 'pid,iaddr'.
292
293STDIO OUTPUT
294------------
295The stdio output displays data on standard output.
296
297Following tables are displayed:
298  Trace Event Information
299  - overall statistics of memory accesses
300
301  Global Shared Cache Line Event Information
302  - overall statistics on shared cachelines
303
304  Shared Data Cache Line Table
305  - list of most expensive cachelines
306
307  Shared Cache Line Distribution Pareto
308  - list of all accessed offsets for each cacheline
309
310TUI OUTPUT
311----------
312The TUI output provides interactive interface to navigate
313through cachelines list and to display offset details.
314
315For details please refer to the help window by pressing '?' key.
316
317CREDITS
318-------
319Although Don Zickus, Dick Fowles and Joe Mario worked together
320to get this implemented, we got lots of early help from Arnaldo
321Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
322
323C2C BLOG
324--------
325Check Joe's blog on c2c tool for detailed use case explanation:
326  https://joemario.github.io/blog/2016/09/01/c2c-blog/
327
328SEE ALSO
329--------
330linkperf:perf-record[1], linkperf:perf-mem[1]
331