171b7ff5eSAndrea ParriC LB+fencembonceonce+ctrlonceonce 271b7ff5eSAndrea Parri 371b7ff5eSAndrea Parri(* 471b7ff5eSAndrea Parri * Result: Never 571b7ff5eSAndrea Parri * 671b7ff5eSAndrea Parri * This litmus test demonstrates that lightweight ordering suffices for 771b7ff5eSAndrea Parri * the load-buffering pattern, in other words, preventing all processes 871b7ff5eSAndrea Parri * reading from the preceding process's write. In this example, the 971b7ff5eSAndrea Parri * combination of a control dependency and a full memory barrier are enough 1071b7ff5eSAndrea Parri * to do the trick. (But the full memory barrier could be replaced with 1171b7ff5eSAndrea Parri * another control dependency and order would still be maintained.) 1271b7ff5eSAndrea Parri *) 1371b7ff5eSAndrea Parri 14*5c587f9bSAkira Yokosawa{} 1571b7ff5eSAndrea Parri 1671b7ff5eSAndrea ParriP0(int *x, int *y) 1771b7ff5eSAndrea Parri{ 1871b7ff5eSAndrea Parri int r0; 1971b7ff5eSAndrea Parri 2071b7ff5eSAndrea Parri r0 = READ_ONCE(*x); 2171b7ff5eSAndrea Parri if (r0) 2271b7ff5eSAndrea Parri WRITE_ONCE(*y, 1); 2371b7ff5eSAndrea Parri} 2471b7ff5eSAndrea Parri 2571b7ff5eSAndrea ParriP1(int *x, int *y) 2671b7ff5eSAndrea Parri{ 2771b7ff5eSAndrea Parri int r0; 2871b7ff5eSAndrea Parri 2971b7ff5eSAndrea Parri r0 = READ_ONCE(*y); 3071b7ff5eSAndrea Parri smp_mb(); 3171b7ff5eSAndrea Parri WRITE_ONCE(*x, 1); 3271b7ff5eSAndrea Parri} 3371b7ff5eSAndrea Parri 3471b7ff5eSAndrea Parriexists (0:r0=1 /\ 1:r0=1) 35