1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 /* Please note that modifications to all structs defined here are 37 * subject to backwards-compatibility constraints. 38 */ 39 40 /** 41 * DOC: uevents generated by i915 on it's device node 42 * 43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44 * event from the gpu l3 cache. Additional information supplied is ROW, 45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46 * track of these events and if a specific cache-line seems to have a 47 * persistent error remap it with the l3 remapping tool supplied in 48 * intel-gpu-tools. The value supplied with the event is always 1. 49 * 50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51 * hangcheck. The error detection event is a good indicator of when things 52 * began to go badly. The value supplied with the event is a 1 upon error 53 * detection, and a 0 upon reset completion, signifying no more error 54 * exists. NOTE: Disabling hangcheck or reset via module parameter will 55 * cause the related events to not be seen. 56 * 57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58 * the GPU. The value supplied with the event is always 1. NOTE: Disable 59 * reset via module parameter will cause this event to not be seen. 60 */ 61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62 #define I915_ERROR_UEVENT "ERROR" 63 #define I915_RESET_UEVENT "RESET" 64 65 /* 66 * i915_user_extension: Base class for defining a chain of extensions 67 * 68 * Many interfaces need to grow over time. In most cases we can simply 69 * extend the struct and have userspace pass in more data. Another option, 70 * as demonstrated by Vulkan's approach to providing extensions for forward 71 * and backward compatibility, is to use a list of optional structs to 72 * provide those extra details. 73 * 74 * The key advantage to using an extension chain is that it allows us to 75 * redefine the interface more easily than an ever growing struct of 76 * increasing complexity, and for large parts of that interface to be 77 * entirely optional. The downside is more pointer chasing; chasing across 78 * the __user boundary with pointers encapsulated inside u64. 79 */ 80 struct i915_user_extension { 81 __u64 next_extension; 82 __u32 name; 83 __u32 flags; /* All undefined bits must be zero. */ 84 __u32 rsvd[4]; /* Reserved for future use; must be zero. */ 85 }; 86 87 /* 88 * MOCS indexes used for GPU surfaces, defining the cacheability of the 89 * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 90 */ 91 enum i915_mocs_table_index { 92 /* 93 * Not cached anywhere, coherency between CPU and GPU accesses is 94 * guaranteed. 95 */ 96 I915_MOCS_UNCACHED, 97 /* 98 * Cacheability and coherency controlled by the kernel automatically 99 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 100 * usage of the surface (used for display scanout or not). 101 */ 102 I915_MOCS_PTE, 103 /* 104 * Cached in all GPU caches available on the platform. 105 * Coherency between CPU and GPU accesses to the surface is not 106 * guaranteed without extra synchronization. 107 */ 108 I915_MOCS_CACHED, 109 }; 110 111 /* 112 * Different engines serve different roles, and there may be more than one 113 * engine serving each role. enum drm_i915_gem_engine_class provides a 114 * classification of the role of the engine, which may be used when requesting 115 * operations to be performed on a certain subset of engines, or for providing 116 * information about that group. 117 */ 118 enum drm_i915_gem_engine_class { 119 I915_ENGINE_CLASS_RENDER = 0, 120 I915_ENGINE_CLASS_COPY = 1, 121 I915_ENGINE_CLASS_VIDEO = 2, 122 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 123 124 /* should be kept compact */ 125 126 I915_ENGINE_CLASS_INVALID = -1 127 }; 128 129 /* 130 * There may be more than one engine fulfilling any role within the system. 131 * Each engine of a class is given a unique instance number and therefore 132 * any engine can be specified by its class:instance tuplet. APIs that allow 133 * access to any engine in the system will use struct i915_engine_class_instance 134 * for this identification. 135 */ 136 struct i915_engine_class_instance { 137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */ 138 __u16 engine_instance; 139 #define I915_ENGINE_CLASS_INVALID_NONE -1 140 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 141 }; 142 143 /** 144 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 145 * 146 */ 147 148 enum drm_i915_pmu_engine_sample { 149 I915_SAMPLE_BUSY = 0, 150 I915_SAMPLE_WAIT = 1, 151 I915_SAMPLE_SEMA = 2 152 }; 153 154 #define I915_PMU_SAMPLE_BITS (4) 155 #define I915_PMU_SAMPLE_MASK (0xf) 156 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 157 #define I915_PMU_CLASS_SHIFT \ 158 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 159 160 #define __I915_PMU_ENGINE(class, instance, sample) \ 161 ((class) << I915_PMU_CLASS_SHIFT | \ 162 (instance) << I915_PMU_SAMPLE_BITS | \ 163 (sample)) 164 165 #define I915_PMU_ENGINE_BUSY(class, instance) \ 166 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 167 168 #define I915_PMU_ENGINE_WAIT(class, instance) \ 169 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 170 171 #define I915_PMU_ENGINE_SEMA(class, instance) \ 172 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 173 174 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 175 176 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 177 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 178 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 179 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 180 181 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 182 183 /* Each region is a minimum of 16k, and there are at most 255 of them. 184 */ 185 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 186 * of chars for next/prev indices */ 187 #define I915_LOG_MIN_TEX_REGION_SIZE 14 188 189 typedef struct _drm_i915_init { 190 enum { 191 I915_INIT_DMA = 0x01, 192 I915_CLEANUP_DMA = 0x02, 193 I915_RESUME_DMA = 0x03 194 } func; 195 unsigned int mmio_offset; 196 int sarea_priv_offset; 197 unsigned int ring_start; 198 unsigned int ring_end; 199 unsigned int ring_size; 200 unsigned int front_offset; 201 unsigned int back_offset; 202 unsigned int depth_offset; 203 unsigned int w; 204 unsigned int h; 205 unsigned int pitch; 206 unsigned int pitch_bits; 207 unsigned int back_pitch; 208 unsigned int depth_pitch; 209 unsigned int cpp; 210 unsigned int chipset; 211 } drm_i915_init_t; 212 213 typedef struct _drm_i915_sarea { 214 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 215 int last_upload; /* last time texture was uploaded */ 216 int last_enqueue; /* last time a buffer was enqueued */ 217 int last_dispatch; /* age of the most recently dispatched buffer */ 218 int ctxOwner; /* last context to upload state */ 219 int texAge; 220 int pf_enabled; /* is pageflipping allowed? */ 221 int pf_active; 222 int pf_current_page; /* which buffer is being displayed? */ 223 int perf_boxes; /* performance boxes to be displayed */ 224 int width, height; /* screen size in pixels */ 225 226 drm_handle_t front_handle; 227 int front_offset; 228 int front_size; 229 230 drm_handle_t back_handle; 231 int back_offset; 232 int back_size; 233 234 drm_handle_t depth_handle; 235 int depth_offset; 236 int depth_size; 237 238 drm_handle_t tex_handle; 239 int tex_offset; 240 int tex_size; 241 int log_tex_granularity; 242 int pitch; 243 int rotation; /* 0, 90, 180 or 270 */ 244 int rotated_offset; 245 int rotated_size; 246 int rotated_pitch; 247 int virtualX, virtualY; 248 249 unsigned int front_tiled; 250 unsigned int back_tiled; 251 unsigned int depth_tiled; 252 unsigned int rotated_tiled; 253 unsigned int rotated2_tiled; 254 255 int pipeA_x; 256 int pipeA_y; 257 int pipeA_w; 258 int pipeA_h; 259 int pipeB_x; 260 int pipeB_y; 261 int pipeB_w; 262 int pipeB_h; 263 264 /* fill out some space for old userspace triple buffer */ 265 drm_handle_t unused_handle; 266 __u32 unused1, unused2, unused3; 267 268 /* buffer object handles for static buffers. May change 269 * over the lifetime of the client. 270 */ 271 __u32 front_bo_handle; 272 __u32 back_bo_handle; 273 __u32 unused_bo_handle; 274 __u32 depth_bo_handle; 275 276 } drm_i915_sarea_t; 277 278 /* due to userspace building against these headers we need some compat here */ 279 #define planeA_x pipeA_x 280 #define planeA_y pipeA_y 281 #define planeA_w pipeA_w 282 #define planeA_h pipeA_h 283 #define planeB_x pipeB_x 284 #define planeB_y pipeB_y 285 #define planeB_w pipeB_w 286 #define planeB_h pipeB_h 287 288 /* Flags for perf_boxes 289 */ 290 #define I915_BOX_RING_EMPTY 0x1 291 #define I915_BOX_FLIP 0x2 292 #define I915_BOX_WAIT 0x4 293 #define I915_BOX_TEXTURE_LOAD 0x8 294 #define I915_BOX_LOST_CONTEXT 0x10 295 296 /* 297 * i915 specific ioctls. 298 * 299 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 300 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 301 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 302 */ 303 #define DRM_I915_INIT 0x00 304 #define DRM_I915_FLUSH 0x01 305 #define DRM_I915_FLIP 0x02 306 #define DRM_I915_BATCHBUFFER 0x03 307 #define DRM_I915_IRQ_EMIT 0x04 308 #define DRM_I915_IRQ_WAIT 0x05 309 #define DRM_I915_GETPARAM 0x06 310 #define DRM_I915_SETPARAM 0x07 311 #define DRM_I915_ALLOC 0x08 312 #define DRM_I915_FREE 0x09 313 #define DRM_I915_INIT_HEAP 0x0a 314 #define DRM_I915_CMDBUFFER 0x0b 315 #define DRM_I915_DESTROY_HEAP 0x0c 316 #define DRM_I915_SET_VBLANK_PIPE 0x0d 317 #define DRM_I915_GET_VBLANK_PIPE 0x0e 318 #define DRM_I915_VBLANK_SWAP 0x0f 319 #define DRM_I915_HWS_ADDR 0x11 320 #define DRM_I915_GEM_INIT 0x13 321 #define DRM_I915_GEM_EXECBUFFER 0x14 322 #define DRM_I915_GEM_PIN 0x15 323 #define DRM_I915_GEM_UNPIN 0x16 324 #define DRM_I915_GEM_BUSY 0x17 325 #define DRM_I915_GEM_THROTTLE 0x18 326 #define DRM_I915_GEM_ENTERVT 0x19 327 #define DRM_I915_GEM_LEAVEVT 0x1a 328 #define DRM_I915_GEM_CREATE 0x1b 329 #define DRM_I915_GEM_PREAD 0x1c 330 #define DRM_I915_GEM_PWRITE 0x1d 331 #define DRM_I915_GEM_MMAP 0x1e 332 #define DRM_I915_GEM_SET_DOMAIN 0x1f 333 #define DRM_I915_GEM_SW_FINISH 0x20 334 #define DRM_I915_GEM_SET_TILING 0x21 335 #define DRM_I915_GEM_GET_TILING 0x22 336 #define DRM_I915_GEM_GET_APERTURE 0x23 337 #define DRM_I915_GEM_MMAP_GTT 0x24 338 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 339 #define DRM_I915_GEM_MADVISE 0x26 340 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 341 #define DRM_I915_OVERLAY_ATTRS 0x28 342 #define DRM_I915_GEM_EXECBUFFER2 0x29 343 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 344 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 345 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 346 #define DRM_I915_GEM_WAIT 0x2c 347 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 348 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 349 #define DRM_I915_GEM_SET_CACHING 0x2f 350 #define DRM_I915_GEM_GET_CACHING 0x30 351 #define DRM_I915_REG_READ 0x31 352 #define DRM_I915_GET_RESET_STATS 0x32 353 #define DRM_I915_GEM_USERPTR 0x33 354 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 355 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 356 #define DRM_I915_PERF_OPEN 0x36 357 #define DRM_I915_PERF_ADD_CONFIG 0x37 358 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 359 #define DRM_I915_QUERY 0x39 360 #define DRM_I915_GEM_VM_CREATE 0x3a 361 #define DRM_I915_GEM_VM_DESTROY 0x3b 362 /* Must be kept compact -- no holes */ 363 364 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 365 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 366 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 367 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 368 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 369 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 370 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 371 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 372 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 373 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 374 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 375 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 376 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 377 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 378 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 379 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 380 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 381 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 382 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 383 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 384 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 385 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 386 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 387 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 388 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 389 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 390 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 391 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 392 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 393 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 394 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 395 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 396 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 397 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 398 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 399 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 400 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 401 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 402 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 403 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 404 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 405 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 406 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 407 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 408 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 409 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 410 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 411 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 412 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 413 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 414 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 415 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 416 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 417 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 418 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 419 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 420 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 421 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 422 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 423 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 424 425 /* Allow drivers to submit batchbuffers directly to hardware, relying 426 * on the security mechanisms provided by hardware. 427 */ 428 typedef struct drm_i915_batchbuffer { 429 int start; /* agp offset */ 430 int used; /* nr bytes in use */ 431 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 432 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 433 int num_cliprects; /* mulitpass with multiple cliprects? */ 434 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 435 } drm_i915_batchbuffer_t; 436 437 /* As above, but pass a pointer to userspace buffer which can be 438 * validated by the kernel prior to sending to hardware. 439 */ 440 typedef struct _drm_i915_cmdbuffer { 441 char __user *buf; /* pointer to userspace command buffer */ 442 int sz; /* nr bytes in buf */ 443 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 444 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 445 int num_cliprects; /* mulitpass with multiple cliprects? */ 446 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 447 } drm_i915_cmdbuffer_t; 448 449 /* Userspace can request & wait on irq's: 450 */ 451 typedef struct drm_i915_irq_emit { 452 int __user *irq_seq; 453 } drm_i915_irq_emit_t; 454 455 typedef struct drm_i915_irq_wait { 456 int irq_seq; 457 } drm_i915_irq_wait_t; 458 459 /* 460 * Different modes of per-process Graphics Translation Table, 461 * see I915_PARAM_HAS_ALIASING_PPGTT 462 */ 463 #define I915_GEM_PPGTT_NONE 0 464 #define I915_GEM_PPGTT_ALIASING 1 465 #define I915_GEM_PPGTT_FULL 2 466 467 /* Ioctl to query kernel params: 468 */ 469 #define I915_PARAM_IRQ_ACTIVE 1 470 #define I915_PARAM_ALLOW_BATCHBUFFER 2 471 #define I915_PARAM_LAST_DISPATCH 3 472 #define I915_PARAM_CHIPSET_ID 4 473 #define I915_PARAM_HAS_GEM 5 474 #define I915_PARAM_NUM_FENCES_AVAIL 6 475 #define I915_PARAM_HAS_OVERLAY 7 476 #define I915_PARAM_HAS_PAGEFLIPPING 8 477 #define I915_PARAM_HAS_EXECBUF2 9 478 #define I915_PARAM_HAS_BSD 10 479 #define I915_PARAM_HAS_BLT 11 480 #define I915_PARAM_HAS_RELAXED_FENCING 12 481 #define I915_PARAM_HAS_COHERENT_RINGS 13 482 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 483 #define I915_PARAM_HAS_RELAXED_DELTA 15 484 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 485 #define I915_PARAM_HAS_LLC 17 486 #define I915_PARAM_HAS_ALIASING_PPGTT 18 487 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 488 #define I915_PARAM_HAS_SEMAPHORES 20 489 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 490 #define I915_PARAM_HAS_VEBOX 22 491 #define I915_PARAM_HAS_SECURE_BATCHES 23 492 #define I915_PARAM_HAS_PINNED_BATCHES 24 493 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 494 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 495 #define I915_PARAM_HAS_WT 27 496 #define I915_PARAM_CMD_PARSER_VERSION 28 497 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 498 #define I915_PARAM_MMAP_VERSION 30 499 #define I915_PARAM_HAS_BSD2 31 500 #define I915_PARAM_REVISION 32 501 #define I915_PARAM_SUBSLICE_TOTAL 33 502 #define I915_PARAM_EU_TOTAL 34 503 #define I915_PARAM_HAS_GPU_RESET 35 504 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 505 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 506 #define I915_PARAM_HAS_POOLED_EU 38 507 #define I915_PARAM_MIN_EU_IN_POOL 39 508 #define I915_PARAM_MMAP_GTT_VERSION 40 509 510 /* 511 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 512 * priorities and the driver will attempt to execute batches in priority order. 513 * The param returns a capability bitmask, nonzero implies that the scheduler 514 * is enabled, with different features present according to the mask. 515 * 516 * The initial priority for each batch is supplied by the context and is 517 * controlled via I915_CONTEXT_PARAM_PRIORITY. 518 */ 519 #define I915_PARAM_HAS_SCHEDULER 41 520 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 521 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 522 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 523 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 524 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 525 526 #define I915_PARAM_HUC_STATUS 42 527 528 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 529 * synchronisation with implicit fencing on individual objects. 530 * See EXEC_OBJECT_ASYNC. 531 */ 532 #define I915_PARAM_HAS_EXEC_ASYNC 43 533 534 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 535 * both being able to pass in a sync_file fd to wait upon before executing, 536 * and being able to return a new sync_file fd that is signaled when the 537 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 538 */ 539 #define I915_PARAM_HAS_EXEC_FENCE 44 540 541 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 542 * user specified bufffers for post-mortem debugging of GPU hangs. See 543 * EXEC_OBJECT_CAPTURE. 544 */ 545 #define I915_PARAM_HAS_EXEC_CAPTURE 45 546 547 #define I915_PARAM_SLICE_MASK 46 548 549 /* Assuming it's uniform for each slice, this queries the mask of subslices 550 * per-slice for this system. 551 */ 552 #define I915_PARAM_SUBSLICE_MASK 47 553 554 /* 555 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 556 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 557 */ 558 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 559 560 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 561 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 562 */ 563 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 564 565 /* 566 * Query whether every context (both per-file default and user created) is 567 * isolated (insofar as HW supports). If this parameter is not true, then 568 * freshly created contexts may inherit values from an existing context, 569 * rather than default HW values. If true, it also ensures (insofar as HW 570 * supports) that all state set by this context will not leak to any other 571 * context. 572 * 573 * As not every engine across every gen support contexts, the returned 574 * value reports the support of context isolation for individual engines by 575 * returning a bitmask of each engine class set to true if that class supports 576 * isolation. 577 */ 578 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 579 580 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 581 * registers. This used to be fixed per platform but from CNL onwards, this 582 * might vary depending on the parts. 583 */ 584 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 585 586 /* 587 * Once upon a time we supposed that writes through the GGTT would be 588 * immediately in physical memory (once flushed out of the CPU path). However, 589 * on a few different processors and chipsets, this is not necessarily the case 590 * as the writes appear to be buffered internally. Thus a read of the backing 591 * storage (physical memory) via a different path (with different physical tags 592 * to the indirect write via the GGTT) will see stale values from before 593 * the GGTT write. Inside the kernel, we can for the most part keep track of 594 * the different read/write domains in use (e.g. set-domain), but the assumption 595 * of coherency is baked into the ABI, hence reporting its true state in this 596 * parameter. 597 * 598 * Reports true when writes via mmap_gtt are immediately visible following an 599 * lfence to flush the WCB. 600 * 601 * Reports false when writes via mmap_gtt are indeterminately delayed in an in 602 * internal buffer and are _not_ immediately visible to third parties accessing 603 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC 604 * communications channel when reporting false is strongly disadvised. 605 */ 606 #define I915_PARAM_MMAP_GTT_COHERENT 52 607 608 /* 609 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel 610 * execution through use of explicit fence support. 611 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. 612 */ 613 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 614 /* Must be kept compact -- no holes and well documented */ 615 616 typedef struct drm_i915_getparam { 617 __s32 param; 618 /* 619 * WARNING: Using pointers instead of fixed-size u64 means we need to write 620 * compat32 code. Don't repeat this mistake. 621 */ 622 int __user *value; 623 } drm_i915_getparam_t; 624 625 /* Ioctl to set kernel params: 626 */ 627 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 628 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 629 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 630 #define I915_SETPARAM_NUM_USED_FENCES 4 631 /* Must be kept compact -- no holes */ 632 633 typedef struct drm_i915_setparam { 634 int param; 635 int value; 636 } drm_i915_setparam_t; 637 638 /* A memory manager for regions of shared memory: 639 */ 640 #define I915_MEM_REGION_AGP 1 641 642 typedef struct drm_i915_mem_alloc { 643 int region; 644 int alignment; 645 int size; 646 int __user *region_offset; /* offset from start of fb or agp */ 647 } drm_i915_mem_alloc_t; 648 649 typedef struct drm_i915_mem_free { 650 int region; 651 int region_offset; 652 } drm_i915_mem_free_t; 653 654 typedef struct drm_i915_mem_init_heap { 655 int region; 656 int size; 657 int start; 658 } drm_i915_mem_init_heap_t; 659 660 /* Allow memory manager to be torn down and re-initialized (eg on 661 * rotate): 662 */ 663 typedef struct drm_i915_mem_destroy_heap { 664 int region; 665 } drm_i915_mem_destroy_heap_t; 666 667 /* Allow X server to configure which pipes to monitor for vblank signals 668 */ 669 #define DRM_I915_VBLANK_PIPE_A 1 670 #define DRM_I915_VBLANK_PIPE_B 2 671 672 typedef struct drm_i915_vblank_pipe { 673 int pipe; 674 } drm_i915_vblank_pipe_t; 675 676 /* Schedule buffer swap at given vertical blank: 677 */ 678 typedef struct drm_i915_vblank_swap { 679 drm_drawable_t drawable; 680 enum drm_vblank_seq_type seqtype; 681 unsigned int sequence; 682 } drm_i915_vblank_swap_t; 683 684 typedef struct drm_i915_hws_addr { 685 __u64 addr; 686 } drm_i915_hws_addr_t; 687 688 struct drm_i915_gem_init { 689 /** 690 * Beginning offset in the GTT to be managed by the DRM memory 691 * manager. 692 */ 693 __u64 gtt_start; 694 /** 695 * Ending offset in the GTT to be managed by the DRM memory 696 * manager. 697 */ 698 __u64 gtt_end; 699 }; 700 701 struct drm_i915_gem_create { 702 /** 703 * Requested size for the object. 704 * 705 * The (page-aligned) allocated size for the object will be returned. 706 */ 707 __u64 size; 708 /** 709 * Returned handle for the object. 710 * 711 * Object handles are nonzero. 712 */ 713 __u32 handle; 714 __u32 pad; 715 }; 716 717 struct drm_i915_gem_pread { 718 /** Handle for the object being read. */ 719 __u32 handle; 720 __u32 pad; 721 /** Offset into the object to read from */ 722 __u64 offset; 723 /** Length of data to read */ 724 __u64 size; 725 /** 726 * Pointer to write the data into. 727 * 728 * This is a fixed-size type for 32/64 compatibility. 729 */ 730 __u64 data_ptr; 731 }; 732 733 struct drm_i915_gem_pwrite { 734 /** Handle for the object being written to. */ 735 __u32 handle; 736 __u32 pad; 737 /** Offset into the object to write to */ 738 __u64 offset; 739 /** Length of data to write */ 740 __u64 size; 741 /** 742 * Pointer to read the data from. 743 * 744 * This is a fixed-size type for 32/64 compatibility. 745 */ 746 __u64 data_ptr; 747 }; 748 749 struct drm_i915_gem_mmap { 750 /** Handle for the object being mapped. */ 751 __u32 handle; 752 __u32 pad; 753 /** Offset in the object to map. */ 754 __u64 offset; 755 /** 756 * Length of data to map. 757 * 758 * The value will be page-aligned. 759 */ 760 __u64 size; 761 /** 762 * Returned pointer the data was mapped at. 763 * 764 * This is a fixed-size type for 32/64 compatibility. 765 */ 766 __u64 addr_ptr; 767 768 /** 769 * Flags for extended behaviour. 770 * 771 * Added in version 2. 772 */ 773 __u64 flags; 774 #define I915_MMAP_WC 0x1 775 }; 776 777 struct drm_i915_gem_mmap_gtt { 778 /** Handle for the object being mapped. */ 779 __u32 handle; 780 __u32 pad; 781 /** 782 * Fake offset to use for subsequent mmap call 783 * 784 * This is a fixed-size type for 32/64 compatibility. 785 */ 786 __u64 offset; 787 }; 788 789 struct drm_i915_gem_set_domain { 790 /** Handle for the object */ 791 __u32 handle; 792 793 /** New read domains */ 794 __u32 read_domains; 795 796 /** New write domain */ 797 __u32 write_domain; 798 }; 799 800 struct drm_i915_gem_sw_finish { 801 /** Handle for the object */ 802 __u32 handle; 803 }; 804 805 struct drm_i915_gem_relocation_entry { 806 /** 807 * Handle of the buffer being pointed to by this relocation entry. 808 * 809 * It's appealing to make this be an index into the mm_validate_entry 810 * list to refer to the buffer, but this allows the driver to create 811 * a relocation list for state buffers and not re-write it per 812 * exec using the buffer. 813 */ 814 __u32 target_handle; 815 816 /** 817 * Value to be added to the offset of the target buffer to make up 818 * the relocation entry. 819 */ 820 __u32 delta; 821 822 /** Offset in the buffer the relocation entry will be written into */ 823 __u64 offset; 824 825 /** 826 * Offset value of the target buffer that the relocation entry was last 827 * written as. 828 * 829 * If the buffer has the same offset as last time, we can skip syncing 830 * and writing the relocation. This value is written back out by 831 * the execbuffer ioctl when the relocation is written. 832 */ 833 __u64 presumed_offset; 834 835 /** 836 * Target memory domains read by this operation. 837 */ 838 __u32 read_domains; 839 840 /** 841 * Target memory domains written by this operation. 842 * 843 * Note that only one domain may be written by the whole 844 * execbuffer operation, so that where there are conflicts, 845 * the application will get -EINVAL back. 846 */ 847 __u32 write_domain; 848 }; 849 850 /** @{ 851 * Intel memory domains 852 * 853 * Most of these just align with the various caches in 854 * the system and are used to flush and invalidate as 855 * objects end up cached in different domains. 856 */ 857 /** CPU cache */ 858 #define I915_GEM_DOMAIN_CPU 0x00000001 859 /** Render cache, used by 2D and 3D drawing */ 860 #define I915_GEM_DOMAIN_RENDER 0x00000002 861 /** Sampler cache, used by texture engine */ 862 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 863 /** Command queue, used to load batch buffers */ 864 #define I915_GEM_DOMAIN_COMMAND 0x00000008 865 /** Instruction cache, used by shader programs */ 866 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 867 /** Vertex address cache */ 868 #define I915_GEM_DOMAIN_VERTEX 0x00000020 869 /** GTT domain - aperture and scanout */ 870 #define I915_GEM_DOMAIN_GTT 0x00000040 871 /** WC domain - uncached access */ 872 #define I915_GEM_DOMAIN_WC 0x00000080 873 /** @} */ 874 875 struct drm_i915_gem_exec_object { 876 /** 877 * User's handle for a buffer to be bound into the GTT for this 878 * operation. 879 */ 880 __u32 handle; 881 882 /** Number of relocations to be performed on this buffer */ 883 __u32 relocation_count; 884 /** 885 * Pointer to array of struct drm_i915_gem_relocation_entry containing 886 * the relocations to be performed in this buffer. 887 */ 888 __u64 relocs_ptr; 889 890 /** Required alignment in graphics aperture */ 891 __u64 alignment; 892 893 /** 894 * Returned value of the updated offset of the object, for future 895 * presumed_offset writes. 896 */ 897 __u64 offset; 898 }; 899 900 struct drm_i915_gem_execbuffer { 901 /** 902 * List of buffers to be validated with their relocations to be 903 * performend on them. 904 * 905 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 906 * 907 * These buffers must be listed in an order such that all relocations 908 * a buffer is performing refer to buffers that have already appeared 909 * in the validate list. 910 */ 911 __u64 buffers_ptr; 912 __u32 buffer_count; 913 914 /** Offset in the batchbuffer to start execution from. */ 915 __u32 batch_start_offset; 916 /** Bytes used in batchbuffer from batch_start_offset */ 917 __u32 batch_len; 918 __u32 DR1; 919 __u32 DR4; 920 __u32 num_cliprects; 921 /** This is a struct drm_clip_rect *cliprects */ 922 __u64 cliprects_ptr; 923 }; 924 925 struct drm_i915_gem_exec_object2 { 926 /** 927 * User's handle for a buffer to be bound into the GTT for this 928 * operation. 929 */ 930 __u32 handle; 931 932 /** Number of relocations to be performed on this buffer */ 933 __u32 relocation_count; 934 /** 935 * Pointer to array of struct drm_i915_gem_relocation_entry containing 936 * the relocations to be performed in this buffer. 937 */ 938 __u64 relocs_ptr; 939 940 /** Required alignment in graphics aperture */ 941 __u64 alignment; 942 943 /** 944 * When the EXEC_OBJECT_PINNED flag is specified this is populated by 945 * the user with the GTT offset at which this object will be pinned. 946 * When the I915_EXEC_NO_RELOC flag is specified this must contain the 947 * presumed_offset of the object. 948 * During execbuffer2 the kernel populates it with the value of the 949 * current GTT offset of the object, for future presumed_offset writes. 950 */ 951 __u64 offset; 952 953 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 954 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 955 #define EXEC_OBJECT_WRITE (1<<2) 956 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 957 #define EXEC_OBJECT_PINNED (1<<4) 958 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 959 /* The kernel implicitly tracks GPU activity on all GEM objects, and 960 * synchronises operations with outstanding rendering. This includes 961 * rendering on other devices if exported via dma-buf. However, sometimes 962 * this tracking is too coarse and the user knows better. For example, 963 * if the object is split into non-overlapping ranges shared between different 964 * clients or engines (i.e. suballocating objects), the implicit tracking 965 * by kernel assumes that each operation affects the whole object rather 966 * than an individual range, causing needless synchronisation between clients. 967 * The kernel will also forgo any CPU cache flushes prior to rendering from 968 * the object as the client is expected to be also handling such domain 969 * tracking. 970 * 971 * The kernel maintains the implicit tracking in order to manage resources 972 * used by the GPU - this flag only disables the synchronisation prior to 973 * rendering with this object in this execbuf. 974 * 975 * Opting out of implicit synhronisation requires the user to do its own 976 * explicit tracking to avoid rendering corruption. See, for example, 977 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 978 */ 979 #define EXEC_OBJECT_ASYNC (1<<6) 980 /* Request that the contents of this execobject be copied into the error 981 * state upon a GPU hang involving this batch for post-mortem debugging. 982 * These buffers are recorded in no particular order as "user" in 983 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 984 * if the kernel supports this flag. 985 */ 986 #define EXEC_OBJECT_CAPTURE (1<<7) 987 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 988 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 989 __u64 flags; 990 991 union { 992 __u64 rsvd1; 993 __u64 pad_to_size; 994 }; 995 __u64 rsvd2; 996 }; 997 998 struct drm_i915_gem_exec_fence { 999 /** 1000 * User's handle for a drm_syncobj to wait on or signal. 1001 */ 1002 __u32 handle; 1003 1004 #define I915_EXEC_FENCE_WAIT (1<<0) 1005 #define I915_EXEC_FENCE_SIGNAL (1<<1) 1006 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 1007 __u32 flags; 1008 }; 1009 1010 struct drm_i915_gem_execbuffer2 { 1011 /** 1012 * List of gem_exec_object2 structs 1013 */ 1014 __u64 buffers_ptr; 1015 __u32 buffer_count; 1016 1017 /** Offset in the batchbuffer to start execution from. */ 1018 __u32 batch_start_offset; 1019 /** Bytes used in batchbuffer from batch_start_offset */ 1020 __u32 batch_len; 1021 __u32 DR1; 1022 __u32 DR4; 1023 __u32 num_cliprects; 1024 /** 1025 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY 1026 * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a 1027 * struct drm_i915_gem_exec_fence *fences. 1028 */ 1029 __u64 cliprects_ptr; 1030 #define I915_EXEC_RING_MASK (0x3f) 1031 #define I915_EXEC_DEFAULT (0<<0) 1032 #define I915_EXEC_RENDER (1<<0) 1033 #define I915_EXEC_BSD (2<<0) 1034 #define I915_EXEC_BLT (3<<0) 1035 #define I915_EXEC_VEBOX (4<<0) 1036 1037 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 1038 * Gen6+ only supports relative addressing to dynamic state (default) and 1039 * absolute addressing. 1040 * 1041 * These flags are ignored for the BSD and BLT rings. 1042 */ 1043 #define I915_EXEC_CONSTANTS_MASK (3<<6) 1044 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 1045 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 1046 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 1047 __u64 flags; 1048 __u64 rsvd1; /* now used for context info */ 1049 __u64 rsvd2; 1050 }; 1051 1052 /** Resets the SO write offset registers for transform feedback on gen7. */ 1053 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 1054 1055 /** Request a privileged ("secure") batch buffer. Note only available for 1056 * DRM_ROOT_ONLY | DRM_MASTER processes. 1057 */ 1058 #define I915_EXEC_SECURE (1<<9) 1059 1060 /** Inform the kernel that the batch is and will always be pinned. This 1061 * negates the requirement for a workaround to be performed to avoid 1062 * an incoherent CS (such as can be found on 830/845). If this flag is 1063 * not passed, the kernel will endeavour to make sure the batch is 1064 * coherent with the CS before execution. If this flag is passed, 1065 * userspace assumes the responsibility for ensuring the same. 1066 */ 1067 #define I915_EXEC_IS_PINNED (1<<10) 1068 1069 /** Provide a hint to the kernel that the command stream and auxiliary 1070 * state buffers already holds the correct presumed addresses and so the 1071 * relocation process may be skipped if no buffers need to be moved in 1072 * preparation for the execbuffer. 1073 */ 1074 #define I915_EXEC_NO_RELOC (1<<11) 1075 1076 /** Use the reloc.handle as an index into the exec object array rather 1077 * than as the per-file handle. 1078 */ 1079 #define I915_EXEC_HANDLE_LUT (1<<12) 1080 1081 /** Used for switching BSD rings on the platforms with two BSD rings */ 1082 #define I915_EXEC_BSD_SHIFT (13) 1083 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 1084 /* default ping-pong mode */ 1085 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1086 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1087 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 1088 1089 /** Tell the kernel that the batchbuffer is processed by 1090 * the resource streamer. 1091 */ 1092 #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1093 1094 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1095 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1096 * the batch. 1097 * 1098 * Returns -EINVAL if the sync_file fd cannot be found. 1099 */ 1100 #define I915_EXEC_FENCE_IN (1<<16) 1101 1102 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1103 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1104 * to the caller, and it should be close() after use. (The fd is a regular 1105 * file descriptor and will be cleaned up on process termination. It holds 1106 * a reference to the request, but nothing else.) 1107 * 1108 * The sync_file fd can be combined with other sync_file and passed either 1109 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1110 * will only occur after this request completes), or to other devices. 1111 * 1112 * Using I915_EXEC_FENCE_OUT requires use of 1113 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1114 * back to userspace. Failure to do so will cause the out-fence to always 1115 * be reported as zero, and the real fence fd to be leaked. 1116 */ 1117 #define I915_EXEC_FENCE_OUT (1<<17) 1118 1119 /* 1120 * Traditionally the execbuf ioctl has only considered the final element in 1121 * the execobject[] to be the executable batch. Often though, the client 1122 * will known the batch object prior to construction and being able to place 1123 * it into the execobject[] array first can simplify the relocation tracking. 1124 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 1125 * execobject[] as the * batch instead (the default is to use the last 1126 * element). 1127 */ 1128 #define I915_EXEC_BATCH_FIRST (1<<18) 1129 1130 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1131 * define an array of i915_gem_exec_fence structures which specify a set of 1132 * dma fences to wait upon or signal. 1133 */ 1134 #define I915_EXEC_FENCE_ARRAY (1<<19) 1135 1136 /* 1137 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent 1138 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1139 * the batch. 1140 * 1141 * Returns -EINVAL if the sync_file fd cannot be found. 1142 */ 1143 #define I915_EXEC_FENCE_SUBMIT (1 << 20) 1144 1145 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1)) 1146 1147 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1148 #define i915_execbuffer2_set_context_id(eb2, context) \ 1149 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1150 #define i915_execbuffer2_get_context_id(eb2) \ 1151 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1152 1153 struct drm_i915_gem_pin { 1154 /** Handle of the buffer to be pinned. */ 1155 __u32 handle; 1156 __u32 pad; 1157 1158 /** alignment required within the aperture */ 1159 __u64 alignment; 1160 1161 /** Returned GTT offset of the buffer. */ 1162 __u64 offset; 1163 }; 1164 1165 struct drm_i915_gem_unpin { 1166 /** Handle of the buffer to be unpinned. */ 1167 __u32 handle; 1168 __u32 pad; 1169 }; 1170 1171 struct drm_i915_gem_busy { 1172 /** Handle of the buffer to check for busy */ 1173 __u32 handle; 1174 1175 /** Return busy status 1176 * 1177 * A return of 0 implies that the object is idle (after 1178 * having flushed any pending activity), and a non-zero return that 1179 * the object is still in-flight on the GPU. (The GPU has not yet 1180 * signaled completion for all pending requests that reference the 1181 * object.) An object is guaranteed to become idle eventually (so 1182 * long as no new GPU commands are executed upon it). Due to the 1183 * asynchronous nature of the hardware, an object reported 1184 * as busy may become idle before the ioctl is completed. 1185 * 1186 * Furthermore, if the object is busy, which engine is busy is only 1187 * provided as a guide and only indirectly by reporting its class 1188 * (there may be more than one engine in each class). There are race 1189 * conditions which prevent the report of which engines are busy from 1190 * being always accurate. However, the converse is not true. If the 1191 * object is idle, the result of the ioctl, that all engines are idle, 1192 * is accurate. 1193 * 1194 * The returned dword is split into two fields to indicate both 1195 * the engine classess on which the object is being read, and the 1196 * engine class on which it is currently being written (if any). 1197 * 1198 * The low word (bits 0:15) indicate if the object is being written 1199 * to by any engine (there can only be one, as the GEM implicit 1200 * synchronisation rules force writes to be serialised). Only the 1201 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as 1202 * 1 not 0 etc) for the last write is reported. 1203 * 1204 * The high word (bits 16:31) are a bitmask of which engines classes 1205 * are currently reading from the object. Multiple engines may be 1206 * reading from the object simultaneously. 1207 * 1208 * The value of each engine class is the same as specified in the 1209 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e. 1210 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. 1211 * reported as active itself. Some hardware may have parallel 1212 * execution engines, e.g. multiple media engines, which are 1213 * mapped to the same class identifier and so are not separately 1214 * reported for busyness. 1215 * 1216 * Caveat emptor: 1217 * Only the boolean result of this query is reliable; that is whether 1218 * the object is idle or busy. The report of which engines are busy 1219 * should be only used as a heuristic. 1220 */ 1221 __u32 busy; 1222 }; 1223 1224 /** 1225 * I915_CACHING_NONE 1226 * 1227 * GPU access is not coherent with cpu caches. Default for machines without an 1228 * LLC. 1229 */ 1230 #define I915_CACHING_NONE 0 1231 /** 1232 * I915_CACHING_CACHED 1233 * 1234 * GPU access is coherent with cpu caches and furthermore the data is cached in 1235 * last-level caches shared between cpu cores and the gpu GT. Default on 1236 * machines with HAS_LLC. 1237 */ 1238 #define I915_CACHING_CACHED 1 1239 /** 1240 * I915_CACHING_DISPLAY 1241 * 1242 * Special GPU caching mode which is coherent with the scanout engines. 1243 * Transparently falls back to I915_CACHING_NONE on platforms where no special 1244 * cache mode (like write-through or gfdt flushing) is available. The kernel 1245 * automatically sets this mode when using a buffer as a scanout target. 1246 * Userspace can manually set this mode to avoid a costly stall and clflush in 1247 * the hotpath of drawing the first frame. 1248 */ 1249 #define I915_CACHING_DISPLAY 2 1250 1251 struct drm_i915_gem_caching { 1252 /** 1253 * Handle of the buffer to set/get the caching level of. */ 1254 __u32 handle; 1255 1256 /** 1257 * Cacheing level to apply or return value 1258 * 1259 * bits0-15 are for generic caching control (i.e. the above defined 1260 * values). bits16-31 are reserved for platform-specific variations 1261 * (e.g. l3$ caching on gen7). */ 1262 __u32 caching; 1263 }; 1264 1265 #define I915_TILING_NONE 0 1266 #define I915_TILING_X 1 1267 #define I915_TILING_Y 2 1268 #define I915_TILING_LAST I915_TILING_Y 1269 1270 #define I915_BIT_6_SWIZZLE_NONE 0 1271 #define I915_BIT_6_SWIZZLE_9 1 1272 #define I915_BIT_6_SWIZZLE_9_10 2 1273 #define I915_BIT_6_SWIZZLE_9_11 3 1274 #define I915_BIT_6_SWIZZLE_9_10_11 4 1275 /* Not seen by userland */ 1276 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1277 /* Seen by userland. */ 1278 #define I915_BIT_6_SWIZZLE_9_17 6 1279 #define I915_BIT_6_SWIZZLE_9_10_17 7 1280 1281 struct drm_i915_gem_set_tiling { 1282 /** Handle of the buffer to have its tiling state updated */ 1283 __u32 handle; 1284 1285 /** 1286 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1287 * I915_TILING_Y). 1288 * 1289 * This value is to be set on request, and will be updated by the 1290 * kernel on successful return with the actual chosen tiling layout. 1291 * 1292 * The tiling mode may be demoted to I915_TILING_NONE when the system 1293 * has bit 6 swizzling that can't be managed correctly by GEM. 1294 * 1295 * Buffer contents become undefined when changing tiling_mode. 1296 */ 1297 __u32 tiling_mode; 1298 1299 /** 1300 * Stride in bytes for the object when in I915_TILING_X or 1301 * I915_TILING_Y. 1302 */ 1303 __u32 stride; 1304 1305 /** 1306 * Returned address bit 6 swizzling required for CPU access through 1307 * mmap mapping. 1308 */ 1309 __u32 swizzle_mode; 1310 }; 1311 1312 struct drm_i915_gem_get_tiling { 1313 /** Handle of the buffer to get tiling state for. */ 1314 __u32 handle; 1315 1316 /** 1317 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1318 * I915_TILING_Y). 1319 */ 1320 __u32 tiling_mode; 1321 1322 /** 1323 * Returned address bit 6 swizzling required for CPU access through 1324 * mmap mapping. 1325 */ 1326 __u32 swizzle_mode; 1327 1328 /** 1329 * Returned address bit 6 swizzling required for CPU access through 1330 * mmap mapping whilst bound. 1331 */ 1332 __u32 phys_swizzle_mode; 1333 }; 1334 1335 struct drm_i915_gem_get_aperture { 1336 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1337 __u64 aper_size; 1338 1339 /** 1340 * Available space in the aperture used by i915_gem_execbuffer, in 1341 * bytes 1342 */ 1343 __u64 aper_available_size; 1344 }; 1345 1346 struct drm_i915_get_pipe_from_crtc_id { 1347 /** ID of CRTC being requested **/ 1348 __u32 crtc_id; 1349 1350 /** pipe of requested CRTC **/ 1351 __u32 pipe; 1352 }; 1353 1354 #define I915_MADV_WILLNEED 0 1355 #define I915_MADV_DONTNEED 1 1356 #define __I915_MADV_PURGED 2 /* internal state */ 1357 1358 struct drm_i915_gem_madvise { 1359 /** Handle of the buffer to change the backing store advice */ 1360 __u32 handle; 1361 1362 /* Advice: either the buffer will be needed again in the near future, 1363 * or wont be and could be discarded under memory pressure. 1364 */ 1365 __u32 madv; 1366 1367 /** Whether the backing store still exists. */ 1368 __u32 retained; 1369 }; 1370 1371 /* flags */ 1372 #define I915_OVERLAY_TYPE_MASK 0xff 1373 #define I915_OVERLAY_YUV_PLANAR 0x01 1374 #define I915_OVERLAY_YUV_PACKED 0x02 1375 #define I915_OVERLAY_RGB 0x03 1376 1377 #define I915_OVERLAY_DEPTH_MASK 0xff00 1378 #define I915_OVERLAY_RGB24 0x1000 1379 #define I915_OVERLAY_RGB16 0x2000 1380 #define I915_OVERLAY_RGB15 0x3000 1381 #define I915_OVERLAY_YUV422 0x0100 1382 #define I915_OVERLAY_YUV411 0x0200 1383 #define I915_OVERLAY_YUV420 0x0300 1384 #define I915_OVERLAY_YUV410 0x0400 1385 1386 #define I915_OVERLAY_SWAP_MASK 0xff0000 1387 #define I915_OVERLAY_NO_SWAP 0x000000 1388 #define I915_OVERLAY_UV_SWAP 0x010000 1389 #define I915_OVERLAY_Y_SWAP 0x020000 1390 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1391 1392 #define I915_OVERLAY_FLAGS_MASK 0xff000000 1393 #define I915_OVERLAY_ENABLE 0x01000000 1394 1395 struct drm_intel_overlay_put_image { 1396 /* various flags and src format description */ 1397 __u32 flags; 1398 /* source picture description */ 1399 __u32 bo_handle; 1400 /* stride values and offsets are in bytes, buffer relative */ 1401 __u16 stride_Y; /* stride for packed formats */ 1402 __u16 stride_UV; 1403 __u32 offset_Y; /* offset for packet formats */ 1404 __u32 offset_U; 1405 __u32 offset_V; 1406 /* in pixels */ 1407 __u16 src_width; 1408 __u16 src_height; 1409 /* to compensate the scaling factors for partially covered surfaces */ 1410 __u16 src_scan_width; 1411 __u16 src_scan_height; 1412 /* output crtc description */ 1413 __u32 crtc_id; 1414 __u16 dst_x; 1415 __u16 dst_y; 1416 __u16 dst_width; 1417 __u16 dst_height; 1418 }; 1419 1420 /* flags */ 1421 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1422 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1423 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1424 struct drm_intel_overlay_attrs { 1425 __u32 flags; 1426 __u32 color_key; 1427 __s32 brightness; 1428 __u32 contrast; 1429 __u32 saturation; 1430 __u32 gamma0; 1431 __u32 gamma1; 1432 __u32 gamma2; 1433 __u32 gamma3; 1434 __u32 gamma4; 1435 __u32 gamma5; 1436 }; 1437 1438 /* 1439 * Intel sprite handling 1440 * 1441 * Color keying works with a min/mask/max tuple. Both source and destination 1442 * color keying is allowed. 1443 * 1444 * Source keying: 1445 * Sprite pixels within the min & max values, masked against the color channels 1446 * specified in the mask field, will be transparent. All other pixels will 1447 * be displayed on top of the primary plane. For RGB surfaces, only the min 1448 * and mask fields will be used; ranged compares are not allowed. 1449 * 1450 * Destination keying: 1451 * Primary plane pixels that match the min value, masked against the color 1452 * channels specified in the mask field, will be replaced by corresponding 1453 * pixels from the sprite plane. 1454 * 1455 * Note that source & destination keying are exclusive; only one can be 1456 * active on a given plane. 1457 */ 1458 1459 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 1460 * flags==0 to disable colorkeying. 1461 */ 1462 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1463 #define I915_SET_COLORKEY_SOURCE (1<<2) 1464 struct drm_intel_sprite_colorkey { 1465 __u32 plane_id; 1466 __u32 min_value; 1467 __u32 channel_mask; 1468 __u32 max_value; 1469 __u32 flags; 1470 }; 1471 1472 struct drm_i915_gem_wait { 1473 /** Handle of BO we shall wait on */ 1474 __u32 bo_handle; 1475 __u32 flags; 1476 /** Number of nanoseconds to wait, Returns time remaining. */ 1477 __s64 timeout_ns; 1478 }; 1479 1480 struct drm_i915_gem_context_create { 1481 __u32 ctx_id; /* output: id of new context*/ 1482 __u32 pad; 1483 }; 1484 1485 struct drm_i915_gem_context_create_ext { 1486 __u32 ctx_id; /* output: id of new context*/ 1487 __u32 flags; 1488 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 1489 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 1490 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ 1491 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 1492 __u64 extensions; 1493 }; 1494 1495 struct drm_i915_gem_context_param { 1496 __u32 ctx_id; 1497 __u32 size; 1498 __u64 param; 1499 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1500 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1501 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1502 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 1503 #define I915_CONTEXT_PARAM_BANNABLE 0x5 1504 #define I915_CONTEXT_PARAM_PRIORITY 0x6 1505 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 1506 #define I915_CONTEXT_DEFAULT_PRIORITY 0 1507 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 1508 /* 1509 * When using the following param, value should be a pointer to 1510 * drm_i915_gem_context_param_sseu. 1511 */ 1512 #define I915_CONTEXT_PARAM_SSEU 0x7 1513 1514 /* 1515 * Not all clients may want to attempt automatic recover of a context after 1516 * a hang (for example, some clients may only submit very small incremental 1517 * batches relying on known logical state of previous batches which will never 1518 * recover correctly and each attempt will hang), and so would prefer that 1519 * the context is forever banned instead. 1520 * 1521 * If set to false (0), after a reset, subsequent (and in flight) rendering 1522 * from this context is discarded, and the client will need to create a new 1523 * context to use instead. 1524 * 1525 * If set to true (1), the kernel will automatically attempt to recover the 1526 * context by skipping the hanging batch and executing the next batch starting 1527 * from the default context state (discarding the incomplete logical context 1528 * state lost due to the reset). 1529 * 1530 * On creation, all new contexts are marked as recoverable. 1531 */ 1532 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 1533 1534 /* 1535 * The id of the associated virtual memory address space (ppGTT) of 1536 * this context. Can be retrieved and passed to another context 1537 * (on the same fd) for both to use the same ppGTT and so share 1538 * address layouts, and avoid reloading the page tables on context 1539 * switches between themselves. 1540 * 1541 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. 1542 */ 1543 #define I915_CONTEXT_PARAM_VM 0x9 1544 1545 /* 1546 * I915_CONTEXT_PARAM_ENGINES: 1547 * 1548 * Bind this context to operate on this subset of available engines. Henceforth, 1549 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as 1550 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] 1551 * and upwards. Slots 0...N are filled in using the specified (class, instance). 1552 * Use 1553 * engine_class: I915_ENGINE_CLASS_INVALID, 1554 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE 1555 * to specify a gap in the array that can be filled in later, e.g. by a 1556 * virtual engine used for load balancing. 1557 * 1558 * Setting the number of engines bound to the context to 0, by passing a zero 1559 * sized argument, will revert back to default settings. 1560 * 1561 * See struct i915_context_param_engines. 1562 * 1563 * Extensions: 1564 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) 1565 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) 1566 */ 1567 #define I915_CONTEXT_PARAM_ENGINES 0xa 1568 /* Must be kept compact -- no holes and well documented */ 1569 1570 __u64 value; 1571 }; 1572 1573 /** 1574 * Context SSEU programming 1575 * 1576 * It may be necessary for either functional or performance reason to configure 1577 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ 1578 * Sub-slice/EU). 1579 * 1580 * This is done by configuring SSEU configuration using the below 1581 * @struct drm_i915_gem_context_param_sseu for every supported engine which 1582 * userspace intends to use. 1583 * 1584 * Not all GPUs or engines support this functionality in which case an error 1585 * code -ENODEV will be returned. 1586 * 1587 * Also, flexibility of possible SSEU configuration permutations varies between 1588 * GPU generations and software imposed limitations. Requesting such a 1589 * combination will return an error code of -EINVAL. 1590 * 1591 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in 1592 * favour of a single global setting. 1593 */ 1594 struct drm_i915_gem_context_param_sseu { 1595 /* 1596 * Engine class & instance to be configured or queried. 1597 */ 1598 struct i915_engine_class_instance engine; 1599 1600 /* 1601 * Unknown flags must be cleared to zero. 1602 */ 1603 __u32 flags; 1604 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 1605 1606 /* 1607 * Mask of slices to enable for the context. Valid values are a subset 1608 * of the bitmask value returned for I915_PARAM_SLICE_MASK. 1609 */ 1610 __u64 slice_mask; 1611 1612 /* 1613 * Mask of subslices to enable for the context. Valid values are a 1614 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. 1615 */ 1616 __u64 subslice_mask; 1617 1618 /* 1619 * Minimum/Maximum number of EUs to enable per subslice for the 1620 * context. min_eus_per_subslice must be inferior or equal to 1621 * max_eus_per_subslice. 1622 */ 1623 __u16 min_eus_per_subslice; 1624 __u16 max_eus_per_subslice; 1625 1626 /* 1627 * Unused for now. Must be cleared to zero. 1628 */ 1629 __u32 rsvd; 1630 }; 1631 1632 /* 1633 * i915_context_engines_load_balance: 1634 * 1635 * Enable load balancing across this set of engines. 1636 * 1637 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when 1638 * used will proxy the execbuffer request onto one of the set of engines 1639 * in such a way as to distribute the load evenly across the set. 1640 * 1641 * The set of engines must be compatible (e.g. the same HW class) as they 1642 * will share the same logical GPU context and ring. 1643 * 1644 * To intermix rendering with the virtual engine and direct rendering onto 1645 * the backing engines (bypassing the load balancing proxy), the context must 1646 * be defined to use a single timeline for all engines. 1647 */ 1648 struct i915_context_engines_load_balance { 1649 struct i915_user_extension base; 1650 1651 __u16 engine_index; 1652 __u16 num_siblings; 1653 __u32 flags; /* all undefined flags must be zero */ 1654 1655 __u64 mbz64; /* reserved for future use; must be zero */ 1656 1657 struct i915_engine_class_instance engines[0]; 1658 } __attribute__((packed)); 1659 1660 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ 1661 struct i915_user_extension base; \ 1662 __u16 engine_index; \ 1663 __u16 num_siblings; \ 1664 __u32 flags; \ 1665 __u64 mbz64; \ 1666 struct i915_engine_class_instance engines[N__]; \ 1667 } __attribute__((packed)) name__ 1668 1669 /* 1670 * i915_context_engines_bond: 1671 * 1672 * Constructed bonded pairs for execution within a virtual engine. 1673 * 1674 * All engines are equal, but some are more equal than others. Given 1675 * the distribution of resources in the HW, it may be preferable to run 1676 * a request on a given subset of engines in parallel to a request on a 1677 * specific engine. We enable this selection of engines within a virtual 1678 * engine by specifying bonding pairs, for any given master engine we will 1679 * only execute on one of the corresponding siblings within the virtual engine. 1680 * 1681 * To execute a request in parallel on the master engine and a sibling requires 1682 * coordination with a I915_EXEC_FENCE_SUBMIT. 1683 */ 1684 struct i915_context_engines_bond { 1685 struct i915_user_extension base; 1686 1687 struct i915_engine_class_instance master; 1688 1689 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ 1690 __u16 num_bonds; 1691 1692 __u64 flags; /* all undefined flags must be zero */ 1693 __u64 mbz64[4]; /* reserved for future use; must be zero */ 1694 1695 struct i915_engine_class_instance engines[0]; 1696 } __attribute__((packed)); 1697 1698 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ 1699 struct i915_user_extension base; \ 1700 struct i915_engine_class_instance master; \ 1701 __u16 virtual_index; \ 1702 __u16 num_bonds; \ 1703 __u64 flags; \ 1704 __u64 mbz64[4]; \ 1705 struct i915_engine_class_instance engines[N__]; \ 1706 } __attribute__((packed)) name__ 1707 1708 struct i915_context_param_engines { 1709 __u64 extensions; /* linked chain of extension blocks, 0 terminates */ 1710 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 1711 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 1712 struct i915_engine_class_instance engines[0]; 1713 } __attribute__((packed)); 1714 1715 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ 1716 __u64 extensions; \ 1717 struct i915_engine_class_instance engines[N__]; \ 1718 } __attribute__((packed)) name__ 1719 1720 struct drm_i915_gem_context_create_ext_setparam { 1721 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 1722 struct i915_user_extension base; 1723 struct drm_i915_gem_context_param param; 1724 }; 1725 1726 struct drm_i915_gem_context_create_ext_clone { 1727 #define I915_CONTEXT_CREATE_EXT_CLONE 1 1728 struct i915_user_extension base; 1729 __u32 clone_id; 1730 __u32 flags; 1731 #define I915_CONTEXT_CLONE_ENGINES (1u << 0) 1732 #define I915_CONTEXT_CLONE_FLAGS (1u << 1) 1733 #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2) 1734 #define I915_CONTEXT_CLONE_SSEU (1u << 3) 1735 #define I915_CONTEXT_CLONE_TIMELINE (1u << 4) 1736 #define I915_CONTEXT_CLONE_VM (1u << 5) 1737 #define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1) 1738 __u64 rsvd; 1739 }; 1740 1741 struct drm_i915_gem_context_destroy { 1742 __u32 ctx_id; 1743 __u32 pad; 1744 }; 1745 1746 /* 1747 * DRM_I915_GEM_VM_CREATE - 1748 * 1749 * Create a new virtual memory address space (ppGTT) for use within a context 1750 * on the same file. Extensions can be provided to configure exactly how the 1751 * address space is setup upon creation. 1752 * 1753 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is 1754 * returned in the outparam @id. 1755 * 1756 * No flags are defined, with all bits reserved and must be zero. 1757 * 1758 * An extension chain maybe provided, starting with @extensions, and terminated 1759 * by the @next_extension being 0. Currently, no extensions are defined. 1760 * 1761 * DRM_I915_GEM_VM_DESTROY - 1762 * 1763 * Destroys a previously created VM id, specified in @id. 1764 * 1765 * No extensions or flags are allowed currently, and so must be zero. 1766 */ 1767 struct drm_i915_gem_vm_control { 1768 __u64 extensions; 1769 __u32 flags; 1770 __u32 vm_id; 1771 }; 1772 1773 struct drm_i915_reg_read { 1774 /* 1775 * Register offset. 1776 * For 64bit wide registers where the upper 32bits don't immediately 1777 * follow the lower 32bits, the offset of the lower 32bits must 1778 * be specified 1779 */ 1780 __u64 offset; 1781 #define I915_REG_READ_8B_WA (1ul << 0) 1782 1783 __u64 val; /* Return value */ 1784 }; 1785 1786 /* Known registers: 1787 * 1788 * Render engine timestamp - 0x2358 + 64bit - gen7+ 1789 * - Note this register returns an invalid value if using the default 1790 * single instruction 8byte read, in order to workaround that pass 1791 * flag I915_REG_READ_8B_WA in offset field. 1792 * 1793 */ 1794 1795 struct drm_i915_reset_stats { 1796 __u32 ctx_id; 1797 __u32 flags; 1798 1799 /* All resets since boot/module reload, for all contexts */ 1800 __u32 reset_count; 1801 1802 /* Number of batches lost when active in GPU, for this context */ 1803 __u32 batch_active; 1804 1805 /* Number of batches lost pending for execution, for this context */ 1806 __u32 batch_pending; 1807 1808 __u32 pad; 1809 }; 1810 1811 struct drm_i915_gem_userptr { 1812 __u64 user_ptr; 1813 __u64 user_size; 1814 __u32 flags; 1815 #define I915_USERPTR_READ_ONLY 0x1 1816 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1817 /** 1818 * Returned handle for the object. 1819 * 1820 * Object handles are nonzero. 1821 */ 1822 __u32 handle; 1823 }; 1824 1825 enum drm_i915_oa_format { 1826 I915_OA_FORMAT_A13 = 1, /* HSW only */ 1827 I915_OA_FORMAT_A29, /* HSW only */ 1828 I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 1829 I915_OA_FORMAT_B4_C8, /* HSW only */ 1830 I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 1831 I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 1832 I915_OA_FORMAT_C4_B8, /* HSW+ */ 1833 1834 /* Gen8+ */ 1835 I915_OA_FORMAT_A12, 1836 I915_OA_FORMAT_A12_B8_C8, 1837 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 1838 1839 I915_OA_FORMAT_MAX /* non-ABI */ 1840 }; 1841 1842 enum drm_i915_perf_property_id { 1843 /** 1844 * Open the stream for a specific context handle (as used with 1845 * execbuffer2). A stream opened for a specific context this way 1846 * won't typically require root privileges. 1847 */ 1848 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 1849 1850 /** 1851 * A value of 1 requests the inclusion of raw OA unit reports as 1852 * part of stream samples. 1853 */ 1854 DRM_I915_PERF_PROP_SAMPLE_OA, 1855 1856 /** 1857 * The value specifies which set of OA unit metrics should be 1858 * be configured, defining the contents of any OA unit reports. 1859 */ 1860 DRM_I915_PERF_PROP_OA_METRICS_SET, 1861 1862 /** 1863 * The value specifies the size and layout of OA unit reports. 1864 */ 1865 DRM_I915_PERF_PROP_OA_FORMAT, 1866 1867 /** 1868 * Specifying this property implicitly requests periodic OA unit 1869 * sampling and (at least on Haswell) the sampling frequency is derived 1870 * from this exponent as follows: 1871 * 1872 * 80ns * 2^(period_exponent + 1) 1873 */ 1874 DRM_I915_PERF_PROP_OA_EXPONENT, 1875 1876 DRM_I915_PERF_PROP_MAX /* non-ABI */ 1877 }; 1878 1879 struct drm_i915_perf_open_param { 1880 __u32 flags; 1881 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 1882 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 1883 #define I915_PERF_FLAG_DISABLED (1<<2) 1884 1885 /** The number of u64 (id, value) pairs */ 1886 __u32 num_properties; 1887 1888 /** 1889 * Pointer to array of u64 (id, value) pairs configuring the stream 1890 * to open. 1891 */ 1892 __u64 properties_ptr; 1893 }; 1894 1895 /** 1896 * Enable data capture for a stream that was either opened in a disabled state 1897 * via I915_PERF_FLAG_DISABLED or was later disabled via 1898 * I915_PERF_IOCTL_DISABLE. 1899 * 1900 * It is intended to be cheaper to disable and enable a stream than it may be 1901 * to close and re-open a stream with the same configuration. 1902 * 1903 * It's undefined whether any pending data for the stream will be lost. 1904 */ 1905 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 1906 1907 /** 1908 * Disable data capture for a stream. 1909 * 1910 * It is an error to try and read a stream that is disabled. 1911 */ 1912 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 1913 1914 /** 1915 * Common to all i915 perf records 1916 */ 1917 struct drm_i915_perf_record_header { 1918 __u32 type; 1919 __u16 pad; 1920 __u16 size; 1921 }; 1922 1923 enum drm_i915_perf_record_type { 1924 1925 /** 1926 * Samples are the work horse record type whose contents are extensible 1927 * and defined when opening an i915 perf stream based on the given 1928 * properties. 1929 * 1930 * Boolean properties following the naming convention 1931 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 1932 * every sample. 1933 * 1934 * The order of these sample properties given by userspace has no 1935 * affect on the ordering of data within a sample. The order is 1936 * documented here. 1937 * 1938 * struct { 1939 * struct drm_i915_perf_record_header header; 1940 * 1941 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 1942 * }; 1943 */ 1944 DRM_I915_PERF_RECORD_SAMPLE = 1, 1945 1946 /* 1947 * Indicates that one or more OA reports were not written by the 1948 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 1949 * command collides with periodic sampling - which would be more likely 1950 * at higher sampling frequencies. 1951 */ 1952 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 1953 1954 /** 1955 * An error occurred that resulted in all pending OA reports being lost. 1956 */ 1957 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 1958 1959 DRM_I915_PERF_RECORD_MAX /* non-ABI */ 1960 }; 1961 1962 /** 1963 * Structure to upload perf dynamic configuration into the kernel. 1964 */ 1965 struct drm_i915_perf_oa_config { 1966 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ 1967 char uuid[36]; 1968 1969 __u32 n_mux_regs; 1970 __u32 n_boolean_regs; 1971 __u32 n_flex_regs; 1972 1973 /* 1974 * These fields are pointers to tuples of u32 values (register address, 1975 * value). For example the expected length of the buffer pointed by 1976 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). 1977 */ 1978 __u64 mux_regs_ptr; 1979 __u64 boolean_regs_ptr; 1980 __u64 flex_regs_ptr; 1981 }; 1982 1983 struct drm_i915_query_item { 1984 __u64 query_id; 1985 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 1986 #define DRM_I915_QUERY_ENGINE_INFO 2 1987 /* Must be kept compact -- no holes and well documented */ 1988 1989 /* 1990 * When set to zero by userspace, this is filled with the size of the 1991 * data to be written at the data_ptr pointer. The kernel sets this 1992 * value to a negative value to signal an error on a particular query 1993 * item. 1994 */ 1995 __s32 length; 1996 1997 /* 1998 * Unused for now. Must be cleared to zero. 1999 */ 2000 __u32 flags; 2001 2002 /* 2003 * Data will be written at the location pointed by data_ptr when the 2004 * value of length matches the length of the data to be written by the 2005 * kernel. 2006 */ 2007 __u64 data_ptr; 2008 }; 2009 2010 struct drm_i915_query { 2011 __u32 num_items; 2012 2013 /* 2014 * Unused for now. Must be cleared to zero. 2015 */ 2016 __u32 flags; 2017 2018 /* 2019 * This points to an array of num_items drm_i915_query_item structures. 2020 */ 2021 __u64 items_ptr; 2022 }; 2023 2024 /* 2025 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : 2026 * 2027 * data: contains the 3 pieces of information : 2028 * 2029 * - the slice mask with one bit per slice telling whether a slice is 2030 * available. The availability of slice X can be queried with the following 2031 * formula : 2032 * 2033 * (data[X / 8] >> (X % 8)) & 1 2034 * 2035 * - the subslice mask for each slice with one bit per subslice telling 2036 * whether a subslice is available. The availability of subslice Y in slice 2037 * X can be queried with the following formula : 2038 * 2039 * (data[subslice_offset + 2040 * X * subslice_stride + 2041 * Y / 8] >> (Y % 8)) & 1 2042 * 2043 * - the EU mask for each subslice in each slice with one bit per EU telling 2044 * whether an EU is available. The availability of EU Z in subslice Y in 2045 * slice X can be queried with the following formula : 2046 * 2047 * (data[eu_offset + 2048 * (X * max_subslices + Y) * eu_stride + 2049 * Z / 8] >> (Z % 8)) & 1 2050 */ 2051 struct drm_i915_query_topology_info { 2052 /* 2053 * Unused for now. Must be cleared to zero. 2054 */ 2055 __u16 flags; 2056 2057 __u16 max_slices; 2058 __u16 max_subslices; 2059 __u16 max_eus_per_subslice; 2060 2061 /* 2062 * Offset in data[] at which the subslice masks are stored. 2063 */ 2064 __u16 subslice_offset; 2065 2066 /* 2067 * Stride at which each of the subslice masks for each slice are 2068 * stored. 2069 */ 2070 __u16 subslice_stride; 2071 2072 /* 2073 * Offset in data[] at which the EU masks are stored. 2074 */ 2075 __u16 eu_offset; 2076 2077 /* 2078 * Stride at which each of the EU masks for each subslice are stored. 2079 */ 2080 __u16 eu_stride; 2081 2082 __u8 data[]; 2083 }; 2084 2085 /** 2086 * struct drm_i915_engine_info 2087 * 2088 * Describes one engine and it's capabilities as known to the driver. 2089 */ 2090 struct drm_i915_engine_info { 2091 /** Engine class and instance. */ 2092 struct i915_engine_class_instance engine; 2093 2094 /** Reserved field. */ 2095 __u32 rsvd0; 2096 2097 /** Engine flags. */ 2098 __u64 flags; 2099 2100 /** Capabilities of this engine. */ 2101 __u64 capabilities; 2102 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 2103 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 2104 2105 /** Reserved fields. */ 2106 __u64 rsvd1[4]; 2107 }; 2108 2109 /** 2110 * struct drm_i915_query_engine_info 2111 * 2112 * Engine info query enumerates all engines known to the driver by filling in 2113 * an array of struct drm_i915_engine_info structures. 2114 */ 2115 struct drm_i915_query_engine_info { 2116 /** Number of struct drm_i915_engine_info structs following. */ 2117 __u32 num_engines; 2118 2119 /** MBZ */ 2120 __u32 rsvd[3]; 2121 2122 /** Marker for drm_i915_engine_info structures. */ 2123 struct drm_i915_engine_info engines[]; 2124 }; 2125 2126 #if defined(__cplusplus) 2127 } 2128 #endif 2129 2130 #endif /* _UAPI_I915_DRM_H_ */ 2131