1c1737f2bSArnaldo Carvalho de Melo /* 2c1737f2bSArnaldo Carvalho de Melo * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c1737f2bSArnaldo Carvalho de Melo * All Rights Reserved. 4c1737f2bSArnaldo Carvalho de Melo * 5c1737f2bSArnaldo Carvalho de Melo * Permission is hereby granted, free of charge, to any person obtaining a 6c1737f2bSArnaldo Carvalho de Melo * copy of this software and associated documentation files (the 7c1737f2bSArnaldo Carvalho de Melo * "Software"), to deal in the Software without restriction, including 8c1737f2bSArnaldo Carvalho de Melo * without limitation the rights to use, copy, modify, merge, publish, 9c1737f2bSArnaldo Carvalho de Melo * distribute, sub license, and/or sell copies of the Software, and to 10c1737f2bSArnaldo Carvalho de Melo * permit persons to whom the Software is furnished to do so, subject to 11c1737f2bSArnaldo Carvalho de Melo * the following conditions: 12c1737f2bSArnaldo Carvalho de Melo * 13c1737f2bSArnaldo Carvalho de Melo * The above copyright notice and this permission notice (including the 14c1737f2bSArnaldo Carvalho de Melo * next paragraph) shall be included in all copies or substantial portions 15c1737f2bSArnaldo Carvalho de Melo * of the Software. 16c1737f2bSArnaldo Carvalho de Melo * 17c1737f2bSArnaldo Carvalho de Melo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c1737f2bSArnaldo Carvalho de Melo * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c1737f2bSArnaldo Carvalho de Melo * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c1737f2bSArnaldo Carvalho de Melo * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c1737f2bSArnaldo Carvalho de Melo * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c1737f2bSArnaldo Carvalho de Melo * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c1737f2bSArnaldo Carvalho de Melo * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c1737f2bSArnaldo Carvalho de Melo * 25c1737f2bSArnaldo Carvalho de Melo */ 26c1737f2bSArnaldo Carvalho de Melo 27c1737f2bSArnaldo Carvalho de Melo #ifndef _UAPI_I915_DRM_H_ 28c1737f2bSArnaldo Carvalho de Melo #define _UAPI_I915_DRM_H_ 29c1737f2bSArnaldo Carvalho de Melo 30c1737f2bSArnaldo Carvalho de Melo #include "drm.h" 31c1737f2bSArnaldo Carvalho de Melo 32c1737f2bSArnaldo Carvalho de Melo #if defined(__cplusplus) 33c1737f2bSArnaldo Carvalho de Melo extern "C" { 34c1737f2bSArnaldo Carvalho de Melo #endif 35c1737f2bSArnaldo Carvalho de Melo 36c1737f2bSArnaldo Carvalho de Melo /* Please note that modifications to all structs defined here are 37c1737f2bSArnaldo Carvalho de Melo * subject to backwards-compatibility constraints. 38c1737f2bSArnaldo Carvalho de Melo */ 39c1737f2bSArnaldo Carvalho de Melo 40c1737f2bSArnaldo Carvalho de Melo /** 41c1737f2bSArnaldo Carvalho de Melo * DOC: uevents generated by i915 on it's device node 42c1737f2bSArnaldo Carvalho de Melo * 43c1737f2bSArnaldo Carvalho de Melo * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44c1737f2bSArnaldo Carvalho de Melo * event from the gpu l3 cache. Additional information supplied is ROW, 45c1737f2bSArnaldo Carvalho de Melo * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46c1737f2bSArnaldo Carvalho de Melo * track of these events and if a specific cache-line seems to have a 47c1737f2bSArnaldo Carvalho de Melo * persistent error remap it with the l3 remapping tool supplied in 48c1737f2bSArnaldo Carvalho de Melo * intel-gpu-tools. The value supplied with the event is always 1. 49c1737f2bSArnaldo Carvalho de Melo * 50c1737f2bSArnaldo Carvalho de Melo * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51c1737f2bSArnaldo Carvalho de Melo * hangcheck. The error detection event is a good indicator of when things 52c1737f2bSArnaldo Carvalho de Melo * began to go badly. The value supplied with the event is a 1 upon error 53c1737f2bSArnaldo Carvalho de Melo * detection, and a 0 upon reset completion, signifying no more error 54c1737f2bSArnaldo Carvalho de Melo * exists. NOTE: Disabling hangcheck or reset via module parameter will 55c1737f2bSArnaldo Carvalho de Melo * cause the related events to not be seen. 56c1737f2bSArnaldo Carvalho de Melo * 57c1737f2bSArnaldo Carvalho de Melo * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58d01541d0SArnaldo Carvalho de Melo * GPU. The value supplied with the event is always 1. NOTE: Disable 59c1737f2bSArnaldo Carvalho de Melo * reset via module parameter will cause this event to not be seen. 60c1737f2bSArnaldo Carvalho de Melo */ 61c1737f2bSArnaldo Carvalho de Melo #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62c1737f2bSArnaldo Carvalho de Melo #define I915_ERROR_UEVENT "ERROR" 63c1737f2bSArnaldo Carvalho de Melo #define I915_RESET_UEVENT "RESET" 64c1737f2bSArnaldo Carvalho de Melo 654a1cddeaSArnaldo Carvalho de Melo /** 664a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension - Base class for defining a chain of extensions 67e6aff9f8SArnaldo Carvalho de Melo * 68e6aff9f8SArnaldo Carvalho de Melo * Many interfaces need to grow over time. In most cases we can simply 69e6aff9f8SArnaldo Carvalho de Melo * extend the struct and have userspace pass in more data. Another option, 70e6aff9f8SArnaldo Carvalho de Melo * as demonstrated by Vulkan's approach to providing extensions for forward 71e6aff9f8SArnaldo Carvalho de Melo * and backward compatibility, is to use a list of optional structs to 72e6aff9f8SArnaldo Carvalho de Melo * provide those extra details. 73e6aff9f8SArnaldo Carvalho de Melo * 74e6aff9f8SArnaldo Carvalho de Melo * The key advantage to using an extension chain is that it allows us to 75e6aff9f8SArnaldo Carvalho de Melo * redefine the interface more easily than an ever growing struct of 76e6aff9f8SArnaldo Carvalho de Melo * increasing complexity, and for large parts of that interface to be 77e6aff9f8SArnaldo Carvalho de Melo * entirely optional. The downside is more pointer chasing; chasing across 78e6aff9f8SArnaldo Carvalho de Melo * the __user boundary with pointers encapsulated inside u64. 794a1cddeaSArnaldo Carvalho de Melo * 804a1cddeaSArnaldo Carvalho de Melo * Example chaining: 814a1cddeaSArnaldo Carvalho de Melo * 824a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 834a1cddeaSArnaldo Carvalho de Melo * 844a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension ext3 { 854a1cddeaSArnaldo Carvalho de Melo * .next_extension = 0, // end 864a1cddeaSArnaldo Carvalho de Melo * .name = ..., 874a1cddeaSArnaldo Carvalho de Melo * }; 884a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension ext2 { 894a1cddeaSArnaldo Carvalho de Melo * .next_extension = (uintptr_t)&ext3, 904a1cddeaSArnaldo Carvalho de Melo * .name = ..., 914a1cddeaSArnaldo Carvalho de Melo * }; 924a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension ext1 { 934a1cddeaSArnaldo Carvalho de Melo * .next_extension = (uintptr_t)&ext2, 944a1cddeaSArnaldo Carvalho de Melo * .name = ..., 954a1cddeaSArnaldo Carvalho de Melo * }; 964a1cddeaSArnaldo Carvalho de Melo * 974a1cddeaSArnaldo Carvalho de Melo * Typically the struct i915_user_extension would be embedded in some uAPI 984a1cddeaSArnaldo Carvalho de Melo * struct, and in this case we would feed it the head of the chain(i.e ext1), 994a1cddeaSArnaldo Carvalho de Melo * which would then apply all of the above extensions. 1004a1cddeaSArnaldo Carvalho de Melo * 101e6aff9f8SArnaldo Carvalho de Melo */ 102e6aff9f8SArnaldo Carvalho de Melo struct i915_user_extension { 1034a1cddeaSArnaldo Carvalho de Melo /** 1044a1cddeaSArnaldo Carvalho de Melo * @next_extension: 1054a1cddeaSArnaldo Carvalho de Melo * 1064a1cddeaSArnaldo Carvalho de Melo * Pointer to the next struct i915_user_extension, or zero if the end. 1074a1cddeaSArnaldo Carvalho de Melo */ 108e6aff9f8SArnaldo Carvalho de Melo __u64 next_extension; 1094a1cddeaSArnaldo Carvalho de Melo /** 1104a1cddeaSArnaldo Carvalho de Melo * @name: Name of the extension. 1114a1cddeaSArnaldo Carvalho de Melo * 1124a1cddeaSArnaldo Carvalho de Melo * Note that the name here is just some integer. 1134a1cddeaSArnaldo Carvalho de Melo * 1144a1cddeaSArnaldo Carvalho de Melo * Also note that the name space for this is not global for the whole 1154a1cddeaSArnaldo Carvalho de Melo * driver, but rather its scope/meaning is limited to the specific piece 1164a1cddeaSArnaldo Carvalho de Melo * of uAPI which has embedded the struct i915_user_extension. 1174a1cddeaSArnaldo Carvalho de Melo */ 118e6aff9f8SArnaldo Carvalho de Melo __u32 name; 1194a1cddeaSArnaldo Carvalho de Melo /** 1204a1cddeaSArnaldo Carvalho de Melo * @flags: MBZ 1214a1cddeaSArnaldo Carvalho de Melo * 1224a1cddeaSArnaldo Carvalho de Melo * All undefined bits must be zero. 1234a1cddeaSArnaldo Carvalho de Melo */ 1244a1cddeaSArnaldo Carvalho de Melo __u32 flags; 1254a1cddeaSArnaldo Carvalho de Melo /** 1264a1cddeaSArnaldo Carvalho de Melo * @rsvd: MBZ 1274a1cddeaSArnaldo Carvalho de Melo * 1284a1cddeaSArnaldo Carvalho de Melo * Reserved for future use; must be zero. 1294a1cddeaSArnaldo Carvalho de Melo */ 1304a1cddeaSArnaldo Carvalho de Melo __u32 rsvd[4]; 131e6aff9f8SArnaldo Carvalho de Melo }; 132e6aff9f8SArnaldo Carvalho de Melo 133e6aff9f8SArnaldo Carvalho de Melo /* 134c1737f2bSArnaldo Carvalho de Melo * MOCS indexes used for GPU surfaces, defining the cacheability of the 135c1737f2bSArnaldo Carvalho de Melo * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 136c1737f2bSArnaldo Carvalho de Melo */ 137c1737f2bSArnaldo Carvalho de Melo enum i915_mocs_table_index { 138c1737f2bSArnaldo Carvalho de Melo /* 139c1737f2bSArnaldo Carvalho de Melo * Not cached anywhere, coherency between CPU and GPU accesses is 140c1737f2bSArnaldo Carvalho de Melo * guaranteed. 141c1737f2bSArnaldo Carvalho de Melo */ 142c1737f2bSArnaldo Carvalho de Melo I915_MOCS_UNCACHED, 143c1737f2bSArnaldo Carvalho de Melo /* 144c1737f2bSArnaldo Carvalho de Melo * Cacheability and coherency controlled by the kernel automatically 145c1737f2bSArnaldo Carvalho de Melo * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 146c1737f2bSArnaldo Carvalho de Melo * usage of the surface (used for display scanout or not). 147c1737f2bSArnaldo Carvalho de Melo */ 148c1737f2bSArnaldo Carvalho de Melo I915_MOCS_PTE, 149c1737f2bSArnaldo Carvalho de Melo /* 150c1737f2bSArnaldo Carvalho de Melo * Cached in all GPU caches available on the platform. 151c1737f2bSArnaldo Carvalho de Melo * Coherency between CPU and GPU accesses to the surface is not 152c1737f2bSArnaldo Carvalho de Melo * guaranteed without extra synchronization. 153c1737f2bSArnaldo Carvalho de Melo */ 154c1737f2bSArnaldo Carvalho de Melo I915_MOCS_CACHED, 155c1737f2bSArnaldo Carvalho de Melo }; 156c1737f2bSArnaldo Carvalho de Melo 157f091f1d6SIngo Molnar /* 158f091f1d6SIngo Molnar * Different engines serve different roles, and there may be more than one 159f091f1d6SIngo Molnar * engine serving each role. enum drm_i915_gem_engine_class provides a 160f091f1d6SIngo Molnar * classification of the role of the engine, which may be used when requesting 161f091f1d6SIngo Molnar * operations to be performed on a certain subset of engines, or for providing 162f091f1d6SIngo Molnar * information about that group. 163f091f1d6SIngo Molnar */ 164f091f1d6SIngo Molnar enum drm_i915_gem_engine_class { 165f091f1d6SIngo Molnar I915_ENGINE_CLASS_RENDER = 0, 166f091f1d6SIngo Molnar I915_ENGINE_CLASS_COPY = 1, 167f091f1d6SIngo Molnar I915_ENGINE_CLASS_VIDEO = 2, 168f091f1d6SIngo Molnar I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 169f091f1d6SIngo Molnar 170e6aff9f8SArnaldo Carvalho de Melo /* should be kept compact */ 171e6aff9f8SArnaldo Carvalho de Melo 172f091f1d6SIngo Molnar I915_ENGINE_CLASS_INVALID = -1 173f091f1d6SIngo Molnar }; 174f091f1d6SIngo Molnar 175e6aff9f8SArnaldo Carvalho de Melo /* 176e6aff9f8SArnaldo Carvalho de Melo * There may be more than one engine fulfilling any role within the system. 177e6aff9f8SArnaldo Carvalho de Melo * Each engine of a class is given a unique instance number and therefore 178e6aff9f8SArnaldo Carvalho de Melo * any engine can be specified by its class:instance tuplet. APIs that allow 179e6aff9f8SArnaldo Carvalho de Melo * access to any engine in the system will use struct i915_engine_class_instance 180e6aff9f8SArnaldo Carvalho de Melo * for this identification. 181e6aff9f8SArnaldo Carvalho de Melo */ 182e6aff9f8SArnaldo Carvalho de Melo struct i915_engine_class_instance { 183e6aff9f8SArnaldo Carvalho de Melo __u16 engine_class; /* see enum drm_i915_gem_engine_class */ 184e6aff9f8SArnaldo Carvalho de Melo __u16 engine_instance; 18595dc663aSArnaldo Carvalho de Melo #define I915_ENGINE_CLASS_INVALID_NONE -1 18695dc663aSArnaldo Carvalho de Melo #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 187e6aff9f8SArnaldo Carvalho de Melo }; 188e6aff9f8SArnaldo Carvalho de Melo 189f091f1d6SIngo Molnar /** 190f091f1d6SIngo Molnar * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 191f091f1d6SIngo Molnar * 192f091f1d6SIngo Molnar */ 193f091f1d6SIngo Molnar 194f091f1d6SIngo Molnar enum drm_i915_pmu_engine_sample { 195f091f1d6SIngo Molnar I915_SAMPLE_BUSY = 0, 196f091f1d6SIngo Molnar I915_SAMPLE_WAIT = 1, 197f091f1d6SIngo Molnar I915_SAMPLE_SEMA = 2 198f091f1d6SIngo Molnar }; 199f091f1d6SIngo Molnar 200f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_BITS (4) 201f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_MASK (0xf) 202f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 203f091f1d6SIngo Molnar #define I915_PMU_CLASS_SHIFT \ 204f091f1d6SIngo Molnar (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 205f091f1d6SIngo Molnar 206f091f1d6SIngo Molnar #define __I915_PMU_ENGINE(class, instance, sample) \ 207f091f1d6SIngo Molnar ((class) << I915_PMU_CLASS_SHIFT | \ 208f091f1d6SIngo Molnar (instance) << I915_PMU_SAMPLE_BITS | \ 209f091f1d6SIngo Molnar (sample)) 210f091f1d6SIngo Molnar 211f091f1d6SIngo Molnar #define I915_PMU_ENGINE_BUSY(class, instance) \ 212f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 213f091f1d6SIngo Molnar 214f091f1d6SIngo Molnar #define I915_PMU_ENGINE_WAIT(class, instance) \ 215f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 216f091f1d6SIngo Molnar 217f091f1d6SIngo Molnar #define I915_PMU_ENGINE_SEMA(class, instance) \ 218f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 219f091f1d6SIngo Molnar 220f091f1d6SIngo Molnar #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 221f091f1d6SIngo Molnar 222f091f1d6SIngo Molnar #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 223f091f1d6SIngo Molnar #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 224f091f1d6SIngo Molnar #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 225f091f1d6SIngo Molnar #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 226c2446944SArnaldo Carvalho de Melo #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) 227f091f1d6SIngo Molnar 228c2446944SArnaldo Carvalho de Melo #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY 229f091f1d6SIngo Molnar 230c1737f2bSArnaldo Carvalho de Melo /* Each region is a minimum of 16k, and there are at most 255 of them. 231c1737f2bSArnaldo Carvalho de Melo */ 232c1737f2bSArnaldo Carvalho de Melo #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 233c1737f2bSArnaldo Carvalho de Melo * of chars for next/prev indices */ 234c1737f2bSArnaldo Carvalho de Melo #define I915_LOG_MIN_TEX_REGION_SIZE 14 235c1737f2bSArnaldo Carvalho de Melo 236c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_init { 237c1737f2bSArnaldo Carvalho de Melo enum { 238c1737f2bSArnaldo Carvalho de Melo I915_INIT_DMA = 0x01, 239c1737f2bSArnaldo Carvalho de Melo I915_CLEANUP_DMA = 0x02, 240c1737f2bSArnaldo Carvalho de Melo I915_RESUME_DMA = 0x03 241c1737f2bSArnaldo Carvalho de Melo } func; 242c1737f2bSArnaldo Carvalho de Melo unsigned int mmio_offset; 243c1737f2bSArnaldo Carvalho de Melo int sarea_priv_offset; 244c1737f2bSArnaldo Carvalho de Melo unsigned int ring_start; 245c1737f2bSArnaldo Carvalho de Melo unsigned int ring_end; 246c1737f2bSArnaldo Carvalho de Melo unsigned int ring_size; 247c1737f2bSArnaldo Carvalho de Melo unsigned int front_offset; 248c1737f2bSArnaldo Carvalho de Melo unsigned int back_offset; 249c1737f2bSArnaldo Carvalho de Melo unsigned int depth_offset; 250c1737f2bSArnaldo Carvalho de Melo unsigned int w; 251c1737f2bSArnaldo Carvalho de Melo unsigned int h; 252c1737f2bSArnaldo Carvalho de Melo unsigned int pitch; 253c1737f2bSArnaldo Carvalho de Melo unsigned int pitch_bits; 254c1737f2bSArnaldo Carvalho de Melo unsigned int back_pitch; 255c1737f2bSArnaldo Carvalho de Melo unsigned int depth_pitch; 256c1737f2bSArnaldo Carvalho de Melo unsigned int cpp; 257c1737f2bSArnaldo Carvalho de Melo unsigned int chipset; 258c1737f2bSArnaldo Carvalho de Melo } drm_i915_init_t; 259c1737f2bSArnaldo Carvalho de Melo 260c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_sarea { 261c1737f2bSArnaldo Carvalho de Melo struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 262c1737f2bSArnaldo Carvalho de Melo int last_upload; /* last time texture was uploaded */ 263c1737f2bSArnaldo Carvalho de Melo int last_enqueue; /* last time a buffer was enqueued */ 264c1737f2bSArnaldo Carvalho de Melo int last_dispatch; /* age of the most recently dispatched buffer */ 265c1737f2bSArnaldo Carvalho de Melo int ctxOwner; /* last context to upload state */ 266c1737f2bSArnaldo Carvalho de Melo int texAge; 267c1737f2bSArnaldo Carvalho de Melo int pf_enabled; /* is pageflipping allowed? */ 268c1737f2bSArnaldo Carvalho de Melo int pf_active; 269c1737f2bSArnaldo Carvalho de Melo int pf_current_page; /* which buffer is being displayed? */ 270c1737f2bSArnaldo Carvalho de Melo int perf_boxes; /* performance boxes to be displayed */ 271c1737f2bSArnaldo Carvalho de Melo int width, height; /* screen size in pixels */ 272c1737f2bSArnaldo Carvalho de Melo 273c1737f2bSArnaldo Carvalho de Melo drm_handle_t front_handle; 274c1737f2bSArnaldo Carvalho de Melo int front_offset; 275c1737f2bSArnaldo Carvalho de Melo int front_size; 276c1737f2bSArnaldo Carvalho de Melo 277c1737f2bSArnaldo Carvalho de Melo drm_handle_t back_handle; 278c1737f2bSArnaldo Carvalho de Melo int back_offset; 279c1737f2bSArnaldo Carvalho de Melo int back_size; 280c1737f2bSArnaldo Carvalho de Melo 281c1737f2bSArnaldo Carvalho de Melo drm_handle_t depth_handle; 282c1737f2bSArnaldo Carvalho de Melo int depth_offset; 283c1737f2bSArnaldo Carvalho de Melo int depth_size; 284c1737f2bSArnaldo Carvalho de Melo 285c1737f2bSArnaldo Carvalho de Melo drm_handle_t tex_handle; 286c1737f2bSArnaldo Carvalho de Melo int tex_offset; 287c1737f2bSArnaldo Carvalho de Melo int tex_size; 288c1737f2bSArnaldo Carvalho de Melo int log_tex_granularity; 289c1737f2bSArnaldo Carvalho de Melo int pitch; 290c1737f2bSArnaldo Carvalho de Melo int rotation; /* 0, 90, 180 or 270 */ 291c1737f2bSArnaldo Carvalho de Melo int rotated_offset; 292c1737f2bSArnaldo Carvalho de Melo int rotated_size; 293c1737f2bSArnaldo Carvalho de Melo int rotated_pitch; 294c1737f2bSArnaldo Carvalho de Melo int virtualX, virtualY; 295c1737f2bSArnaldo Carvalho de Melo 296c1737f2bSArnaldo Carvalho de Melo unsigned int front_tiled; 297c1737f2bSArnaldo Carvalho de Melo unsigned int back_tiled; 298c1737f2bSArnaldo Carvalho de Melo unsigned int depth_tiled; 299c1737f2bSArnaldo Carvalho de Melo unsigned int rotated_tiled; 300c1737f2bSArnaldo Carvalho de Melo unsigned int rotated2_tiled; 301c1737f2bSArnaldo Carvalho de Melo 302c1737f2bSArnaldo Carvalho de Melo int pipeA_x; 303c1737f2bSArnaldo Carvalho de Melo int pipeA_y; 304c1737f2bSArnaldo Carvalho de Melo int pipeA_w; 305c1737f2bSArnaldo Carvalho de Melo int pipeA_h; 306c1737f2bSArnaldo Carvalho de Melo int pipeB_x; 307c1737f2bSArnaldo Carvalho de Melo int pipeB_y; 308c1737f2bSArnaldo Carvalho de Melo int pipeB_w; 309c1737f2bSArnaldo Carvalho de Melo int pipeB_h; 310c1737f2bSArnaldo Carvalho de Melo 311c1737f2bSArnaldo Carvalho de Melo /* fill out some space for old userspace triple buffer */ 312c1737f2bSArnaldo Carvalho de Melo drm_handle_t unused_handle; 313c1737f2bSArnaldo Carvalho de Melo __u32 unused1, unused2, unused3; 314c1737f2bSArnaldo Carvalho de Melo 315c1737f2bSArnaldo Carvalho de Melo /* buffer object handles for static buffers. May change 316c1737f2bSArnaldo Carvalho de Melo * over the lifetime of the client. 317c1737f2bSArnaldo Carvalho de Melo */ 318c1737f2bSArnaldo Carvalho de Melo __u32 front_bo_handle; 319c1737f2bSArnaldo Carvalho de Melo __u32 back_bo_handle; 320c1737f2bSArnaldo Carvalho de Melo __u32 unused_bo_handle; 321c1737f2bSArnaldo Carvalho de Melo __u32 depth_bo_handle; 322c1737f2bSArnaldo Carvalho de Melo 323c1737f2bSArnaldo Carvalho de Melo } drm_i915_sarea_t; 324c1737f2bSArnaldo Carvalho de Melo 325c1737f2bSArnaldo Carvalho de Melo /* due to userspace building against these headers we need some compat here */ 326c1737f2bSArnaldo Carvalho de Melo #define planeA_x pipeA_x 327c1737f2bSArnaldo Carvalho de Melo #define planeA_y pipeA_y 328c1737f2bSArnaldo Carvalho de Melo #define planeA_w pipeA_w 329c1737f2bSArnaldo Carvalho de Melo #define planeA_h pipeA_h 330c1737f2bSArnaldo Carvalho de Melo #define planeB_x pipeB_x 331c1737f2bSArnaldo Carvalho de Melo #define planeB_y pipeB_y 332c1737f2bSArnaldo Carvalho de Melo #define planeB_w pipeB_w 333c1737f2bSArnaldo Carvalho de Melo #define planeB_h pipeB_h 334c1737f2bSArnaldo Carvalho de Melo 335c1737f2bSArnaldo Carvalho de Melo /* Flags for perf_boxes 336c1737f2bSArnaldo Carvalho de Melo */ 337c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_RING_EMPTY 0x1 338c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_FLIP 0x2 339c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_WAIT 0x4 340c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_TEXTURE_LOAD 0x8 341c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_LOST_CONTEXT 0x10 342c1737f2bSArnaldo Carvalho de Melo 343c1737f2bSArnaldo Carvalho de Melo /* 344c1737f2bSArnaldo Carvalho de Melo * i915 specific ioctls. 345c1737f2bSArnaldo Carvalho de Melo * 346c1737f2bSArnaldo Carvalho de Melo * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 347c1737f2bSArnaldo Carvalho de Melo * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 348c1737f2bSArnaldo Carvalho de Melo * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 349c1737f2bSArnaldo Carvalho de Melo */ 350c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_INIT 0x00 351c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FLUSH 0x01 352c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FLIP 0x02 353c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_BATCHBUFFER 0x03 354c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_IRQ_EMIT 0x04 355c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_IRQ_WAIT 0x05 356c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GETPARAM 0x06 357c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SETPARAM 0x07 358c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_ALLOC 0x08 359c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FREE 0x09 360c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_INIT_HEAP 0x0a 361c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_CMDBUFFER 0x0b 362c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_DESTROY_HEAP 0x0c 363c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SET_VBLANK_PIPE 0x0d 364c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_VBLANK_PIPE 0x0e 365c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_SWAP 0x0f 366c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_HWS_ADDR 0x11 367c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_INIT 0x13 368c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER 0x14 369c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PIN 0x15 370c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_UNPIN 0x16 371c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_BUSY 0x17 372c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_THROTTLE 0x18 373c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_ENTERVT 0x19 374c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_LEAVEVT 0x1a 375c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CREATE 0x1b 376c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PREAD 0x1c 377c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PWRITE 0x1d 378c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MMAP 0x1e 379c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_DOMAIN 0x1f 380c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SW_FINISH 0x20 381c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_TILING 0x21 382c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_TILING 0x22 383c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_APERTURE 0x23 384c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MMAP_GTT 0x24 385c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 386c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MADVISE 0x26 387c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 388c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_OVERLAY_ATTRS 0x28 389c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER2 0x29 390c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 391c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 392c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 393c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_WAIT 0x2c 394c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 395c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 396c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_CACHING 0x2f 397c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_CACHING 0x30 398c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_REG_READ 0x31 399c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_RESET_STATS 0x32 400c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_USERPTR 0x33 401c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 402c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 403c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_PERF_OPEN 0x36 404549a3976SIngo Molnar #define DRM_I915_PERF_ADD_CONFIG 0x37 405549a3976SIngo Molnar #define DRM_I915_PERF_REMOVE_CONFIG 0x38 40601f97511SArnaldo Carvalho de Melo #define DRM_I915_QUERY 0x39 40795dc663aSArnaldo Carvalho de Melo #define DRM_I915_GEM_VM_CREATE 0x3a 40895dc663aSArnaldo Carvalho de Melo #define DRM_I915_GEM_VM_DESTROY 0x3b 4094a1cddeaSArnaldo Carvalho de Melo #define DRM_I915_GEM_CREATE_EXT 0x3c 410e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes */ 411c1737f2bSArnaldo Carvalho de Melo 412c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 413c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 414c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 415c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 416c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 417c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 418c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 419c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 420c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 421c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 422c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 423c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 424c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 425c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 426c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 427c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 428c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 429c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 430c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 431c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 432c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 433c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 434c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 435c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 436c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 437c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 438c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 439c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 440c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 441c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 4424a1cddeaSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) 443c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 444c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 445c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 446c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 447365f9cc1SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 448c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 449c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 450c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 451c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 452c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 453c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 454c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 455c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 456c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 457c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 458c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 459c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 460c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 461e6aff9f8SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 462c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 463c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 464c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 465c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 466c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 467c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 468c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 469549a3976SIngo Molnar #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 470549a3976SIngo Molnar #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 47101f97511SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 47295dc663aSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 47395dc663aSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 474c1737f2bSArnaldo Carvalho de Melo 475c1737f2bSArnaldo Carvalho de Melo /* Allow drivers to submit batchbuffers directly to hardware, relying 476c1737f2bSArnaldo Carvalho de Melo * on the security mechanisms provided by hardware. 477c1737f2bSArnaldo Carvalho de Melo */ 478c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_batchbuffer { 479c1737f2bSArnaldo Carvalho de Melo int start; /* agp offset */ 480c1737f2bSArnaldo Carvalho de Melo int used; /* nr bytes in use */ 481c1737f2bSArnaldo Carvalho de Melo int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 482c1737f2bSArnaldo Carvalho de Melo int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 483c1737f2bSArnaldo Carvalho de Melo int num_cliprects; /* mulitpass with multiple cliprects? */ 484c1737f2bSArnaldo Carvalho de Melo struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 485c1737f2bSArnaldo Carvalho de Melo } drm_i915_batchbuffer_t; 486c1737f2bSArnaldo Carvalho de Melo 487c1737f2bSArnaldo Carvalho de Melo /* As above, but pass a pointer to userspace buffer which can be 488c1737f2bSArnaldo Carvalho de Melo * validated by the kernel prior to sending to hardware. 489c1737f2bSArnaldo Carvalho de Melo */ 490c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_cmdbuffer { 491c1737f2bSArnaldo Carvalho de Melo char __user *buf; /* pointer to userspace command buffer */ 492c1737f2bSArnaldo Carvalho de Melo int sz; /* nr bytes in buf */ 493c1737f2bSArnaldo Carvalho de Melo int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 494c1737f2bSArnaldo Carvalho de Melo int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 495c1737f2bSArnaldo Carvalho de Melo int num_cliprects; /* mulitpass with multiple cliprects? */ 496c1737f2bSArnaldo Carvalho de Melo struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 497c1737f2bSArnaldo Carvalho de Melo } drm_i915_cmdbuffer_t; 498c1737f2bSArnaldo Carvalho de Melo 499c1737f2bSArnaldo Carvalho de Melo /* Userspace can request & wait on irq's: 500c1737f2bSArnaldo Carvalho de Melo */ 501c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_irq_emit { 502c1737f2bSArnaldo Carvalho de Melo int __user *irq_seq; 503c1737f2bSArnaldo Carvalho de Melo } drm_i915_irq_emit_t; 504c1737f2bSArnaldo Carvalho de Melo 505c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_irq_wait { 506c1737f2bSArnaldo Carvalho de Melo int irq_seq; 507c1737f2bSArnaldo Carvalho de Melo } drm_i915_irq_wait_t; 508c1737f2bSArnaldo Carvalho de Melo 5098858ecb5SArnaldo Carvalho de Melo /* 5108858ecb5SArnaldo Carvalho de Melo * Different modes of per-process Graphics Translation Table, 5118858ecb5SArnaldo Carvalho de Melo * see I915_PARAM_HAS_ALIASING_PPGTT 5128858ecb5SArnaldo Carvalho de Melo */ 5138858ecb5SArnaldo Carvalho de Melo #define I915_GEM_PPGTT_NONE 0 5148858ecb5SArnaldo Carvalho de Melo #define I915_GEM_PPGTT_ALIASING 1 5158858ecb5SArnaldo Carvalho de Melo #define I915_GEM_PPGTT_FULL 2 5168858ecb5SArnaldo Carvalho de Melo 517c1737f2bSArnaldo Carvalho de Melo /* Ioctl to query kernel params: 518c1737f2bSArnaldo Carvalho de Melo */ 519c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_IRQ_ACTIVE 1 520c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_ALLOW_BATCHBUFFER 2 521c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_LAST_DISPATCH 3 522c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_CHIPSET_ID 4 523c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GEM 5 524c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_NUM_FENCES_AVAIL 6 525c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_OVERLAY 7 526c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PAGEFLIPPING 8 527c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXECBUF2 9 528c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BSD 10 529c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BLT 11 530c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RELAXED_FENCING 12 531c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_COHERENT_RINGS 13 532c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_CONSTANTS 14 533c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RELAXED_DELTA 15 534c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GEN7_SOL_RESET 16 535c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_LLC 17 536c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_ALIASING_PPGTT 18 537c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_WAIT_TIMEOUT 19 538c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SEMAPHORES 20 539c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 540c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_VEBOX 22 541c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SECURE_BATCHES 23 542c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PINNED_BATCHES 24 543c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_NO_RELOC 25 544c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 545c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_WT 27 546c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_CMD_PARSER_VERSION 28 547c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 548c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MMAP_VERSION 30 549c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BSD2 31 550c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_REVISION 32 551c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SUBSLICE_TOTAL 33 552c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_EU_TOTAL 34 553c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GPU_RESET 35 554c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RESOURCE_STREAMER 36 555c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_SOFTPIN 37 556c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_POOLED_EU 38 557c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MIN_EU_IN_POOL 39 558c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MMAP_GTT_VERSION 40 559c1737f2bSArnaldo Carvalho de Melo 560485be0cbSArnaldo Carvalho de Melo /* 561485be0cbSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 562c1737f2bSArnaldo Carvalho de Melo * priorities and the driver will attempt to execute batches in priority order. 563485be0cbSArnaldo Carvalho de Melo * The param returns a capability bitmask, nonzero implies that the scheduler 564485be0cbSArnaldo Carvalho de Melo * is enabled, with different features present according to the mask. 565485be0cbSArnaldo Carvalho de Melo * 566485be0cbSArnaldo Carvalho de Melo * The initial priority for each batch is supplied by the context and is 567485be0cbSArnaldo Carvalho de Melo * controlled via I915_CONTEXT_PARAM_PRIORITY. 568c1737f2bSArnaldo Carvalho de Melo */ 569c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SCHEDULER 41 570485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 571485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 572485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 573e6aff9f8SArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 57408a96a31SArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 575*4dc24d7cSArnaldo Carvalho de Melo /* 576*4dc24d7cSArnaldo Carvalho de Melo * Indicates the 2k user priority levels are statically mapped into 3 buckets as 577*4dc24d7cSArnaldo Carvalho de Melo * follows: 578*4dc24d7cSArnaldo Carvalho de Melo * 579*4dc24d7cSArnaldo Carvalho de Melo * -1k to -1 Low priority 580*4dc24d7cSArnaldo Carvalho de Melo * 0 Normal priority 581*4dc24d7cSArnaldo Carvalho de Melo * 1 to 1k Highest priority 582*4dc24d7cSArnaldo Carvalho de Melo */ 583*4dc24d7cSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) 584485be0cbSArnaldo Carvalho de Melo 585c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HUC_STATUS 42 586c1737f2bSArnaldo Carvalho de Melo 587c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 588c1737f2bSArnaldo Carvalho de Melo * synchronisation with implicit fencing on individual objects. 589c1737f2bSArnaldo Carvalho de Melo * See EXEC_OBJECT_ASYNC. 590c1737f2bSArnaldo Carvalho de Melo */ 591c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_ASYNC 43 592c1737f2bSArnaldo Carvalho de Melo 593c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 594c1737f2bSArnaldo Carvalho de Melo * both being able to pass in a sync_file fd to wait upon before executing, 595c1737f2bSArnaldo Carvalho de Melo * and being able to return a new sync_file fd that is signaled when the 596c1737f2bSArnaldo Carvalho de Melo * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 597c1737f2bSArnaldo Carvalho de Melo */ 598c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_FENCE 44 599c1737f2bSArnaldo Carvalho de Melo 600c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 601c1737f2bSArnaldo Carvalho de Melo * user specified bufffers for post-mortem debugging of GPU hangs. See 602c1737f2bSArnaldo Carvalho de Melo * EXEC_OBJECT_CAPTURE. 603c1737f2bSArnaldo Carvalho de Melo */ 604c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_CAPTURE 45 605c1737f2bSArnaldo Carvalho de Melo 606c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SLICE_MASK 46 607c1737f2bSArnaldo Carvalho de Melo 608c1737f2bSArnaldo Carvalho de Melo /* Assuming it's uniform for each slice, this queries the mask of subslices 609c1737f2bSArnaldo Carvalho de Melo * per-slice for this system. 610c1737f2bSArnaldo Carvalho de Melo */ 611c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SUBSLICE_MASK 47 612c1737f2bSArnaldo Carvalho de Melo 613c1737f2bSArnaldo Carvalho de Melo /* 614c1737f2bSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 615c1737f2bSArnaldo Carvalho de Melo * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 616c1737f2bSArnaldo Carvalho de Melo */ 617c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 618c1737f2bSArnaldo Carvalho de Melo 619549a3976SIngo Molnar /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 620549a3976SIngo Molnar * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 621549a3976SIngo Molnar */ 622549a3976SIngo Molnar #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 623549a3976SIngo Molnar 624f091f1d6SIngo Molnar /* 625f091f1d6SIngo Molnar * Query whether every context (both per-file default and user created) is 626f091f1d6SIngo Molnar * isolated (insofar as HW supports). If this parameter is not true, then 627f091f1d6SIngo Molnar * freshly created contexts may inherit values from an existing context, 628f091f1d6SIngo Molnar * rather than default HW values. If true, it also ensures (insofar as HW 629f091f1d6SIngo Molnar * supports) that all state set by this context will not leak to any other 630f091f1d6SIngo Molnar * context. 631f091f1d6SIngo Molnar * 632f091f1d6SIngo Molnar * As not every engine across every gen support contexts, the returned 633f091f1d6SIngo Molnar * value reports the support of context isolation for individual engines by 634f091f1d6SIngo Molnar * returning a bitmask of each engine class set to true if that class supports 635f091f1d6SIngo Molnar * isolation. 636f091f1d6SIngo Molnar */ 637f091f1d6SIngo Molnar #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 638f091f1d6SIngo Molnar 639f091f1d6SIngo Molnar /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 640f091f1d6SIngo Molnar * registers. This used to be fixed per platform but from CNL onwards, this 641f091f1d6SIngo Molnar * might vary depending on the parts. 642f091f1d6SIngo Molnar */ 643f091f1d6SIngo Molnar #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 644f091f1d6SIngo Molnar 64553f00f45SArnaldo Carvalho de Melo /* 64653f00f45SArnaldo Carvalho de Melo * Once upon a time we supposed that writes through the GGTT would be 64753f00f45SArnaldo Carvalho de Melo * immediately in physical memory (once flushed out of the CPU path). However, 64853f00f45SArnaldo Carvalho de Melo * on a few different processors and chipsets, this is not necessarily the case 64953f00f45SArnaldo Carvalho de Melo * as the writes appear to be buffered internally. Thus a read of the backing 65053f00f45SArnaldo Carvalho de Melo * storage (physical memory) via a different path (with different physical tags 65153f00f45SArnaldo Carvalho de Melo * to the indirect write via the GGTT) will see stale values from before 65253f00f45SArnaldo Carvalho de Melo * the GGTT write. Inside the kernel, we can for the most part keep track of 65353f00f45SArnaldo Carvalho de Melo * the different read/write domains in use (e.g. set-domain), but the assumption 65453f00f45SArnaldo Carvalho de Melo * of coherency is baked into the ABI, hence reporting its true state in this 65553f00f45SArnaldo Carvalho de Melo * parameter. 65653f00f45SArnaldo Carvalho de Melo * 65753f00f45SArnaldo Carvalho de Melo * Reports true when writes via mmap_gtt are immediately visible following an 65853f00f45SArnaldo Carvalho de Melo * lfence to flush the WCB. 65953f00f45SArnaldo Carvalho de Melo * 66053f00f45SArnaldo Carvalho de Melo * Reports false when writes via mmap_gtt are indeterminately delayed in an in 66153f00f45SArnaldo Carvalho de Melo * internal buffer and are _not_ immediately visible to third parties accessing 66253f00f45SArnaldo Carvalho de Melo * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC 66353f00f45SArnaldo Carvalho de Melo * communications channel when reporting false is strongly disadvised. 66453f00f45SArnaldo Carvalho de Melo */ 66553f00f45SArnaldo Carvalho de Melo #define I915_PARAM_MMAP_GTT_COHERENT 52 66653f00f45SArnaldo Carvalho de Melo 66795dc663aSArnaldo Carvalho de Melo /* 66895dc663aSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel 66995dc663aSArnaldo Carvalho de Melo * execution through use of explicit fence support. 67095dc663aSArnaldo Carvalho de Melo * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. 67195dc663aSArnaldo Carvalho de Melo */ 67295dc663aSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 6730b3fca6aSArnaldo Carvalho de Melo 6740b3fca6aSArnaldo Carvalho de Melo /* 6750b3fca6aSArnaldo Carvalho de Melo * Revision of the i915-perf uAPI. The value returned helps determine what 6760b3fca6aSArnaldo Carvalho de Melo * i915-perf features are available. See drm_i915_perf_property_id. 6770b3fca6aSArnaldo Carvalho de Melo */ 6780b3fca6aSArnaldo Carvalho de Melo #define I915_PARAM_PERF_REVISION 54 6790b3fca6aSArnaldo Carvalho de Melo 6809e228f48SArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 6819e228f48SArnaldo Carvalho de Melo * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See 6829e228f48SArnaldo Carvalho de Melo * I915_EXEC_USE_EXTENSIONS. 6839e228f48SArnaldo Carvalho de Melo */ 6849e228f48SArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 6859e228f48SArnaldo Carvalho de Melo 686*4dc24d7cSArnaldo Carvalho de Melo /* Query if the kernel supports the I915_USERPTR_PROBE flag. */ 687*4dc24d7cSArnaldo Carvalho de Melo #define I915_PARAM_HAS_USERPTR_PROBE 56 688*4dc24d7cSArnaldo Carvalho de Melo 689e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes and well documented */ 690e6aff9f8SArnaldo Carvalho de Melo 691c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_getparam { 692c1737f2bSArnaldo Carvalho de Melo __s32 param; 693c1737f2bSArnaldo Carvalho de Melo /* 694c1737f2bSArnaldo Carvalho de Melo * WARNING: Using pointers instead of fixed-size u64 means we need to write 695c1737f2bSArnaldo Carvalho de Melo * compat32 code. Don't repeat this mistake. 696c1737f2bSArnaldo Carvalho de Melo */ 697c1737f2bSArnaldo Carvalho de Melo int __user *value; 698c1737f2bSArnaldo Carvalho de Melo } drm_i915_getparam_t; 699c1737f2bSArnaldo Carvalho de Melo 700c1737f2bSArnaldo Carvalho de Melo /* Ioctl to set kernel params: 701c1737f2bSArnaldo Carvalho de Melo */ 702c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 703c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 704c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 705c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_NUM_USED_FENCES 4 706e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes */ 707c1737f2bSArnaldo Carvalho de Melo 708c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_setparam { 709c1737f2bSArnaldo Carvalho de Melo int param; 710c1737f2bSArnaldo Carvalho de Melo int value; 711c1737f2bSArnaldo Carvalho de Melo } drm_i915_setparam_t; 712c1737f2bSArnaldo Carvalho de Melo 713c1737f2bSArnaldo Carvalho de Melo /* A memory manager for regions of shared memory: 714c1737f2bSArnaldo Carvalho de Melo */ 715c1737f2bSArnaldo Carvalho de Melo #define I915_MEM_REGION_AGP 1 716c1737f2bSArnaldo Carvalho de Melo 717c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_alloc { 718c1737f2bSArnaldo Carvalho de Melo int region; 719c1737f2bSArnaldo Carvalho de Melo int alignment; 720c1737f2bSArnaldo Carvalho de Melo int size; 721c1737f2bSArnaldo Carvalho de Melo int __user *region_offset; /* offset from start of fb or agp */ 722c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_alloc_t; 723c1737f2bSArnaldo Carvalho de Melo 724c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_free { 725c1737f2bSArnaldo Carvalho de Melo int region; 726c1737f2bSArnaldo Carvalho de Melo int region_offset; 727c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_free_t; 728c1737f2bSArnaldo Carvalho de Melo 729c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_init_heap { 730c1737f2bSArnaldo Carvalho de Melo int region; 731c1737f2bSArnaldo Carvalho de Melo int size; 732c1737f2bSArnaldo Carvalho de Melo int start; 733c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_init_heap_t; 734c1737f2bSArnaldo Carvalho de Melo 735c1737f2bSArnaldo Carvalho de Melo /* Allow memory manager to be torn down and re-initialized (eg on 736c1737f2bSArnaldo Carvalho de Melo * rotate): 737c1737f2bSArnaldo Carvalho de Melo */ 738c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_destroy_heap { 739c1737f2bSArnaldo Carvalho de Melo int region; 740c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_destroy_heap_t; 741c1737f2bSArnaldo Carvalho de Melo 742c1737f2bSArnaldo Carvalho de Melo /* Allow X server to configure which pipes to monitor for vblank signals 743c1737f2bSArnaldo Carvalho de Melo */ 744c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_PIPE_A 1 745c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_PIPE_B 2 746c1737f2bSArnaldo Carvalho de Melo 747c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_vblank_pipe { 748c1737f2bSArnaldo Carvalho de Melo int pipe; 749c1737f2bSArnaldo Carvalho de Melo } drm_i915_vblank_pipe_t; 750c1737f2bSArnaldo Carvalho de Melo 751c1737f2bSArnaldo Carvalho de Melo /* Schedule buffer swap at given vertical blank: 752c1737f2bSArnaldo Carvalho de Melo */ 753c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_vblank_swap { 754c1737f2bSArnaldo Carvalho de Melo drm_drawable_t drawable; 755c1737f2bSArnaldo Carvalho de Melo enum drm_vblank_seq_type seqtype; 756c1737f2bSArnaldo Carvalho de Melo unsigned int sequence; 757c1737f2bSArnaldo Carvalho de Melo } drm_i915_vblank_swap_t; 758c1737f2bSArnaldo Carvalho de Melo 759c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_hws_addr { 760c1737f2bSArnaldo Carvalho de Melo __u64 addr; 761c1737f2bSArnaldo Carvalho de Melo } drm_i915_hws_addr_t; 762c1737f2bSArnaldo Carvalho de Melo 763c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_init { 764c1737f2bSArnaldo Carvalho de Melo /** 765c1737f2bSArnaldo Carvalho de Melo * Beginning offset in the GTT to be managed by the DRM memory 766c1737f2bSArnaldo Carvalho de Melo * manager. 767c1737f2bSArnaldo Carvalho de Melo */ 768c1737f2bSArnaldo Carvalho de Melo __u64 gtt_start; 769c1737f2bSArnaldo Carvalho de Melo /** 770c1737f2bSArnaldo Carvalho de Melo * Ending offset in the GTT to be managed by the DRM memory 771c1737f2bSArnaldo Carvalho de Melo * manager. 772c1737f2bSArnaldo Carvalho de Melo */ 773c1737f2bSArnaldo Carvalho de Melo __u64 gtt_end; 774c1737f2bSArnaldo Carvalho de Melo }; 775c1737f2bSArnaldo Carvalho de Melo 776c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_create { 777c1737f2bSArnaldo Carvalho de Melo /** 778c1737f2bSArnaldo Carvalho de Melo * Requested size for the object. 779c1737f2bSArnaldo Carvalho de Melo * 780c1737f2bSArnaldo Carvalho de Melo * The (page-aligned) allocated size for the object will be returned. 781c1737f2bSArnaldo Carvalho de Melo */ 782c1737f2bSArnaldo Carvalho de Melo __u64 size; 783c1737f2bSArnaldo Carvalho de Melo /** 784c1737f2bSArnaldo Carvalho de Melo * Returned handle for the object. 785c1737f2bSArnaldo Carvalho de Melo * 786c1737f2bSArnaldo Carvalho de Melo * Object handles are nonzero. 787c1737f2bSArnaldo Carvalho de Melo */ 788c1737f2bSArnaldo Carvalho de Melo __u32 handle; 789c1737f2bSArnaldo Carvalho de Melo __u32 pad; 790c1737f2bSArnaldo Carvalho de Melo }; 791c1737f2bSArnaldo Carvalho de Melo 792c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pread { 793c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being read. */ 794c1737f2bSArnaldo Carvalho de Melo __u32 handle; 795c1737f2bSArnaldo Carvalho de Melo __u32 pad; 796c1737f2bSArnaldo Carvalho de Melo /** Offset into the object to read from */ 797c1737f2bSArnaldo Carvalho de Melo __u64 offset; 798c1737f2bSArnaldo Carvalho de Melo /** Length of data to read */ 799c1737f2bSArnaldo Carvalho de Melo __u64 size; 800c1737f2bSArnaldo Carvalho de Melo /** 801c1737f2bSArnaldo Carvalho de Melo * Pointer to write the data into. 802c1737f2bSArnaldo Carvalho de Melo * 803c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 804c1737f2bSArnaldo Carvalho de Melo */ 805c1737f2bSArnaldo Carvalho de Melo __u64 data_ptr; 806c1737f2bSArnaldo Carvalho de Melo }; 807c1737f2bSArnaldo Carvalho de Melo 808c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pwrite { 809c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being written to. */ 810c1737f2bSArnaldo Carvalho de Melo __u32 handle; 811c1737f2bSArnaldo Carvalho de Melo __u32 pad; 812c1737f2bSArnaldo Carvalho de Melo /** Offset into the object to write to */ 813c1737f2bSArnaldo Carvalho de Melo __u64 offset; 814c1737f2bSArnaldo Carvalho de Melo /** Length of data to write */ 815c1737f2bSArnaldo Carvalho de Melo __u64 size; 816c1737f2bSArnaldo Carvalho de Melo /** 817c1737f2bSArnaldo Carvalho de Melo * Pointer to read the data from. 818c1737f2bSArnaldo Carvalho de Melo * 819c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 820c1737f2bSArnaldo Carvalho de Melo */ 821c1737f2bSArnaldo Carvalho de Melo __u64 data_ptr; 822c1737f2bSArnaldo Carvalho de Melo }; 823c1737f2bSArnaldo Carvalho de Melo 824c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_mmap { 825c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being mapped. */ 826c1737f2bSArnaldo Carvalho de Melo __u32 handle; 827c1737f2bSArnaldo Carvalho de Melo __u32 pad; 828c1737f2bSArnaldo Carvalho de Melo /** Offset in the object to map. */ 829c1737f2bSArnaldo Carvalho de Melo __u64 offset; 830c1737f2bSArnaldo Carvalho de Melo /** 831c1737f2bSArnaldo Carvalho de Melo * Length of data to map. 832c1737f2bSArnaldo Carvalho de Melo * 833c1737f2bSArnaldo Carvalho de Melo * The value will be page-aligned. 834c1737f2bSArnaldo Carvalho de Melo */ 835c1737f2bSArnaldo Carvalho de Melo __u64 size; 836c1737f2bSArnaldo Carvalho de Melo /** 837c1737f2bSArnaldo Carvalho de Melo * Returned pointer the data was mapped at. 838c1737f2bSArnaldo Carvalho de Melo * 839c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 840c1737f2bSArnaldo Carvalho de Melo */ 841c1737f2bSArnaldo Carvalho de Melo __u64 addr_ptr; 842c1737f2bSArnaldo Carvalho de Melo 843c1737f2bSArnaldo Carvalho de Melo /** 844c1737f2bSArnaldo Carvalho de Melo * Flags for extended behaviour. 845c1737f2bSArnaldo Carvalho de Melo * 846c1737f2bSArnaldo Carvalho de Melo * Added in version 2. 847c1737f2bSArnaldo Carvalho de Melo */ 848c1737f2bSArnaldo Carvalho de Melo __u64 flags; 849c1737f2bSArnaldo Carvalho de Melo #define I915_MMAP_WC 0x1 850c1737f2bSArnaldo Carvalho de Melo }; 851c1737f2bSArnaldo Carvalho de Melo 852c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_mmap_gtt { 853c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being mapped. */ 854c1737f2bSArnaldo Carvalho de Melo __u32 handle; 855c1737f2bSArnaldo Carvalho de Melo __u32 pad; 856c1737f2bSArnaldo Carvalho de Melo /** 857c1737f2bSArnaldo Carvalho de Melo * Fake offset to use for subsequent mmap call 858c1737f2bSArnaldo Carvalho de Melo * 859c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 860c1737f2bSArnaldo Carvalho de Melo */ 861c1737f2bSArnaldo Carvalho de Melo __u64 offset; 862c1737f2bSArnaldo Carvalho de Melo }; 863c1737f2bSArnaldo Carvalho de Melo 864*4dc24d7cSArnaldo Carvalho de Melo /** 865*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object. 866*4dc24d7cSArnaldo Carvalho de Melo * 867*4dc24d7cSArnaldo Carvalho de Melo * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, 868*4dc24d7cSArnaldo Carvalho de Melo * and is used to retrieve the fake offset to mmap an object specified by &handle. 869*4dc24d7cSArnaldo Carvalho de Melo * 870*4dc24d7cSArnaldo Carvalho de Melo * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. 871*4dc24d7cSArnaldo Carvalho de Melo * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave 872*4dc24d7cSArnaldo Carvalho de Melo * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`. 873*4dc24d7cSArnaldo Carvalho de Melo */ 874365f9cc1SArnaldo Carvalho de Melo struct drm_i915_gem_mmap_offset { 875*4dc24d7cSArnaldo Carvalho de Melo /** @handle: Handle for the object being mapped. */ 876365f9cc1SArnaldo Carvalho de Melo __u32 handle; 877*4dc24d7cSArnaldo Carvalho de Melo /** @pad: Must be zero */ 878365f9cc1SArnaldo Carvalho de Melo __u32 pad; 879365f9cc1SArnaldo Carvalho de Melo /** 880*4dc24d7cSArnaldo Carvalho de Melo * @offset: The fake offset to use for subsequent mmap call 881365f9cc1SArnaldo Carvalho de Melo * 882365f9cc1SArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 883365f9cc1SArnaldo Carvalho de Melo */ 884365f9cc1SArnaldo Carvalho de Melo __u64 offset; 885365f9cc1SArnaldo Carvalho de Melo 886365f9cc1SArnaldo Carvalho de Melo /** 887*4dc24d7cSArnaldo Carvalho de Melo * @flags: Flags for extended behaviour. 888365f9cc1SArnaldo Carvalho de Melo * 889*4dc24d7cSArnaldo Carvalho de Melo * It is mandatory that one of the `MMAP_OFFSET` types 890*4dc24d7cSArnaldo Carvalho de Melo * should be included: 891*4dc24d7cSArnaldo Carvalho de Melo * 892*4dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) 893*4dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. 894*4dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. 895*4dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. 896*4dc24d7cSArnaldo Carvalho de Melo * 897*4dc24d7cSArnaldo Carvalho de Melo * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid 898*4dc24d7cSArnaldo Carvalho de Melo * type. On devices without local memory, this caching mode is invalid. 899*4dc24d7cSArnaldo Carvalho de Melo * 900*4dc24d7cSArnaldo Carvalho de Melo * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will 901*4dc24d7cSArnaldo Carvalho de Melo * be used, depending on the object placement on creation. WB will be used 902*4dc24d7cSArnaldo Carvalho de Melo * when the object can only exist in system memory, WC otherwise. 903365f9cc1SArnaldo Carvalho de Melo */ 904365f9cc1SArnaldo Carvalho de Melo __u64 flags; 905*4dc24d7cSArnaldo Carvalho de Melo 906365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_GTT 0 907365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_WC 1 908365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_WB 2 909365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_UC 3 910*4dc24d7cSArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_FIXED 4 911365f9cc1SArnaldo Carvalho de Melo 912*4dc24d7cSArnaldo Carvalho de Melo /** 913*4dc24d7cSArnaldo Carvalho de Melo * @extensions: Zero-terminated chain of extensions. 914365f9cc1SArnaldo Carvalho de Melo * 915365f9cc1SArnaldo Carvalho de Melo * No current extensions defined; mbz. 916365f9cc1SArnaldo Carvalho de Melo */ 917365f9cc1SArnaldo Carvalho de Melo __u64 extensions; 918365f9cc1SArnaldo Carvalho de Melo }; 919365f9cc1SArnaldo Carvalho de Melo 920*4dc24d7cSArnaldo Carvalho de Melo /** 921*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in 922*4dc24d7cSArnaldo Carvalho de Melo * preparation for accessing the pages via some CPU domain. 923*4dc24d7cSArnaldo Carvalho de Melo * 924*4dc24d7cSArnaldo Carvalho de Melo * Specifying a new write or read domain will flush the object out of the 925*4dc24d7cSArnaldo Carvalho de Melo * previous domain(if required), before then updating the objects domain 926*4dc24d7cSArnaldo Carvalho de Melo * tracking with the new domain. 927*4dc24d7cSArnaldo Carvalho de Melo * 928*4dc24d7cSArnaldo Carvalho de Melo * Note this might involve waiting for the object first if it is still active on 929*4dc24d7cSArnaldo Carvalho de Melo * the GPU. 930*4dc24d7cSArnaldo Carvalho de Melo * 931*4dc24d7cSArnaldo Carvalho de Melo * Supported values for @read_domains and @write_domain: 932*4dc24d7cSArnaldo Carvalho de Melo * 933*4dc24d7cSArnaldo Carvalho de Melo * - I915_GEM_DOMAIN_WC: Uncached write-combined domain 934*4dc24d7cSArnaldo Carvalho de Melo * - I915_GEM_DOMAIN_CPU: CPU cache domain 935*4dc24d7cSArnaldo Carvalho de Melo * - I915_GEM_DOMAIN_GTT: Mappable aperture domain 936*4dc24d7cSArnaldo Carvalho de Melo * 937*4dc24d7cSArnaldo Carvalho de Melo * All other domains are rejected. 938*4dc24d7cSArnaldo Carvalho de Melo * 939*4dc24d7cSArnaldo Carvalho de Melo * Note that for discrete, starting from DG1, this is no longer supported, and 940*4dc24d7cSArnaldo Carvalho de Melo * is instead rejected. On such platforms the CPU domain is effectively static, 941*4dc24d7cSArnaldo Carvalho de Melo * where we also only support a single &drm_i915_gem_mmap_offset cache mode, 942*4dc24d7cSArnaldo Carvalho de Melo * which can't be set explicitly and instead depends on the object placements, 943*4dc24d7cSArnaldo Carvalho de Melo * as per the below. 944*4dc24d7cSArnaldo Carvalho de Melo * 945*4dc24d7cSArnaldo Carvalho de Melo * Implicit caching rules, starting from DG1: 946*4dc24d7cSArnaldo Carvalho de Melo * 947*4dc24d7cSArnaldo Carvalho de Melo * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 948*4dc24d7cSArnaldo Carvalho de Melo * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 949*4dc24d7cSArnaldo Carvalho de Melo * mapped as write-combined only. 950*4dc24d7cSArnaldo Carvalho de Melo * 951*4dc24d7cSArnaldo Carvalho de Melo * - Everything else is always allocated and mapped as write-back, with the 952*4dc24d7cSArnaldo Carvalho de Melo * guarantee that everything is also coherent with the GPU. 953*4dc24d7cSArnaldo Carvalho de Melo * 954*4dc24d7cSArnaldo Carvalho de Melo * Note that this is likely to change in the future again, where we might need 955*4dc24d7cSArnaldo Carvalho de Melo * more flexibility on future devices, so making this all explicit as part of a 956*4dc24d7cSArnaldo Carvalho de Melo * new &drm_i915_gem_create_ext extension is probable. 957*4dc24d7cSArnaldo Carvalho de Melo */ 958c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_set_domain { 959*4dc24d7cSArnaldo Carvalho de Melo /** @handle: Handle for the object. */ 960c1737f2bSArnaldo Carvalho de Melo __u32 handle; 961c1737f2bSArnaldo Carvalho de Melo 962*4dc24d7cSArnaldo Carvalho de Melo /** @read_domains: New read domains. */ 963c1737f2bSArnaldo Carvalho de Melo __u32 read_domains; 964c1737f2bSArnaldo Carvalho de Melo 965*4dc24d7cSArnaldo Carvalho de Melo /** 966*4dc24d7cSArnaldo Carvalho de Melo * @write_domain: New write domain. 967*4dc24d7cSArnaldo Carvalho de Melo * 968*4dc24d7cSArnaldo Carvalho de Melo * Note that having something in the write domain implies it's in the 969*4dc24d7cSArnaldo Carvalho de Melo * read domain, and only that read domain. 970*4dc24d7cSArnaldo Carvalho de Melo */ 971c1737f2bSArnaldo Carvalho de Melo __u32 write_domain; 972c1737f2bSArnaldo Carvalho de Melo }; 973c1737f2bSArnaldo Carvalho de Melo 974c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_sw_finish { 975c1737f2bSArnaldo Carvalho de Melo /** Handle for the object */ 976c1737f2bSArnaldo Carvalho de Melo __u32 handle; 977c1737f2bSArnaldo Carvalho de Melo }; 978c1737f2bSArnaldo Carvalho de Melo 979c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_relocation_entry { 980c1737f2bSArnaldo Carvalho de Melo /** 981c1737f2bSArnaldo Carvalho de Melo * Handle of the buffer being pointed to by this relocation entry. 982c1737f2bSArnaldo Carvalho de Melo * 983c1737f2bSArnaldo Carvalho de Melo * It's appealing to make this be an index into the mm_validate_entry 984c1737f2bSArnaldo Carvalho de Melo * list to refer to the buffer, but this allows the driver to create 985c1737f2bSArnaldo Carvalho de Melo * a relocation list for state buffers and not re-write it per 986c1737f2bSArnaldo Carvalho de Melo * exec using the buffer. 987c1737f2bSArnaldo Carvalho de Melo */ 988c1737f2bSArnaldo Carvalho de Melo __u32 target_handle; 989c1737f2bSArnaldo Carvalho de Melo 990c1737f2bSArnaldo Carvalho de Melo /** 991c1737f2bSArnaldo Carvalho de Melo * Value to be added to the offset of the target buffer to make up 992c1737f2bSArnaldo Carvalho de Melo * the relocation entry. 993c1737f2bSArnaldo Carvalho de Melo */ 994c1737f2bSArnaldo Carvalho de Melo __u32 delta; 995c1737f2bSArnaldo Carvalho de Melo 996c1737f2bSArnaldo Carvalho de Melo /** Offset in the buffer the relocation entry will be written into */ 997c1737f2bSArnaldo Carvalho de Melo __u64 offset; 998c1737f2bSArnaldo Carvalho de Melo 999c1737f2bSArnaldo Carvalho de Melo /** 1000c1737f2bSArnaldo Carvalho de Melo * Offset value of the target buffer that the relocation entry was last 1001c1737f2bSArnaldo Carvalho de Melo * written as. 1002c1737f2bSArnaldo Carvalho de Melo * 1003c1737f2bSArnaldo Carvalho de Melo * If the buffer has the same offset as last time, we can skip syncing 1004c1737f2bSArnaldo Carvalho de Melo * and writing the relocation. This value is written back out by 1005c1737f2bSArnaldo Carvalho de Melo * the execbuffer ioctl when the relocation is written. 1006c1737f2bSArnaldo Carvalho de Melo */ 1007c1737f2bSArnaldo Carvalho de Melo __u64 presumed_offset; 1008c1737f2bSArnaldo Carvalho de Melo 1009c1737f2bSArnaldo Carvalho de Melo /** 1010c1737f2bSArnaldo Carvalho de Melo * Target memory domains read by this operation. 1011c1737f2bSArnaldo Carvalho de Melo */ 1012c1737f2bSArnaldo Carvalho de Melo __u32 read_domains; 1013c1737f2bSArnaldo Carvalho de Melo 1014c1737f2bSArnaldo Carvalho de Melo /** 1015c1737f2bSArnaldo Carvalho de Melo * Target memory domains written by this operation. 1016c1737f2bSArnaldo Carvalho de Melo * 1017c1737f2bSArnaldo Carvalho de Melo * Note that only one domain may be written by the whole 1018c1737f2bSArnaldo Carvalho de Melo * execbuffer operation, so that where there are conflicts, 1019c1737f2bSArnaldo Carvalho de Melo * the application will get -EINVAL back. 1020c1737f2bSArnaldo Carvalho de Melo */ 1021c1737f2bSArnaldo Carvalho de Melo __u32 write_domain; 1022c1737f2bSArnaldo Carvalho de Melo }; 1023c1737f2bSArnaldo Carvalho de Melo 1024c1737f2bSArnaldo Carvalho de Melo /** @{ 1025c1737f2bSArnaldo Carvalho de Melo * Intel memory domains 1026c1737f2bSArnaldo Carvalho de Melo * 1027c1737f2bSArnaldo Carvalho de Melo * Most of these just align with the various caches in 1028c1737f2bSArnaldo Carvalho de Melo * the system and are used to flush and invalidate as 1029c1737f2bSArnaldo Carvalho de Melo * objects end up cached in different domains. 1030c1737f2bSArnaldo Carvalho de Melo */ 1031c1737f2bSArnaldo Carvalho de Melo /** CPU cache */ 1032c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_CPU 0x00000001 1033c1737f2bSArnaldo Carvalho de Melo /** Render cache, used by 2D and 3D drawing */ 1034c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_RENDER 0x00000002 1035c1737f2bSArnaldo Carvalho de Melo /** Sampler cache, used by texture engine */ 1036c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_SAMPLER 0x00000004 1037c1737f2bSArnaldo Carvalho de Melo /** Command queue, used to load batch buffers */ 1038c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_COMMAND 0x00000008 1039c1737f2bSArnaldo Carvalho de Melo /** Instruction cache, used by shader programs */ 1040c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 1041c1737f2bSArnaldo Carvalho de Melo /** Vertex address cache */ 1042c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_VERTEX 0x00000020 1043c1737f2bSArnaldo Carvalho de Melo /** GTT domain - aperture and scanout */ 1044c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_GTT 0x00000040 1045c1737f2bSArnaldo Carvalho de Melo /** WC domain - uncached access */ 1046c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_WC 0x00000080 1047c1737f2bSArnaldo Carvalho de Melo /** @} */ 1048c1737f2bSArnaldo Carvalho de Melo 1049c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_exec_object { 1050c1737f2bSArnaldo Carvalho de Melo /** 1051c1737f2bSArnaldo Carvalho de Melo * User's handle for a buffer to be bound into the GTT for this 1052c1737f2bSArnaldo Carvalho de Melo * operation. 1053c1737f2bSArnaldo Carvalho de Melo */ 1054c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1055c1737f2bSArnaldo Carvalho de Melo 1056c1737f2bSArnaldo Carvalho de Melo /** Number of relocations to be performed on this buffer */ 1057c1737f2bSArnaldo Carvalho de Melo __u32 relocation_count; 1058c1737f2bSArnaldo Carvalho de Melo /** 1059c1737f2bSArnaldo Carvalho de Melo * Pointer to array of struct drm_i915_gem_relocation_entry containing 1060c1737f2bSArnaldo Carvalho de Melo * the relocations to be performed in this buffer. 1061c1737f2bSArnaldo Carvalho de Melo */ 1062c1737f2bSArnaldo Carvalho de Melo __u64 relocs_ptr; 1063c1737f2bSArnaldo Carvalho de Melo 1064c1737f2bSArnaldo Carvalho de Melo /** Required alignment in graphics aperture */ 1065c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1066c1737f2bSArnaldo Carvalho de Melo 1067c1737f2bSArnaldo Carvalho de Melo /** 1068c1737f2bSArnaldo Carvalho de Melo * Returned value of the updated offset of the object, for future 1069c1737f2bSArnaldo Carvalho de Melo * presumed_offset writes. 1070c1737f2bSArnaldo Carvalho de Melo */ 1071c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1072c1737f2bSArnaldo Carvalho de Melo }; 1073c1737f2bSArnaldo Carvalho de Melo 10740fdee797SArnaldo Carvalho de Melo /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */ 1075c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer { 1076c1737f2bSArnaldo Carvalho de Melo /** 1077c1737f2bSArnaldo Carvalho de Melo * List of buffers to be validated with their relocations to be 1078c1737f2bSArnaldo Carvalho de Melo * performend on them. 1079c1737f2bSArnaldo Carvalho de Melo * 1080c1737f2bSArnaldo Carvalho de Melo * This is a pointer to an array of struct drm_i915_gem_validate_entry. 1081c1737f2bSArnaldo Carvalho de Melo * 1082c1737f2bSArnaldo Carvalho de Melo * These buffers must be listed in an order such that all relocations 1083c1737f2bSArnaldo Carvalho de Melo * a buffer is performing refer to buffers that have already appeared 1084c1737f2bSArnaldo Carvalho de Melo * in the validate list. 1085c1737f2bSArnaldo Carvalho de Melo */ 1086c1737f2bSArnaldo Carvalho de Melo __u64 buffers_ptr; 1087c1737f2bSArnaldo Carvalho de Melo __u32 buffer_count; 1088c1737f2bSArnaldo Carvalho de Melo 1089c1737f2bSArnaldo Carvalho de Melo /** Offset in the batchbuffer to start execution from. */ 1090c1737f2bSArnaldo Carvalho de Melo __u32 batch_start_offset; 1091c1737f2bSArnaldo Carvalho de Melo /** Bytes used in batchbuffer from batch_start_offset */ 1092c1737f2bSArnaldo Carvalho de Melo __u32 batch_len; 1093c1737f2bSArnaldo Carvalho de Melo __u32 DR1; 1094c1737f2bSArnaldo Carvalho de Melo __u32 DR4; 1095c1737f2bSArnaldo Carvalho de Melo __u32 num_cliprects; 1096c1737f2bSArnaldo Carvalho de Melo /** This is a struct drm_clip_rect *cliprects */ 1097c1737f2bSArnaldo Carvalho de Melo __u64 cliprects_ptr; 1098c1737f2bSArnaldo Carvalho de Melo }; 1099c1737f2bSArnaldo Carvalho de Melo 1100c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_exec_object2 { 1101c1737f2bSArnaldo Carvalho de Melo /** 1102c1737f2bSArnaldo Carvalho de Melo * User's handle for a buffer to be bound into the GTT for this 1103c1737f2bSArnaldo Carvalho de Melo * operation. 1104c1737f2bSArnaldo Carvalho de Melo */ 1105c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1106c1737f2bSArnaldo Carvalho de Melo 1107c1737f2bSArnaldo Carvalho de Melo /** Number of relocations to be performed on this buffer */ 1108c1737f2bSArnaldo Carvalho de Melo __u32 relocation_count; 1109c1737f2bSArnaldo Carvalho de Melo /** 1110c1737f2bSArnaldo Carvalho de Melo * Pointer to array of struct drm_i915_gem_relocation_entry containing 1111c1737f2bSArnaldo Carvalho de Melo * the relocations to be performed in this buffer. 1112c1737f2bSArnaldo Carvalho de Melo */ 1113c1737f2bSArnaldo Carvalho de Melo __u64 relocs_ptr; 1114c1737f2bSArnaldo Carvalho de Melo 1115c1737f2bSArnaldo Carvalho de Melo /** Required alignment in graphics aperture */ 1116c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1117c1737f2bSArnaldo Carvalho de Melo 1118c1737f2bSArnaldo Carvalho de Melo /** 1119c1737f2bSArnaldo Carvalho de Melo * When the EXEC_OBJECT_PINNED flag is specified this is populated by 1120c1737f2bSArnaldo Carvalho de Melo * the user with the GTT offset at which this object will be pinned. 1121c1737f2bSArnaldo Carvalho de Melo * When the I915_EXEC_NO_RELOC flag is specified this must contain the 1122c1737f2bSArnaldo Carvalho de Melo * presumed_offset of the object. 1123c1737f2bSArnaldo Carvalho de Melo * During execbuffer2 the kernel populates it with the value of the 1124c1737f2bSArnaldo Carvalho de Melo * current GTT offset of the object, for future presumed_offset writes. 1125c1737f2bSArnaldo Carvalho de Melo */ 1126c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1127c1737f2bSArnaldo Carvalho de Melo 1128c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 1129c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_NEEDS_GTT (1<<1) 1130c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_WRITE (1<<2) 1131c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 1132c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_PINNED (1<<4) 1133c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 1134c1737f2bSArnaldo Carvalho de Melo /* The kernel implicitly tracks GPU activity on all GEM objects, and 1135c1737f2bSArnaldo Carvalho de Melo * synchronises operations with outstanding rendering. This includes 1136c1737f2bSArnaldo Carvalho de Melo * rendering on other devices if exported via dma-buf. However, sometimes 1137c1737f2bSArnaldo Carvalho de Melo * this tracking is too coarse and the user knows better. For example, 1138c1737f2bSArnaldo Carvalho de Melo * if the object is split into non-overlapping ranges shared between different 1139c1737f2bSArnaldo Carvalho de Melo * clients or engines (i.e. suballocating objects), the implicit tracking 1140c1737f2bSArnaldo Carvalho de Melo * by kernel assumes that each operation affects the whole object rather 1141c1737f2bSArnaldo Carvalho de Melo * than an individual range, causing needless synchronisation between clients. 1142c1737f2bSArnaldo Carvalho de Melo * The kernel will also forgo any CPU cache flushes prior to rendering from 1143c1737f2bSArnaldo Carvalho de Melo * the object as the client is expected to be also handling such domain 1144c1737f2bSArnaldo Carvalho de Melo * tracking. 1145c1737f2bSArnaldo Carvalho de Melo * 1146c1737f2bSArnaldo Carvalho de Melo * The kernel maintains the implicit tracking in order to manage resources 1147c1737f2bSArnaldo Carvalho de Melo * used by the GPU - this flag only disables the synchronisation prior to 1148c1737f2bSArnaldo Carvalho de Melo * rendering with this object in this execbuf. 1149c1737f2bSArnaldo Carvalho de Melo * 1150c1737f2bSArnaldo Carvalho de Melo * Opting out of implicit synhronisation requires the user to do its own 1151c1737f2bSArnaldo Carvalho de Melo * explicit tracking to avoid rendering corruption. See, for example, 1152c1737f2bSArnaldo Carvalho de Melo * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 1153c1737f2bSArnaldo Carvalho de Melo */ 1154c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_ASYNC (1<<6) 1155c1737f2bSArnaldo Carvalho de Melo /* Request that the contents of this execobject be copied into the error 1156c1737f2bSArnaldo Carvalho de Melo * state upon a GPU hang involving this batch for post-mortem debugging. 1157c1737f2bSArnaldo Carvalho de Melo * These buffers are recorded in no particular order as "user" in 1158c1737f2bSArnaldo Carvalho de Melo * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 1159c1737f2bSArnaldo Carvalho de Melo * if the kernel supports this flag. 1160c1737f2bSArnaldo Carvalho de Melo */ 1161c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_CAPTURE (1<<7) 1162c1737f2bSArnaldo Carvalho de Melo /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 1163c1737f2bSArnaldo Carvalho de Melo #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 1164c1737f2bSArnaldo Carvalho de Melo __u64 flags; 1165c1737f2bSArnaldo Carvalho de Melo 1166c1737f2bSArnaldo Carvalho de Melo union { 1167c1737f2bSArnaldo Carvalho de Melo __u64 rsvd1; 1168c1737f2bSArnaldo Carvalho de Melo __u64 pad_to_size; 1169c1737f2bSArnaldo Carvalho de Melo }; 1170c1737f2bSArnaldo Carvalho de Melo __u64 rsvd2; 1171c1737f2bSArnaldo Carvalho de Melo }; 1172c1737f2bSArnaldo Carvalho de Melo 1173549a3976SIngo Molnar struct drm_i915_gem_exec_fence { 1174549a3976SIngo Molnar /** 1175549a3976SIngo Molnar * User's handle for a drm_syncobj to wait on or signal. 1176549a3976SIngo Molnar */ 1177549a3976SIngo Molnar __u32 handle; 1178549a3976SIngo Molnar 1179549a3976SIngo Molnar #define I915_EXEC_FENCE_WAIT (1<<0) 1180549a3976SIngo Molnar #define I915_EXEC_FENCE_SIGNAL (1<<1) 1181505ee767SIngo Molnar #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 1182549a3976SIngo Molnar __u32 flags; 1183549a3976SIngo Molnar }; 1184549a3976SIngo Molnar 11854a1cddeaSArnaldo Carvalho de Melo /* 11869e228f48SArnaldo Carvalho de Melo * See drm_i915_gem_execbuffer_ext_timeline_fences. 11879e228f48SArnaldo Carvalho de Melo */ 11889e228f48SArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 11899e228f48SArnaldo Carvalho de Melo 11904a1cddeaSArnaldo Carvalho de Melo /* 11919e228f48SArnaldo Carvalho de Melo * This structure describes an array of drm_syncobj and associated points for 11929e228f48SArnaldo Carvalho de Melo * timeline variants of drm_syncobj. It is invalid to append this structure to 11939e228f48SArnaldo Carvalho de Melo * the execbuf if I915_EXEC_FENCE_ARRAY is set. 11949e228f48SArnaldo Carvalho de Melo */ 11959e228f48SArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer_ext_timeline_fences { 11969e228f48SArnaldo Carvalho de Melo struct i915_user_extension base; 11979e228f48SArnaldo Carvalho de Melo 11989e228f48SArnaldo Carvalho de Melo /** 11999e228f48SArnaldo Carvalho de Melo * Number of element in the handles_ptr & value_ptr arrays. 12009e228f48SArnaldo Carvalho de Melo */ 12019e228f48SArnaldo Carvalho de Melo __u64 fence_count; 12029e228f48SArnaldo Carvalho de Melo 12039e228f48SArnaldo Carvalho de Melo /** 12049e228f48SArnaldo Carvalho de Melo * Pointer to an array of struct drm_i915_gem_exec_fence of length 12059e228f48SArnaldo Carvalho de Melo * fence_count. 12069e228f48SArnaldo Carvalho de Melo */ 12079e228f48SArnaldo Carvalho de Melo __u64 handles_ptr; 12089e228f48SArnaldo Carvalho de Melo 12099e228f48SArnaldo Carvalho de Melo /** 12109e228f48SArnaldo Carvalho de Melo * Pointer to an array of u64 values of length fence_count. Values 12119e228f48SArnaldo Carvalho de Melo * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline 12129e228f48SArnaldo Carvalho de Melo * drm_syncobj is invalid as it turns a drm_syncobj into a binary one. 12139e228f48SArnaldo Carvalho de Melo */ 12149e228f48SArnaldo Carvalho de Melo __u64 values_ptr; 12159e228f48SArnaldo Carvalho de Melo }; 12169e228f48SArnaldo Carvalho de Melo 1217c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer2 { 1218c1737f2bSArnaldo Carvalho de Melo /** 1219c1737f2bSArnaldo Carvalho de Melo * List of gem_exec_object2 structs 1220c1737f2bSArnaldo Carvalho de Melo */ 1221c1737f2bSArnaldo Carvalho de Melo __u64 buffers_ptr; 1222c1737f2bSArnaldo Carvalho de Melo __u32 buffer_count; 1223c1737f2bSArnaldo Carvalho de Melo 1224c1737f2bSArnaldo Carvalho de Melo /** Offset in the batchbuffer to start execution from. */ 1225c1737f2bSArnaldo Carvalho de Melo __u32 batch_start_offset; 1226c1737f2bSArnaldo Carvalho de Melo /** Bytes used in batchbuffer from batch_start_offset */ 1227c1737f2bSArnaldo Carvalho de Melo __u32 batch_len; 1228c1737f2bSArnaldo Carvalho de Melo __u32 DR1; 1229c1737f2bSArnaldo Carvalho de Melo __u32 DR4; 1230c1737f2bSArnaldo Carvalho de Melo __u32 num_cliprects; 1231549a3976SIngo Molnar /** 1232549a3976SIngo Molnar * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY 12339e228f48SArnaldo Carvalho de Melo * & I915_EXEC_USE_EXTENSIONS are not set. 12349e228f48SArnaldo Carvalho de Melo * 12359e228f48SArnaldo Carvalho de Melo * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array 12369e228f48SArnaldo Carvalho de Melo * of struct drm_i915_gem_exec_fence and num_cliprects is the length 12379e228f48SArnaldo Carvalho de Melo * of the array. 12389e228f48SArnaldo Carvalho de Melo * 12399e228f48SArnaldo Carvalho de Melo * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a 12409e228f48SArnaldo Carvalho de Melo * single struct i915_user_extension and num_cliprects is 0. 1241549a3976SIngo Molnar */ 1242c1737f2bSArnaldo Carvalho de Melo __u64 cliprects_ptr; 1243e6aff9f8SArnaldo Carvalho de Melo #define I915_EXEC_RING_MASK (0x3f) 1244c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_DEFAULT (0<<0) 1245c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RENDER (1<<0) 1246c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD (2<<0) 1247c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BLT (3<<0) 1248c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_VEBOX (4<<0) 1249c1737f2bSArnaldo Carvalho de Melo 1250c1737f2bSArnaldo Carvalho de Melo /* Used for switching the constants addressing mode on gen4+ RENDER ring. 1251c1737f2bSArnaldo Carvalho de Melo * Gen6+ only supports relative addressing to dynamic state (default) and 1252c1737f2bSArnaldo Carvalho de Melo * absolute addressing. 1253c1737f2bSArnaldo Carvalho de Melo * 1254c1737f2bSArnaldo Carvalho de Melo * These flags are ignored for the BSD and BLT rings. 1255c1737f2bSArnaldo Carvalho de Melo */ 1256c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_MASK (3<<6) 1257c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 1258c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 1259c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 1260c1737f2bSArnaldo Carvalho de Melo __u64 flags; 1261c1737f2bSArnaldo Carvalho de Melo __u64 rsvd1; /* now used for context info */ 1262c1737f2bSArnaldo Carvalho de Melo __u64 rsvd2; 1263c1737f2bSArnaldo Carvalho de Melo }; 1264c1737f2bSArnaldo Carvalho de Melo 1265c1737f2bSArnaldo Carvalho de Melo /** Resets the SO write offset registers for transform feedback on gen7. */ 1266c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_GEN7_SOL_RESET (1<<8) 1267c1737f2bSArnaldo Carvalho de Melo 1268c1737f2bSArnaldo Carvalho de Melo /** Request a privileged ("secure") batch buffer. Note only available for 1269c1737f2bSArnaldo Carvalho de Melo * DRM_ROOT_ONLY | DRM_MASTER processes. 1270c1737f2bSArnaldo Carvalho de Melo */ 1271c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_SECURE (1<<9) 1272c1737f2bSArnaldo Carvalho de Melo 1273c1737f2bSArnaldo Carvalho de Melo /** Inform the kernel that the batch is and will always be pinned. This 1274c1737f2bSArnaldo Carvalho de Melo * negates the requirement for a workaround to be performed to avoid 1275c1737f2bSArnaldo Carvalho de Melo * an incoherent CS (such as can be found on 830/845). If this flag is 1276c1737f2bSArnaldo Carvalho de Melo * not passed, the kernel will endeavour to make sure the batch is 1277c1737f2bSArnaldo Carvalho de Melo * coherent with the CS before execution. If this flag is passed, 1278c1737f2bSArnaldo Carvalho de Melo * userspace assumes the responsibility for ensuring the same. 1279c1737f2bSArnaldo Carvalho de Melo */ 1280c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_IS_PINNED (1<<10) 1281c1737f2bSArnaldo Carvalho de Melo 1282c1737f2bSArnaldo Carvalho de Melo /** Provide a hint to the kernel that the command stream and auxiliary 1283c1737f2bSArnaldo Carvalho de Melo * state buffers already holds the correct presumed addresses and so the 1284c1737f2bSArnaldo Carvalho de Melo * relocation process may be skipped if no buffers need to be moved in 1285c1737f2bSArnaldo Carvalho de Melo * preparation for the execbuffer. 1286c1737f2bSArnaldo Carvalho de Melo */ 1287c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_NO_RELOC (1<<11) 1288c1737f2bSArnaldo Carvalho de Melo 1289c1737f2bSArnaldo Carvalho de Melo /** Use the reloc.handle as an index into the exec object array rather 1290c1737f2bSArnaldo Carvalho de Melo * than as the per-file handle. 1291c1737f2bSArnaldo Carvalho de Melo */ 1292c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_HANDLE_LUT (1<<12) 1293c1737f2bSArnaldo Carvalho de Melo 1294c1737f2bSArnaldo Carvalho de Melo /** Used for switching BSD rings on the platforms with two BSD rings */ 1295c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_SHIFT (13) 1296c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 1297c1737f2bSArnaldo Carvalho de Melo /* default ping-pong mode */ 1298c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1299c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1300c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 1301c1737f2bSArnaldo Carvalho de Melo 1302c1737f2bSArnaldo Carvalho de Melo /** Tell the kernel that the batchbuffer is processed by 1303c1737f2bSArnaldo Carvalho de Melo * the resource streamer. 1304c1737f2bSArnaldo Carvalho de Melo */ 1305c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1306c1737f2bSArnaldo Carvalho de Melo 1307c1737f2bSArnaldo Carvalho de Melo /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1308c1737f2bSArnaldo Carvalho de Melo * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1309c1737f2bSArnaldo Carvalho de Melo * the batch. 1310c1737f2bSArnaldo Carvalho de Melo * 1311c1737f2bSArnaldo Carvalho de Melo * Returns -EINVAL if the sync_file fd cannot be found. 1312c1737f2bSArnaldo Carvalho de Melo */ 1313c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_IN (1<<16) 1314c1737f2bSArnaldo Carvalho de Melo 1315c1737f2bSArnaldo Carvalho de Melo /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1316c1737f2bSArnaldo Carvalho de Melo * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1317c1737f2bSArnaldo Carvalho de Melo * to the caller, and it should be close() after use. (The fd is a regular 1318c1737f2bSArnaldo Carvalho de Melo * file descriptor and will be cleaned up on process termination. It holds 1319c1737f2bSArnaldo Carvalho de Melo * a reference to the request, but nothing else.) 1320c1737f2bSArnaldo Carvalho de Melo * 1321c1737f2bSArnaldo Carvalho de Melo * The sync_file fd can be combined with other sync_file and passed either 1322c1737f2bSArnaldo Carvalho de Melo * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1323c1737f2bSArnaldo Carvalho de Melo * will only occur after this request completes), or to other devices. 1324c1737f2bSArnaldo Carvalho de Melo * 1325c1737f2bSArnaldo Carvalho de Melo * Using I915_EXEC_FENCE_OUT requires use of 1326c1737f2bSArnaldo Carvalho de Melo * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1327c1737f2bSArnaldo Carvalho de Melo * back to userspace. Failure to do so will cause the out-fence to always 1328c1737f2bSArnaldo Carvalho de Melo * be reported as zero, and the real fence fd to be leaked. 1329c1737f2bSArnaldo Carvalho de Melo */ 1330c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_OUT (1<<17) 1331c1737f2bSArnaldo Carvalho de Melo 1332c1737f2bSArnaldo Carvalho de Melo /* 1333c1737f2bSArnaldo Carvalho de Melo * Traditionally the execbuf ioctl has only considered the final element in 1334c1737f2bSArnaldo Carvalho de Melo * the execobject[] to be the executable batch. Often though, the client 1335c1737f2bSArnaldo Carvalho de Melo * will known the batch object prior to construction and being able to place 1336c1737f2bSArnaldo Carvalho de Melo * it into the execobject[] array first can simplify the relocation tracking. 1337c1737f2bSArnaldo Carvalho de Melo * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 1338c1737f2bSArnaldo Carvalho de Melo * execobject[] as the * batch instead (the default is to use the last 1339c1737f2bSArnaldo Carvalho de Melo * element). 1340c1737f2bSArnaldo Carvalho de Melo */ 1341c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BATCH_FIRST (1<<18) 1342549a3976SIngo Molnar 1343549a3976SIngo Molnar /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1344549a3976SIngo Molnar * define an array of i915_gem_exec_fence structures which specify a set of 1345549a3976SIngo Molnar * dma fences to wait upon or signal. 1346549a3976SIngo Molnar */ 1347549a3976SIngo Molnar #define I915_EXEC_FENCE_ARRAY (1<<19) 1348549a3976SIngo Molnar 134995dc663aSArnaldo Carvalho de Melo /* 135095dc663aSArnaldo Carvalho de Melo * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent 135195dc663aSArnaldo Carvalho de Melo * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 135295dc663aSArnaldo Carvalho de Melo * the batch. 135395dc663aSArnaldo Carvalho de Melo * 135495dc663aSArnaldo Carvalho de Melo * Returns -EINVAL if the sync_file fd cannot be found. 135595dc663aSArnaldo Carvalho de Melo */ 135695dc663aSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_SUBMIT (1 << 20) 135795dc663aSArnaldo Carvalho de Melo 13589e228f48SArnaldo Carvalho de Melo /* 13599e228f48SArnaldo Carvalho de Melo * Setting I915_EXEC_USE_EXTENSIONS implies that 13609e228f48SArnaldo Carvalho de Melo * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked 13619e228f48SArnaldo Carvalho de Melo * list of i915_user_extension. Each i915_user_extension node is the base of a 13629e228f48SArnaldo Carvalho de Melo * larger structure. The list of supported structures are listed in the 13639e228f48SArnaldo Carvalho de Melo * drm_i915_gem_execbuffer_ext enum. 13649e228f48SArnaldo Carvalho de Melo */ 13659e228f48SArnaldo Carvalho de Melo #define I915_EXEC_USE_EXTENSIONS (1 << 21) 13669e228f48SArnaldo Carvalho de Melo 13679e228f48SArnaldo Carvalho de Melo #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) 1368c1737f2bSArnaldo Carvalho de Melo 1369c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1370c1737f2bSArnaldo Carvalho de Melo #define i915_execbuffer2_set_context_id(eb2, context) \ 1371c1737f2bSArnaldo Carvalho de Melo (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1372c1737f2bSArnaldo Carvalho de Melo #define i915_execbuffer2_get_context_id(eb2) \ 1373c1737f2bSArnaldo Carvalho de Melo ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1374c1737f2bSArnaldo Carvalho de Melo 1375c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pin { 1376c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to be pinned. */ 1377c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1378c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1379c1737f2bSArnaldo Carvalho de Melo 1380c1737f2bSArnaldo Carvalho de Melo /** alignment required within the aperture */ 1381c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1382c1737f2bSArnaldo Carvalho de Melo 1383c1737f2bSArnaldo Carvalho de Melo /** Returned GTT offset of the buffer. */ 1384c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1385c1737f2bSArnaldo Carvalho de Melo }; 1386c1737f2bSArnaldo Carvalho de Melo 1387c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_unpin { 1388c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to be unpinned. */ 1389c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1390c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1391c1737f2bSArnaldo Carvalho de Melo }; 1392c1737f2bSArnaldo Carvalho de Melo 1393c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_busy { 1394c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to check for busy */ 1395c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1396c1737f2bSArnaldo Carvalho de Melo 1397c1737f2bSArnaldo Carvalho de Melo /** Return busy status 1398c1737f2bSArnaldo Carvalho de Melo * 1399c1737f2bSArnaldo Carvalho de Melo * A return of 0 implies that the object is idle (after 1400c1737f2bSArnaldo Carvalho de Melo * having flushed any pending activity), and a non-zero return that 1401c1737f2bSArnaldo Carvalho de Melo * the object is still in-flight on the GPU. (The GPU has not yet 1402c1737f2bSArnaldo Carvalho de Melo * signaled completion for all pending requests that reference the 1403c1737f2bSArnaldo Carvalho de Melo * object.) An object is guaranteed to become idle eventually (so 1404c1737f2bSArnaldo Carvalho de Melo * long as no new GPU commands are executed upon it). Due to the 1405c1737f2bSArnaldo Carvalho de Melo * asynchronous nature of the hardware, an object reported 1406c1737f2bSArnaldo Carvalho de Melo * as busy may become idle before the ioctl is completed. 1407c1737f2bSArnaldo Carvalho de Melo * 1408c1737f2bSArnaldo Carvalho de Melo * Furthermore, if the object is busy, which engine is busy is only 1409e6aff9f8SArnaldo Carvalho de Melo * provided as a guide and only indirectly by reporting its class 1410e6aff9f8SArnaldo Carvalho de Melo * (there may be more than one engine in each class). There are race 1411e6aff9f8SArnaldo Carvalho de Melo * conditions which prevent the report of which engines are busy from 1412e6aff9f8SArnaldo Carvalho de Melo * being always accurate. However, the converse is not true. If the 1413e6aff9f8SArnaldo Carvalho de Melo * object is idle, the result of the ioctl, that all engines are idle, 1414e6aff9f8SArnaldo Carvalho de Melo * is accurate. 1415c1737f2bSArnaldo Carvalho de Melo * 1416c1737f2bSArnaldo Carvalho de Melo * The returned dword is split into two fields to indicate both 1417e6aff9f8SArnaldo Carvalho de Melo * the engine classess on which the object is being read, and the 1418e6aff9f8SArnaldo Carvalho de Melo * engine class on which it is currently being written (if any). 1419c1737f2bSArnaldo Carvalho de Melo * 1420c1737f2bSArnaldo Carvalho de Melo * The low word (bits 0:15) indicate if the object is being written 1421c1737f2bSArnaldo Carvalho de Melo * to by any engine (there can only be one, as the GEM implicit 1422c1737f2bSArnaldo Carvalho de Melo * synchronisation rules force writes to be serialised). Only the 1423e6aff9f8SArnaldo Carvalho de Melo * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as 1424e6aff9f8SArnaldo Carvalho de Melo * 1 not 0 etc) for the last write is reported. 1425c1737f2bSArnaldo Carvalho de Melo * 1426e6aff9f8SArnaldo Carvalho de Melo * The high word (bits 16:31) are a bitmask of which engines classes 1427e6aff9f8SArnaldo Carvalho de Melo * are currently reading from the object. Multiple engines may be 1428c1737f2bSArnaldo Carvalho de Melo * reading from the object simultaneously. 1429c1737f2bSArnaldo Carvalho de Melo * 1430e6aff9f8SArnaldo Carvalho de Melo * The value of each engine class is the same as specified in the 1431*4dc24d7cSArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. 1432e6aff9f8SArnaldo Carvalho de Melo * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. 1433*4dc24d7cSArnaldo Carvalho de Melo * Some hardware may have parallel execution engines, e.g. multiple 1434*4dc24d7cSArnaldo Carvalho de Melo * media engines, which are mapped to the same class identifier and so 1435*4dc24d7cSArnaldo Carvalho de Melo * are not separately reported for busyness. 1436c1737f2bSArnaldo Carvalho de Melo * 1437c1737f2bSArnaldo Carvalho de Melo * Caveat emptor: 1438c1737f2bSArnaldo Carvalho de Melo * Only the boolean result of this query is reliable; that is whether 1439c1737f2bSArnaldo Carvalho de Melo * the object is idle or busy. The report of which engines are busy 1440c1737f2bSArnaldo Carvalho de Melo * should be only used as a heuristic. 1441c1737f2bSArnaldo Carvalho de Melo */ 1442c1737f2bSArnaldo Carvalho de Melo __u32 busy; 1443c1737f2bSArnaldo Carvalho de Melo }; 1444c1737f2bSArnaldo Carvalho de Melo 1445c1737f2bSArnaldo Carvalho de Melo /** 1446*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_caching - Set or get the caching for given object 1447*4dc24d7cSArnaldo Carvalho de Melo * handle. 1448c1737f2bSArnaldo Carvalho de Melo * 1449*4dc24d7cSArnaldo Carvalho de Melo * Allow userspace to control the GTT caching bits for a given object when the 1450*4dc24d7cSArnaldo Carvalho de Melo * object is later mapped through the ppGTT(or GGTT on older platforms lacking 1451*4dc24d7cSArnaldo Carvalho de Melo * ppGTT support, or if the object is used for scanout). Note that this might 1452*4dc24d7cSArnaldo Carvalho de Melo * require unbinding the object from the GTT first, if its current caching value 1453*4dc24d7cSArnaldo Carvalho de Melo * doesn't match. 1454c1737f2bSArnaldo Carvalho de Melo * 1455*4dc24d7cSArnaldo Carvalho de Melo * Note that this all changes on discrete platforms, starting from DG1, the 1456*4dc24d7cSArnaldo Carvalho de Melo * set/get caching is no longer supported, and is now rejected. Instead the CPU 1457*4dc24d7cSArnaldo Carvalho de Melo * caching attributes(WB vs WC) will become an immutable creation time property 1458*4dc24d7cSArnaldo Carvalho de Melo * for the object, along with the GTT caching level. For now we don't expose any 1459*4dc24d7cSArnaldo Carvalho de Melo * new uAPI for this, instead on DG1 this is all implicit, although this largely 1460*4dc24d7cSArnaldo Carvalho de Melo * shouldn't matter since DG1 is coherent by default(without any way of 1461*4dc24d7cSArnaldo Carvalho de Melo * controlling it). 1462c1737f2bSArnaldo Carvalho de Melo * 1463*4dc24d7cSArnaldo Carvalho de Melo * Implicit caching rules, starting from DG1: 1464*4dc24d7cSArnaldo Carvalho de Melo * 1465*4dc24d7cSArnaldo Carvalho de Melo * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 1466*4dc24d7cSArnaldo Carvalho de Melo * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 1467*4dc24d7cSArnaldo Carvalho de Melo * mapped as write-combined only. 1468*4dc24d7cSArnaldo Carvalho de Melo * 1469*4dc24d7cSArnaldo Carvalho de Melo * - Everything else is always allocated and mapped as write-back, with the 1470*4dc24d7cSArnaldo Carvalho de Melo * guarantee that everything is also coherent with the GPU. 1471*4dc24d7cSArnaldo Carvalho de Melo * 1472*4dc24d7cSArnaldo Carvalho de Melo * Note that this is likely to change in the future again, where we might need 1473*4dc24d7cSArnaldo Carvalho de Melo * more flexibility on future devices, so making this all explicit as part of a 1474*4dc24d7cSArnaldo Carvalho de Melo * new &drm_i915_gem_create_ext extension is probable. 1475*4dc24d7cSArnaldo Carvalho de Melo * 1476*4dc24d7cSArnaldo Carvalho de Melo * Side note: Part of the reason for this is that changing the at-allocation-time CPU 1477*4dc24d7cSArnaldo Carvalho de Melo * caching attributes for the pages might be required(and is expensive) if we 1478*4dc24d7cSArnaldo Carvalho de Melo * need to then CPU map the pages later with different caching attributes. This 1479*4dc24d7cSArnaldo Carvalho de Melo * inconsistent caching behaviour, while supported on x86, is not universally 1480*4dc24d7cSArnaldo Carvalho de Melo * supported on other architectures. So for simplicity we opt for setting 1481*4dc24d7cSArnaldo Carvalho de Melo * everything at creation time, whilst also making it immutable, on discrete 1482*4dc24d7cSArnaldo Carvalho de Melo * platforms. 1483c1737f2bSArnaldo Carvalho de Melo */ 1484c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_caching { 1485c1737f2bSArnaldo Carvalho de Melo /** 1486*4dc24d7cSArnaldo Carvalho de Melo * @handle: Handle of the buffer to set/get the caching level. 1487*4dc24d7cSArnaldo Carvalho de Melo */ 1488c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1489c1737f2bSArnaldo Carvalho de Melo 1490c1737f2bSArnaldo Carvalho de Melo /** 1491*4dc24d7cSArnaldo Carvalho de Melo * @caching: The GTT caching level to apply or possible return value. 1492c1737f2bSArnaldo Carvalho de Melo * 1493*4dc24d7cSArnaldo Carvalho de Melo * The supported @caching values: 1494*4dc24d7cSArnaldo Carvalho de Melo * 1495*4dc24d7cSArnaldo Carvalho de Melo * I915_CACHING_NONE: 1496*4dc24d7cSArnaldo Carvalho de Melo * 1497*4dc24d7cSArnaldo Carvalho de Melo * GPU access is not coherent with CPU caches. Default for machines 1498*4dc24d7cSArnaldo Carvalho de Melo * without an LLC. This means manual flushing might be needed, if we 1499*4dc24d7cSArnaldo Carvalho de Melo * want GPU access to be coherent. 1500*4dc24d7cSArnaldo Carvalho de Melo * 1501*4dc24d7cSArnaldo Carvalho de Melo * I915_CACHING_CACHED: 1502*4dc24d7cSArnaldo Carvalho de Melo * 1503*4dc24d7cSArnaldo Carvalho de Melo * GPU access is coherent with CPU caches and furthermore the data is 1504*4dc24d7cSArnaldo Carvalho de Melo * cached in last-level caches shared between CPU cores and the GPU GT. 1505*4dc24d7cSArnaldo Carvalho de Melo * 1506*4dc24d7cSArnaldo Carvalho de Melo * I915_CACHING_DISPLAY: 1507*4dc24d7cSArnaldo Carvalho de Melo * 1508*4dc24d7cSArnaldo Carvalho de Melo * Special GPU caching mode which is coherent with the scanout engines. 1509*4dc24d7cSArnaldo Carvalho de Melo * Transparently falls back to I915_CACHING_NONE on platforms where no 1510*4dc24d7cSArnaldo Carvalho de Melo * special cache mode (like write-through or gfdt flushing) is 1511*4dc24d7cSArnaldo Carvalho de Melo * available. The kernel automatically sets this mode when using a 1512*4dc24d7cSArnaldo Carvalho de Melo * buffer as a scanout target. Userspace can manually set this mode to 1513*4dc24d7cSArnaldo Carvalho de Melo * avoid a costly stall and clflush in the hotpath of drawing the first 1514*4dc24d7cSArnaldo Carvalho de Melo * frame. 1515*4dc24d7cSArnaldo Carvalho de Melo */ 1516*4dc24d7cSArnaldo Carvalho de Melo #define I915_CACHING_NONE 0 1517*4dc24d7cSArnaldo Carvalho de Melo #define I915_CACHING_CACHED 1 1518*4dc24d7cSArnaldo Carvalho de Melo #define I915_CACHING_DISPLAY 2 1519c1737f2bSArnaldo Carvalho de Melo __u32 caching; 1520c1737f2bSArnaldo Carvalho de Melo }; 1521c1737f2bSArnaldo Carvalho de Melo 1522c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_NONE 0 1523c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_X 1 1524c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_Y 2 1525c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_LAST I915_TILING_Y 1526c1737f2bSArnaldo Carvalho de Melo 1527c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_NONE 0 1528c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9 1 1529c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10 2 1530c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_11 3 1531c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10_11 4 1532c1737f2bSArnaldo Carvalho de Melo /* Not seen by userland */ 1533c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1534c1737f2bSArnaldo Carvalho de Melo /* Seen by userland. */ 1535c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_17 6 1536c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10_17 7 1537c1737f2bSArnaldo Carvalho de Melo 1538c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_set_tiling { 1539c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to have its tiling state updated */ 1540c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1541c1737f2bSArnaldo Carvalho de Melo 1542c1737f2bSArnaldo Carvalho de Melo /** 1543c1737f2bSArnaldo Carvalho de Melo * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1544c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y). 1545c1737f2bSArnaldo Carvalho de Melo * 1546c1737f2bSArnaldo Carvalho de Melo * This value is to be set on request, and will be updated by the 1547c1737f2bSArnaldo Carvalho de Melo * kernel on successful return with the actual chosen tiling layout. 1548c1737f2bSArnaldo Carvalho de Melo * 1549c1737f2bSArnaldo Carvalho de Melo * The tiling mode may be demoted to I915_TILING_NONE when the system 1550c1737f2bSArnaldo Carvalho de Melo * has bit 6 swizzling that can't be managed correctly by GEM. 1551c1737f2bSArnaldo Carvalho de Melo * 1552c1737f2bSArnaldo Carvalho de Melo * Buffer contents become undefined when changing tiling_mode. 1553c1737f2bSArnaldo Carvalho de Melo */ 1554c1737f2bSArnaldo Carvalho de Melo __u32 tiling_mode; 1555c1737f2bSArnaldo Carvalho de Melo 1556c1737f2bSArnaldo Carvalho de Melo /** 1557c1737f2bSArnaldo Carvalho de Melo * Stride in bytes for the object when in I915_TILING_X or 1558c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y. 1559c1737f2bSArnaldo Carvalho de Melo */ 1560c1737f2bSArnaldo Carvalho de Melo __u32 stride; 1561c1737f2bSArnaldo Carvalho de Melo 1562c1737f2bSArnaldo Carvalho de Melo /** 1563c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1564c1737f2bSArnaldo Carvalho de Melo * mmap mapping. 1565c1737f2bSArnaldo Carvalho de Melo */ 1566c1737f2bSArnaldo Carvalho de Melo __u32 swizzle_mode; 1567c1737f2bSArnaldo Carvalho de Melo }; 1568c1737f2bSArnaldo Carvalho de Melo 1569c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_get_tiling { 1570c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to get tiling state for. */ 1571c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1572c1737f2bSArnaldo Carvalho de Melo 1573c1737f2bSArnaldo Carvalho de Melo /** 1574c1737f2bSArnaldo Carvalho de Melo * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1575c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y). 1576c1737f2bSArnaldo Carvalho de Melo */ 1577c1737f2bSArnaldo Carvalho de Melo __u32 tiling_mode; 1578c1737f2bSArnaldo Carvalho de Melo 1579c1737f2bSArnaldo Carvalho de Melo /** 1580c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1581c1737f2bSArnaldo Carvalho de Melo * mmap mapping. 1582c1737f2bSArnaldo Carvalho de Melo */ 1583c1737f2bSArnaldo Carvalho de Melo __u32 swizzle_mode; 1584c1737f2bSArnaldo Carvalho de Melo 1585c1737f2bSArnaldo Carvalho de Melo /** 1586c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1587c1737f2bSArnaldo Carvalho de Melo * mmap mapping whilst bound. 1588c1737f2bSArnaldo Carvalho de Melo */ 1589c1737f2bSArnaldo Carvalho de Melo __u32 phys_swizzle_mode; 1590c1737f2bSArnaldo Carvalho de Melo }; 1591c1737f2bSArnaldo Carvalho de Melo 1592c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_get_aperture { 1593c1737f2bSArnaldo Carvalho de Melo /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1594c1737f2bSArnaldo Carvalho de Melo __u64 aper_size; 1595c1737f2bSArnaldo Carvalho de Melo 1596c1737f2bSArnaldo Carvalho de Melo /** 1597c1737f2bSArnaldo Carvalho de Melo * Available space in the aperture used by i915_gem_execbuffer, in 1598c1737f2bSArnaldo Carvalho de Melo * bytes 1599c1737f2bSArnaldo Carvalho de Melo */ 1600c1737f2bSArnaldo Carvalho de Melo __u64 aper_available_size; 1601c1737f2bSArnaldo Carvalho de Melo }; 1602c1737f2bSArnaldo Carvalho de Melo 1603c1737f2bSArnaldo Carvalho de Melo struct drm_i915_get_pipe_from_crtc_id { 1604c1737f2bSArnaldo Carvalho de Melo /** ID of CRTC being requested **/ 1605c1737f2bSArnaldo Carvalho de Melo __u32 crtc_id; 1606c1737f2bSArnaldo Carvalho de Melo 1607c1737f2bSArnaldo Carvalho de Melo /** pipe of requested CRTC **/ 1608c1737f2bSArnaldo Carvalho de Melo __u32 pipe; 1609c1737f2bSArnaldo Carvalho de Melo }; 1610c1737f2bSArnaldo Carvalho de Melo 1611c1737f2bSArnaldo Carvalho de Melo #define I915_MADV_WILLNEED 0 1612c1737f2bSArnaldo Carvalho de Melo #define I915_MADV_DONTNEED 1 1613c1737f2bSArnaldo Carvalho de Melo #define __I915_MADV_PURGED 2 /* internal state */ 1614c1737f2bSArnaldo Carvalho de Melo 1615c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_madvise { 1616c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to change the backing store advice */ 1617c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1618c1737f2bSArnaldo Carvalho de Melo 1619c1737f2bSArnaldo Carvalho de Melo /* Advice: either the buffer will be needed again in the near future, 1620c1737f2bSArnaldo Carvalho de Melo * or wont be and could be discarded under memory pressure. 1621c1737f2bSArnaldo Carvalho de Melo */ 1622c1737f2bSArnaldo Carvalho de Melo __u32 madv; 1623c1737f2bSArnaldo Carvalho de Melo 1624c1737f2bSArnaldo Carvalho de Melo /** Whether the backing store still exists. */ 1625c1737f2bSArnaldo Carvalho de Melo __u32 retained; 1626c1737f2bSArnaldo Carvalho de Melo }; 1627c1737f2bSArnaldo Carvalho de Melo 1628c1737f2bSArnaldo Carvalho de Melo /* flags */ 1629c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_TYPE_MASK 0xff 1630c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV_PLANAR 0x01 1631c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV_PACKED 0x02 1632c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB 0x03 1633c1737f2bSArnaldo Carvalho de Melo 1634c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_DEPTH_MASK 0xff00 1635c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB24 0x1000 1636c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB16 0x2000 1637c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB15 0x3000 1638c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV422 0x0100 1639c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV411 0x0200 1640c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV420 0x0300 1641c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV410 0x0400 1642c1737f2bSArnaldo Carvalho de Melo 1643c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_SWAP_MASK 0xff0000 1644c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_NO_SWAP 0x000000 1645c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UV_SWAP 0x010000 1646c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_Y_SWAP 0x020000 1647c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1648c1737f2bSArnaldo Carvalho de Melo 1649c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_FLAGS_MASK 0xff000000 1650c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_ENABLE 0x01000000 1651c1737f2bSArnaldo Carvalho de Melo 1652c1737f2bSArnaldo Carvalho de Melo struct drm_intel_overlay_put_image { 1653c1737f2bSArnaldo Carvalho de Melo /* various flags and src format description */ 1654c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1655c1737f2bSArnaldo Carvalho de Melo /* source picture description */ 1656c1737f2bSArnaldo Carvalho de Melo __u32 bo_handle; 1657c1737f2bSArnaldo Carvalho de Melo /* stride values and offsets are in bytes, buffer relative */ 1658c1737f2bSArnaldo Carvalho de Melo __u16 stride_Y; /* stride for packed formats */ 1659c1737f2bSArnaldo Carvalho de Melo __u16 stride_UV; 1660c1737f2bSArnaldo Carvalho de Melo __u32 offset_Y; /* offset for packet formats */ 1661c1737f2bSArnaldo Carvalho de Melo __u32 offset_U; 1662c1737f2bSArnaldo Carvalho de Melo __u32 offset_V; 1663c1737f2bSArnaldo Carvalho de Melo /* in pixels */ 1664c1737f2bSArnaldo Carvalho de Melo __u16 src_width; 1665c1737f2bSArnaldo Carvalho de Melo __u16 src_height; 1666c1737f2bSArnaldo Carvalho de Melo /* to compensate the scaling factors for partially covered surfaces */ 1667c1737f2bSArnaldo Carvalho de Melo __u16 src_scan_width; 1668c1737f2bSArnaldo Carvalho de Melo __u16 src_scan_height; 1669c1737f2bSArnaldo Carvalho de Melo /* output crtc description */ 1670c1737f2bSArnaldo Carvalho de Melo __u32 crtc_id; 1671c1737f2bSArnaldo Carvalho de Melo __u16 dst_x; 1672c1737f2bSArnaldo Carvalho de Melo __u16 dst_y; 1673c1737f2bSArnaldo Carvalho de Melo __u16 dst_width; 1674c1737f2bSArnaldo Carvalho de Melo __u16 dst_height; 1675c1737f2bSArnaldo Carvalho de Melo }; 1676c1737f2bSArnaldo Carvalho de Melo 1677c1737f2bSArnaldo Carvalho de Melo /* flags */ 1678c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1679c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1680c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1681c1737f2bSArnaldo Carvalho de Melo struct drm_intel_overlay_attrs { 1682c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1683c1737f2bSArnaldo Carvalho de Melo __u32 color_key; 1684c1737f2bSArnaldo Carvalho de Melo __s32 brightness; 1685c1737f2bSArnaldo Carvalho de Melo __u32 contrast; 1686c1737f2bSArnaldo Carvalho de Melo __u32 saturation; 1687c1737f2bSArnaldo Carvalho de Melo __u32 gamma0; 1688c1737f2bSArnaldo Carvalho de Melo __u32 gamma1; 1689c1737f2bSArnaldo Carvalho de Melo __u32 gamma2; 1690c1737f2bSArnaldo Carvalho de Melo __u32 gamma3; 1691c1737f2bSArnaldo Carvalho de Melo __u32 gamma4; 1692c1737f2bSArnaldo Carvalho de Melo __u32 gamma5; 1693c1737f2bSArnaldo Carvalho de Melo }; 1694c1737f2bSArnaldo Carvalho de Melo 1695c1737f2bSArnaldo Carvalho de Melo /* 1696c1737f2bSArnaldo Carvalho de Melo * Intel sprite handling 1697c1737f2bSArnaldo Carvalho de Melo * 1698c1737f2bSArnaldo Carvalho de Melo * Color keying works with a min/mask/max tuple. Both source and destination 1699c1737f2bSArnaldo Carvalho de Melo * color keying is allowed. 1700c1737f2bSArnaldo Carvalho de Melo * 1701c1737f2bSArnaldo Carvalho de Melo * Source keying: 1702c1737f2bSArnaldo Carvalho de Melo * Sprite pixels within the min & max values, masked against the color channels 1703c1737f2bSArnaldo Carvalho de Melo * specified in the mask field, will be transparent. All other pixels will 1704c1737f2bSArnaldo Carvalho de Melo * be displayed on top of the primary plane. For RGB surfaces, only the min 1705c1737f2bSArnaldo Carvalho de Melo * and mask fields will be used; ranged compares are not allowed. 1706c1737f2bSArnaldo Carvalho de Melo * 1707c1737f2bSArnaldo Carvalho de Melo * Destination keying: 1708c1737f2bSArnaldo Carvalho de Melo * Primary plane pixels that match the min value, masked against the color 1709c1737f2bSArnaldo Carvalho de Melo * channels specified in the mask field, will be replaced by corresponding 1710c1737f2bSArnaldo Carvalho de Melo * pixels from the sprite plane. 1711c1737f2bSArnaldo Carvalho de Melo * 1712c1737f2bSArnaldo Carvalho de Melo * Note that source & destination keying are exclusive; only one can be 1713c1737f2bSArnaldo Carvalho de Melo * active on a given plane. 1714c1737f2bSArnaldo Carvalho de Melo */ 1715c1737f2bSArnaldo Carvalho de Melo 171601f97511SArnaldo Carvalho de Melo #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 171701f97511SArnaldo Carvalho de Melo * flags==0 to disable colorkeying. 171801f97511SArnaldo Carvalho de Melo */ 1719c1737f2bSArnaldo Carvalho de Melo #define I915_SET_COLORKEY_DESTINATION (1<<1) 1720c1737f2bSArnaldo Carvalho de Melo #define I915_SET_COLORKEY_SOURCE (1<<2) 1721c1737f2bSArnaldo Carvalho de Melo struct drm_intel_sprite_colorkey { 1722c1737f2bSArnaldo Carvalho de Melo __u32 plane_id; 1723c1737f2bSArnaldo Carvalho de Melo __u32 min_value; 1724c1737f2bSArnaldo Carvalho de Melo __u32 channel_mask; 1725c1737f2bSArnaldo Carvalho de Melo __u32 max_value; 1726c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1727c1737f2bSArnaldo Carvalho de Melo }; 1728c1737f2bSArnaldo Carvalho de Melo 1729c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_wait { 1730c1737f2bSArnaldo Carvalho de Melo /** Handle of BO we shall wait on */ 1731c1737f2bSArnaldo Carvalho de Melo __u32 bo_handle; 1732c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1733c1737f2bSArnaldo Carvalho de Melo /** Number of nanoseconds to wait, Returns time remaining. */ 1734c1737f2bSArnaldo Carvalho de Melo __s64 timeout_ns; 1735c1737f2bSArnaldo Carvalho de Melo }; 1736c1737f2bSArnaldo Carvalho de Melo 1737c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_create { 1738e6aff9f8SArnaldo Carvalho de Melo __u32 ctx_id; /* output: id of new context*/ 1739c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1740c1737f2bSArnaldo Carvalho de Melo }; 1741c1737f2bSArnaldo Carvalho de Melo 1742e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_create_ext { 1743e6aff9f8SArnaldo Carvalho de Melo __u32 ctx_id; /* output: id of new context*/ 1744e6aff9f8SArnaldo Carvalho de Melo __u32 flags; 1745e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 174695dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 1747e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ 174895dc663aSArnaldo Carvalho de Melo (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 1749e6aff9f8SArnaldo Carvalho de Melo __u64 extensions; 1750e6aff9f8SArnaldo Carvalho de Melo }; 1751e6aff9f8SArnaldo Carvalho de Melo 1752e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_param { 1753e6aff9f8SArnaldo Carvalho de Melo __u32 ctx_id; 1754e6aff9f8SArnaldo Carvalho de Melo __u32 size; 1755e6aff9f8SArnaldo Carvalho de Melo __u64 param; 1756e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1757*4dc24d7cSArnaldo Carvalho de Melo /* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance 1758*4dc24d7cSArnaldo Carvalho de Melo * someone somewhere has attempted to use it, never re-use this context 1759*4dc24d7cSArnaldo Carvalho de Melo * param number. 1760*4dc24d7cSArnaldo Carvalho de Melo */ 1761e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1762e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1763e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 1764e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_BANNABLE 0x5 1765e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_PRIORITY 0x6 1766e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 1767e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_DEFAULT_PRIORITY 0 1768e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 1769e6aff9f8SArnaldo Carvalho de Melo /* 1770e6aff9f8SArnaldo Carvalho de Melo * When using the following param, value should be a pointer to 1771e6aff9f8SArnaldo Carvalho de Melo * drm_i915_gem_context_param_sseu. 1772e6aff9f8SArnaldo Carvalho de Melo */ 1773e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_SSEU 0x7 1774e6aff9f8SArnaldo Carvalho de Melo 1775e6aff9f8SArnaldo Carvalho de Melo /* 1776e6aff9f8SArnaldo Carvalho de Melo * Not all clients may want to attempt automatic recover of a context after 1777e6aff9f8SArnaldo Carvalho de Melo * a hang (for example, some clients may only submit very small incremental 1778e6aff9f8SArnaldo Carvalho de Melo * batches relying on known logical state of previous batches which will never 1779e6aff9f8SArnaldo Carvalho de Melo * recover correctly and each attempt will hang), and so would prefer that 1780e6aff9f8SArnaldo Carvalho de Melo * the context is forever banned instead. 1781e6aff9f8SArnaldo Carvalho de Melo * 1782e6aff9f8SArnaldo Carvalho de Melo * If set to false (0), after a reset, subsequent (and in flight) rendering 1783e6aff9f8SArnaldo Carvalho de Melo * from this context is discarded, and the client will need to create a new 1784e6aff9f8SArnaldo Carvalho de Melo * context to use instead. 1785e6aff9f8SArnaldo Carvalho de Melo * 1786e6aff9f8SArnaldo Carvalho de Melo * If set to true (1), the kernel will automatically attempt to recover the 1787e6aff9f8SArnaldo Carvalho de Melo * context by skipping the hanging batch and executing the next batch starting 1788e6aff9f8SArnaldo Carvalho de Melo * from the default context state (discarding the incomplete logical context 1789e6aff9f8SArnaldo Carvalho de Melo * state lost due to the reset). 1790e6aff9f8SArnaldo Carvalho de Melo * 1791e6aff9f8SArnaldo Carvalho de Melo * On creation, all new contexts are marked as recoverable. 1792e6aff9f8SArnaldo Carvalho de Melo */ 1793e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 179495dc663aSArnaldo Carvalho de Melo 179595dc663aSArnaldo Carvalho de Melo /* 179695dc663aSArnaldo Carvalho de Melo * The id of the associated virtual memory address space (ppGTT) of 179795dc663aSArnaldo Carvalho de Melo * this context. Can be retrieved and passed to another context 179895dc663aSArnaldo Carvalho de Melo * (on the same fd) for both to use the same ppGTT and so share 179995dc663aSArnaldo Carvalho de Melo * address layouts, and avoid reloading the page tables on context 180095dc663aSArnaldo Carvalho de Melo * switches between themselves. 180195dc663aSArnaldo Carvalho de Melo * 180295dc663aSArnaldo Carvalho de Melo * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. 180395dc663aSArnaldo Carvalho de Melo */ 180495dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_VM 0x9 180595dc663aSArnaldo Carvalho de Melo 180695dc663aSArnaldo Carvalho de Melo /* 180795dc663aSArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_ENGINES: 180895dc663aSArnaldo Carvalho de Melo * 180995dc663aSArnaldo Carvalho de Melo * Bind this context to operate on this subset of available engines. Henceforth, 181095dc663aSArnaldo Carvalho de Melo * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as 181195dc663aSArnaldo Carvalho de Melo * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] 181295dc663aSArnaldo Carvalho de Melo * and upwards. Slots 0...N are filled in using the specified (class, instance). 181395dc663aSArnaldo Carvalho de Melo * Use 181495dc663aSArnaldo Carvalho de Melo * engine_class: I915_ENGINE_CLASS_INVALID, 181595dc663aSArnaldo Carvalho de Melo * engine_instance: I915_ENGINE_CLASS_INVALID_NONE 181695dc663aSArnaldo Carvalho de Melo * to specify a gap in the array that can be filled in later, e.g. by a 181795dc663aSArnaldo Carvalho de Melo * virtual engine used for load balancing. 181895dc663aSArnaldo Carvalho de Melo * 181995dc663aSArnaldo Carvalho de Melo * Setting the number of engines bound to the context to 0, by passing a zero 182095dc663aSArnaldo Carvalho de Melo * sized argument, will revert back to default settings. 182195dc663aSArnaldo Carvalho de Melo * 182295dc663aSArnaldo Carvalho de Melo * See struct i915_context_param_engines. 182395dc663aSArnaldo Carvalho de Melo * 182495dc663aSArnaldo Carvalho de Melo * Extensions: 182595dc663aSArnaldo Carvalho de Melo * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) 182695dc663aSArnaldo Carvalho de Melo * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) 182795dc663aSArnaldo Carvalho de Melo */ 182895dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_ENGINES 0xa 18290b3fca6aSArnaldo Carvalho de Melo 18300b3fca6aSArnaldo Carvalho de Melo /* 18310b3fca6aSArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_PERSISTENCE: 18320b3fca6aSArnaldo Carvalho de Melo * 18330b3fca6aSArnaldo Carvalho de Melo * Allow the context and active rendering to survive the process until 18340b3fca6aSArnaldo Carvalho de Melo * completion. Persistence allows fire-and-forget clients to queue up a 18350b3fca6aSArnaldo Carvalho de Melo * bunch of work, hand the output over to a display server and then quit. 18360b3fca6aSArnaldo Carvalho de Melo * If the context is marked as not persistent, upon closing (either via 18370b3fca6aSArnaldo Carvalho de Melo * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure 18380b3fca6aSArnaldo Carvalho de Melo * or process termination), the context and any outstanding requests will be 18390b3fca6aSArnaldo Carvalho de Melo * cancelled (and exported fences for cancelled requests marked as -EIO). 18400b3fca6aSArnaldo Carvalho de Melo * 18410b3fca6aSArnaldo Carvalho de Melo * By default, new contexts allow persistence. 18420b3fca6aSArnaldo Carvalho de Melo */ 18430b3fca6aSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 184454a58ebcSArnaldo Carvalho de Melo 1845*4dc24d7cSArnaldo Carvalho de Melo /* This API has been removed. On the off chance someone somewhere has 1846*4dc24d7cSArnaldo Carvalho de Melo * attempted to use it, never re-use this context param number. 184754a58ebcSArnaldo Carvalho de Melo */ 184854a58ebcSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_RINGSIZE 0xc 1849e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes and well documented */ 1850e6aff9f8SArnaldo Carvalho de Melo 1851e6aff9f8SArnaldo Carvalho de Melo __u64 value; 1852e6aff9f8SArnaldo Carvalho de Melo }; 1853e6aff9f8SArnaldo Carvalho de Melo 18544a1cddeaSArnaldo Carvalho de Melo /* 1855e6aff9f8SArnaldo Carvalho de Melo * Context SSEU programming 1856e6aff9f8SArnaldo Carvalho de Melo * 1857e6aff9f8SArnaldo Carvalho de Melo * It may be necessary for either functional or performance reason to configure 1858e6aff9f8SArnaldo Carvalho de Melo * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ 1859e6aff9f8SArnaldo Carvalho de Melo * Sub-slice/EU). 1860e6aff9f8SArnaldo Carvalho de Melo * 1861e6aff9f8SArnaldo Carvalho de Melo * This is done by configuring SSEU configuration using the below 1862e6aff9f8SArnaldo Carvalho de Melo * @struct drm_i915_gem_context_param_sseu for every supported engine which 1863e6aff9f8SArnaldo Carvalho de Melo * userspace intends to use. 1864e6aff9f8SArnaldo Carvalho de Melo * 1865e6aff9f8SArnaldo Carvalho de Melo * Not all GPUs or engines support this functionality in which case an error 1866e6aff9f8SArnaldo Carvalho de Melo * code -ENODEV will be returned. 1867e6aff9f8SArnaldo Carvalho de Melo * 1868e6aff9f8SArnaldo Carvalho de Melo * Also, flexibility of possible SSEU configuration permutations varies between 1869e6aff9f8SArnaldo Carvalho de Melo * GPU generations and software imposed limitations. Requesting such a 1870e6aff9f8SArnaldo Carvalho de Melo * combination will return an error code of -EINVAL. 1871e6aff9f8SArnaldo Carvalho de Melo * 1872e6aff9f8SArnaldo Carvalho de Melo * NOTE: When perf/OA is active the context's SSEU configuration is ignored in 1873e6aff9f8SArnaldo Carvalho de Melo * favour of a single global setting. 1874e6aff9f8SArnaldo Carvalho de Melo */ 1875e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_param_sseu { 1876e6aff9f8SArnaldo Carvalho de Melo /* 1877e6aff9f8SArnaldo Carvalho de Melo * Engine class & instance to be configured or queried. 1878e6aff9f8SArnaldo Carvalho de Melo */ 1879e6aff9f8SArnaldo Carvalho de Melo struct i915_engine_class_instance engine; 1880e6aff9f8SArnaldo Carvalho de Melo 1881e6aff9f8SArnaldo Carvalho de Melo /* 188295dc663aSArnaldo Carvalho de Melo * Unknown flags must be cleared to zero. 1883e6aff9f8SArnaldo Carvalho de Melo */ 1884e6aff9f8SArnaldo Carvalho de Melo __u32 flags; 188595dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 1886e6aff9f8SArnaldo Carvalho de Melo 1887e6aff9f8SArnaldo Carvalho de Melo /* 1888e6aff9f8SArnaldo Carvalho de Melo * Mask of slices to enable for the context. Valid values are a subset 1889e6aff9f8SArnaldo Carvalho de Melo * of the bitmask value returned for I915_PARAM_SLICE_MASK. 1890e6aff9f8SArnaldo Carvalho de Melo */ 1891e6aff9f8SArnaldo Carvalho de Melo __u64 slice_mask; 1892e6aff9f8SArnaldo Carvalho de Melo 1893e6aff9f8SArnaldo Carvalho de Melo /* 1894e6aff9f8SArnaldo Carvalho de Melo * Mask of subslices to enable for the context. Valid values are a 1895e6aff9f8SArnaldo Carvalho de Melo * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. 1896e6aff9f8SArnaldo Carvalho de Melo */ 1897e6aff9f8SArnaldo Carvalho de Melo __u64 subslice_mask; 1898e6aff9f8SArnaldo Carvalho de Melo 1899e6aff9f8SArnaldo Carvalho de Melo /* 1900e6aff9f8SArnaldo Carvalho de Melo * Minimum/Maximum number of EUs to enable per subslice for the 1901e6aff9f8SArnaldo Carvalho de Melo * context. min_eus_per_subslice must be inferior or equal to 1902e6aff9f8SArnaldo Carvalho de Melo * max_eus_per_subslice. 1903e6aff9f8SArnaldo Carvalho de Melo */ 1904e6aff9f8SArnaldo Carvalho de Melo __u16 min_eus_per_subslice; 1905e6aff9f8SArnaldo Carvalho de Melo __u16 max_eus_per_subslice; 1906e6aff9f8SArnaldo Carvalho de Melo 1907e6aff9f8SArnaldo Carvalho de Melo /* 1908e6aff9f8SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 1909e6aff9f8SArnaldo Carvalho de Melo */ 1910e6aff9f8SArnaldo Carvalho de Melo __u32 rsvd; 1911e6aff9f8SArnaldo Carvalho de Melo }; 1912e6aff9f8SArnaldo Carvalho de Melo 1913*4dc24d7cSArnaldo Carvalho de Melo /** 1914*4dc24d7cSArnaldo Carvalho de Melo * DOC: Virtual Engine uAPI 1915*4dc24d7cSArnaldo Carvalho de Melo * 1916*4dc24d7cSArnaldo Carvalho de Melo * Virtual engine is a concept where userspace is able to configure a set of 1917*4dc24d7cSArnaldo Carvalho de Melo * physical engines, submit a batch buffer, and let the driver execute it on any 1918*4dc24d7cSArnaldo Carvalho de Melo * engine from the set as it sees fit. 1919*4dc24d7cSArnaldo Carvalho de Melo * 1920*4dc24d7cSArnaldo Carvalho de Melo * This is primarily useful on parts which have multiple instances of a same 1921*4dc24d7cSArnaldo Carvalho de Melo * class engine, like for example GT3+ Skylake parts with their two VCS engines. 1922*4dc24d7cSArnaldo Carvalho de Melo * 1923*4dc24d7cSArnaldo Carvalho de Melo * For instance userspace can enumerate all engines of a certain class using the 1924*4dc24d7cSArnaldo Carvalho de Melo * previously described `Engine Discovery uAPI`_. After that userspace can 1925*4dc24d7cSArnaldo Carvalho de Melo * create a GEM context with a placeholder slot for the virtual engine (using 1926*4dc24d7cSArnaldo Carvalho de Melo * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class 1927*4dc24d7cSArnaldo Carvalho de Melo * and instance respectively) and finally using the 1928*4dc24d7cSArnaldo Carvalho de Melo * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in 1929*4dc24d7cSArnaldo Carvalho de Melo * the same reserved slot. 1930*4dc24d7cSArnaldo Carvalho de Melo * 1931*4dc24d7cSArnaldo Carvalho de Melo * Example of creating a virtual engine and submitting a batch buffer to it: 1932*4dc24d7cSArnaldo Carvalho de Melo * 1933*4dc24d7cSArnaldo Carvalho de Melo * .. code-block:: C 1934*4dc24d7cSArnaldo Carvalho de Melo * 1935*4dc24d7cSArnaldo Carvalho de Melo * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { 1936*4dc24d7cSArnaldo Carvalho de Melo * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, 1937*4dc24d7cSArnaldo Carvalho de Melo * .engine_index = 0, // Place this virtual engine into engine map slot 0 1938*4dc24d7cSArnaldo Carvalho de Melo * .num_siblings = 2, 1939*4dc24d7cSArnaldo Carvalho de Melo * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, 1940*4dc24d7cSArnaldo Carvalho de Melo * { I915_ENGINE_CLASS_VIDEO, 1 }, }, 1941*4dc24d7cSArnaldo Carvalho de Melo * }; 1942*4dc24d7cSArnaldo Carvalho de Melo * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { 1943*4dc24d7cSArnaldo Carvalho de Melo * .engines = { { I915_ENGINE_CLASS_INVALID, 1944*4dc24d7cSArnaldo Carvalho de Melo * I915_ENGINE_CLASS_INVALID_NONE } }, 1945*4dc24d7cSArnaldo Carvalho de Melo * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension 1946*4dc24d7cSArnaldo Carvalho de Melo * }; 1947*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam p_engines = { 1948*4dc24d7cSArnaldo Carvalho de Melo * .base = { 1949*4dc24d7cSArnaldo Carvalho de Melo * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 1950*4dc24d7cSArnaldo Carvalho de Melo * }, 1951*4dc24d7cSArnaldo Carvalho de Melo * .param = { 1952*4dc24d7cSArnaldo Carvalho de Melo * .param = I915_CONTEXT_PARAM_ENGINES, 1953*4dc24d7cSArnaldo Carvalho de Melo * .value = to_user_pointer(&engines), 1954*4dc24d7cSArnaldo Carvalho de Melo * .size = sizeof(engines), 1955*4dc24d7cSArnaldo Carvalho de Melo * }, 1956*4dc24d7cSArnaldo Carvalho de Melo * }; 1957*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext create = { 1958*4dc24d7cSArnaldo Carvalho de Melo * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 1959*4dc24d7cSArnaldo Carvalho de Melo * .extensions = to_user_pointer(&p_engines); 1960*4dc24d7cSArnaldo Carvalho de Melo * }; 1961*4dc24d7cSArnaldo Carvalho de Melo * 1962*4dc24d7cSArnaldo Carvalho de Melo * ctx_id = gem_context_create_ext(drm_fd, &create); 1963*4dc24d7cSArnaldo Carvalho de Melo * 1964*4dc24d7cSArnaldo Carvalho de Melo * // Now we have created a GEM context with its engine map containing a 1965*4dc24d7cSArnaldo Carvalho de Melo * // single virtual engine. Submissions to this slot can go either to 1966*4dc24d7cSArnaldo Carvalho de Melo * // vcs0 or vcs1, depending on the load balancing algorithm used inside 1967*4dc24d7cSArnaldo Carvalho de Melo * // the driver. The load balancing is dynamic from one batch buffer to 1968*4dc24d7cSArnaldo Carvalho de Melo * // another and transparent to userspace. 1969*4dc24d7cSArnaldo Carvalho de Melo * 1970*4dc24d7cSArnaldo Carvalho de Melo * ... 1971*4dc24d7cSArnaldo Carvalho de Melo * execbuf.rsvd1 = ctx_id; 1972*4dc24d7cSArnaldo Carvalho de Melo * execbuf.flags = 0; // Submits to index 0 which is the virtual engine 1973*4dc24d7cSArnaldo Carvalho de Melo * gem_execbuf(drm_fd, &execbuf); 1974*4dc24d7cSArnaldo Carvalho de Melo */ 1975*4dc24d7cSArnaldo Carvalho de Melo 197695dc663aSArnaldo Carvalho de Melo /* 197795dc663aSArnaldo Carvalho de Melo * i915_context_engines_load_balance: 197895dc663aSArnaldo Carvalho de Melo * 197995dc663aSArnaldo Carvalho de Melo * Enable load balancing across this set of engines. 198095dc663aSArnaldo Carvalho de Melo * 198195dc663aSArnaldo Carvalho de Melo * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when 198295dc663aSArnaldo Carvalho de Melo * used will proxy the execbuffer request onto one of the set of engines 198395dc663aSArnaldo Carvalho de Melo * in such a way as to distribute the load evenly across the set. 198495dc663aSArnaldo Carvalho de Melo * 198595dc663aSArnaldo Carvalho de Melo * The set of engines must be compatible (e.g. the same HW class) as they 198695dc663aSArnaldo Carvalho de Melo * will share the same logical GPU context and ring. 198795dc663aSArnaldo Carvalho de Melo * 198895dc663aSArnaldo Carvalho de Melo * To intermix rendering with the virtual engine and direct rendering onto 198995dc663aSArnaldo Carvalho de Melo * the backing engines (bypassing the load balancing proxy), the context must 199095dc663aSArnaldo Carvalho de Melo * be defined to use a single timeline for all engines. 199195dc663aSArnaldo Carvalho de Melo */ 199295dc663aSArnaldo Carvalho de Melo struct i915_context_engines_load_balance { 199395dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; 199495dc663aSArnaldo Carvalho de Melo 199595dc663aSArnaldo Carvalho de Melo __u16 engine_index; 199695dc663aSArnaldo Carvalho de Melo __u16 num_siblings; 199795dc663aSArnaldo Carvalho de Melo __u32 flags; /* all undefined flags must be zero */ 199895dc663aSArnaldo Carvalho de Melo 199995dc663aSArnaldo Carvalho de Melo __u64 mbz64; /* reserved for future use; must be zero */ 200095dc663aSArnaldo Carvalho de Melo 200195dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[0]; 200295dc663aSArnaldo Carvalho de Melo } __attribute__((packed)); 200395dc663aSArnaldo Carvalho de Melo 200495dc663aSArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ 200595dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; \ 200695dc663aSArnaldo Carvalho de Melo __u16 engine_index; \ 200795dc663aSArnaldo Carvalho de Melo __u16 num_siblings; \ 200895dc663aSArnaldo Carvalho de Melo __u32 flags; \ 200995dc663aSArnaldo Carvalho de Melo __u64 mbz64; \ 201095dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 201195dc663aSArnaldo Carvalho de Melo } __attribute__((packed)) name__ 201295dc663aSArnaldo Carvalho de Melo 201395dc663aSArnaldo Carvalho de Melo /* 201495dc663aSArnaldo Carvalho de Melo * i915_context_engines_bond: 201595dc663aSArnaldo Carvalho de Melo * 201695dc663aSArnaldo Carvalho de Melo * Constructed bonded pairs for execution within a virtual engine. 201795dc663aSArnaldo Carvalho de Melo * 201895dc663aSArnaldo Carvalho de Melo * All engines are equal, but some are more equal than others. Given 201995dc663aSArnaldo Carvalho de Melo * the distribution of resources in the HW, it may be preferable to run 202095dc663aSArnaldo Carvalho de Melo * a request on a given subset of engines in parallel to a request on a 202195dc663aSArnaldo Carvalho de Melo * specific engine. We enable this selection of engines within a virtual 202295dc663aSArnaldo Carvalho de Melo * engine by specifying bonding pairs, for any given master engine we will 202395dc663aSArnaldo Carvalho de Melo * only execute on one of the corresponding siblings within the virtual engine. 202495dc663aSArnaldo Carvalho de Melo * 202595dc663aSArnaldo Carvalho de Melo * To execute a request in parallel on the master engine and a sibling requires 202695dc663aSArnaldo Carvalho de Melo * coordination with a I915_EXEC_FENCE_SUBMIT. 202795dc663aSArnaldo Carvalho de Melo */ 202895dc663aSArnaldo Carvalho de Melo struct i915_context_engines_bond { 202995dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; 203095dc663aSArnaldo Carvalho de Melo 203195dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance master; 203295dc663aSArnaldo Carvalho de Melo 203395dc663aSArnaldo Carvalho de Melo __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ 203495dc663aSArnaldo Carvalho de Melo __u16 num_bonds; 203595dc663aSArnaldo Carvalho de Melo 203695dc663aSArnaldo Carvalho de Melo __u64 flags; /* all undefined flags must be zero */ 203795dc663aSArnaldo Carvalho de Melo __u64 mbz64[4]; /* reserved for future use; must be zero */ 203895dc663aSArnaldo Carvalho de Melo 203995dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[0]; 204095dc663aSArnaldo Carvalho de Melo } __attribute__((packed)); 204195dc663aSArnaldo Carvalho de Melo 204295dc663aSArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ 204395dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; \ 204495dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance master; \ 204595dc663aSArnaldo Carvalho de Melo __u16 virtual_index; \ 204695dc663aSArnaldo Carvalho de Melo __u16 num_bonds; \ 204795dc663aSArnaldo Carvalho de Melo __u64 flags; \ 204895dc663aSArnaldo Carvalho de Melo __u64 mbz64[4]; \ 204995dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 205095dc663aSArnaldo Carvalho de Melo } __attribute__((packed)) name__ 205195dc663aSArnaldo Carvalho de Melo 2052*4dc24d7cSArnaldo Carvalho de Melo /** 2053*4dc24d7cSArnaldo Carvalho de Melo * DOC: Context Engine Map uAPI 2054*4dc24d7cSArnaldo Carvalho de Melo * 2055*4dc24d7cSArnaldo Carvalho de Melo * Context engine map is a new way of addressing engines when submitting batch- 2056*4dc24d7cSArnaldo Carvalho de Melo * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` 2057*4dc24d7cSArnaldo Carvalho de Melo * inside the flags field of `struct drm_i915_gem_execbuffer2`. 2058*4dc24d7cSArnaldo Carvalho de Melo * 2059*4dc24d7cSArnaldo Carvalho de Melo * To use it created GEM contexts need to be configured with a list of engines 2060*4dc24d7cSArnaldo Carvalho de Melo * the user is intending to submit to. This is accomplished using the 2061*4dc24d7cSArnaldo Carvalho de Melo * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct 2062*4dc24d7cSArnaldo Carvalho de Melo * i915_context_param_engines`. 2063*4dc24d7cSArnaldo Carvalho de Melo * 2064*4dc24d7cSArnaldo Carvalho de Melo * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the 2065*4dc24d7cSArnaldo Carvalho de Melo * configured map. 2066*4dc24d7cSArnaldo Carvalho de Melo * 2067*4dc24d7cSArnaldo Carvalho de Melo * Example of creating such context and submitting against it: 2068*4dc24d7cSArnaldo Carvalho de Melo * 2069*4dc24d7cSArnaldo Carvalho de Melo * .. code-block:: C 2070*4dc24d7cSArnaldo Carvalho de Melo * 2071*4dc24d7cSArnaldo Carvalho de Melo * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { 2072*4dc24d7cSArnaldo Carvalho de Melo * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, 2073*4dc24d7cSArnaldo Carvalho de Melo * { I915_ENGINE_CLASS_COPY, 0 } } 2074*4dc24d7cSArnaldo Carvalho de Melo * }; 2075*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam p_engines = { 2076*4dc24d7cSArnaldo Carvalho de Melo * .base = { 2077*4dc24d7cSArnaldo Carvalho de Melo * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 2078*4dc24d7cSArnaldo Carvalho de Melo * }, 2079*4dc24d7cSArnaldo Carvalho de Melo * .param = { 2080*4dc24d7cSArnaldo Carvalho de Melo * .param = I915_CONTEXT_PARAM_ENGINES, 2081*4dc24d7cSArnaldo Carvalho de Melo * .value = to_user_pointer(&engines), 2082*4dc24d7cSArnaldo Carvalho de Melo * .size = sizeof(engines), 2083*4dc24d7cSArnaldo Carvalho de Melo * }, 2084*4dc24d7cSArnaldo Carvalho de Melo * }; 2085*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext create = { 2086*4dc24d7cSArnaldo Carvalho de Melo * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 2087*4dc24d7cSArnaldo Carvalho de Melo * .extensions = to_user_pointer(&p_engines); 2088*4dc24d7cSArnaldo Carvalho de Melo * }; 2089*4dc24d7cSArnaldo Carvalho de Melo * 2090*4dc24d7cSArnaldo Carvalho de Melo * ctx_id = gem_context_create_ext(drm_fd, &create); 2091*4dc24d7cSArnaldo Carvalho de Melo * 2092*4dc24d7cSArnaldo Carvalho de Melo * // We have now created a GEM context with two engines in the map: 2093*4dc24d7cSArnaldo Carvalho de Melo * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines 2094*4dc24d7cSArnaldo Carvalho de Melo * // will not be accessible from this context. 2095*4dc24d7cSArnaldo Carvalho de Melo * 2096*4dc24d7cSArnaldo Carvalho de Melo * ... 2097*4dc24d7cSArnaldo Carvalho de Melo * execbuf.rsvd1 = ctx_id; 2098*4dc24d7cSArnaldo Carvalho de Melo * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context 2099*4dc24d7cSArnaldo Carvalho de Melo * gem_execbuf(drm_fd, &execbuf); 2100*4dc24d7cSArnaldo Carvalho de Melo * 2101*4dc24d7cSArnaldo Carvalho de Melo * ... 2102*4dc24d7cSArnaldo Carvalho de Melo * execbuf.rsvd1 = ctx_id; 2103*4dc24d7cSArnaldo Carvalho de Melo * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context 2104*4dc24d7cSArnaldo Carvalho de Melo * gem_execbuf(drm_fd, &execbuf); 2105*4dc24d7cSArnaldo Carvalho de Melo */ 2106*4dc24d7cSArnaldo Carvalho de Melo 210795dc663aSArnaldo Carvalho de Melo struct i915_context_param_engines { 210895dc663aSArnaldo Carvalho de Melo __u64 extensions; /* linked chain of extension blocks, 0 terminates */ 210995dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 211095dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 211195dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[0]; 211295dc663aSArnaldo Carvalho de Melo } __attribute__((packed)); 211395dc663aSArnaldo Carvalho de Melo 211495dc663aSArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ 211595dc663aSArnaldo Carvalho de Melo __u64 extensions; \ 211695dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 211795dc663aSArnaldo Carvalho de Melo } __attribute__((packed)) name__ 211895dc663aSArnaldo Carvalho de Melo 2119e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_create_ext_setparam { 2120e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 2121e6aff9f8SArnaldo Carvalho de Melo struct i915_user_extension base; 2122e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_param param; 2123e6aff9f8SArnaldo Carvalho de Melo }; 2124e6aff9f8SArnaldo Carvalho de Melo 2125*4dc24d7cSArnaldo Carvalho de Melo /* This API has been removed. On the off chance someone somewhere has 2126*4dc24d7cSArnaldo Carvalho de Melo * attempted to use it, never re-use this extension number. 2127*4dc24d7cSArnaldo Carvalho de Melo */ 212895dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_EXT_CLONE 1 212995dc663aSArnaldo Carvalho de Melo 2130c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_destroy { 2131c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 2132c1737f2bSArnaldo Carvalho de Melo __u32 pad; 2133c1737f2bSArnaldo Carvalho de Melo }; 2134c1737f2bSArnaldo Carvalho de Melo 2135e6aff9f8SArnaldo Carvalho de Melo /* 2136e6aff9f8SArnaldo Carvalho de Melo * DRM_I915_GEM_VM_CREATE - 2137e6aff9f8SArnaldo Carvalho de Melo * 2138e6aff9f8SArnaldo Carvalho de Melo * Create a new virtual memory address space (ppGTT) for use within a context 2139e6aff9f8SArnaldo Carvalho de Melo * on the same file. Extensions can be provided to configure exactly how the 2140e6aff9f8SArnaldo Carvalho de Melo * address space is setup upon creation. 2141e6aff9f8SArnaldo Carvalho de Melo * 2142e6aff9f8SArnaldo Carvalho de Melo * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is 2143e6aff9f8SArnaldo Carvalho de Melo * returned in the outparam @id. 2144e6aff9f8SArnaldo Carvalho de Melo * 2145e6aff9f8SArnaldo Carvalho de Melo * No flags are defined, with all bits reserved and must be zero. 2146e6aff9f8SArnaldo Carvalho de Melo * 2147e6aff9f8SArnaldo Carvalho de Melo * An extension chain maybe provided, starting with @extensions, and terminated 2148e6aff9f8SArnaldo Carvalho de Melo * by the @next_extension being 0. Currently, no extensions are defined. 2149e6aff9f8SArnaldo Carvalho de Melo * 2150e6aff9f8SArnaldo Carvalho de Melo * DRM_I915_GEM_VM_DESTROY - 2151e6aff9f8SArnaldo Carvalho de Melo * 2152e6aff9f8SArnaldo Carvalho de Melo * Destroys a previously created VM id, specified in @id. 2153e6aff9f8SArnaldo Carvalho de Melo * 2154e6aff9f8SArnaldo Carvalho de Melo * No extensions or flags are allowed currently, and so must be zero. 2155e6aff9f8SArnaldo Carvalho de Melo */ 2156e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_vm_control { 2157e6aff9f8SArnaldo Carvalho de Melo __u64 extensions; 2158e6aff9f8SArnaldo Carvalho de Melo __u32 flags; 2159e6aff9f8SArnaldo Carvalho de Melo __u32 vm_id; 2160e6aff9f8SArnaldo Carvalho de Melo }; 2161e6aff9f8SArnaldo Carvalho de Melo 2162c1737f2bSArnaldo Carvalho de Melo struct drm_i915_reg_read { 2163c1737f2bSArnaldo Carvalho de Melo /* 2164c1737f2bSArnaldo Carvalho de Melo * Register offset. 2165c1737f2bSArnaldo Carvalho de Melo * For 64bit wide registers where the upper 32bits don't immediately 2166c1737f2bSArnaldo Carvalho de Melo * follow the lower 32bits, the offset of the lower 32bits must 2167c1737f2bSArnaldo Carvalho de Melo * be specified 2168c1737f2bSArnaldo Carvalho de Melo */ 2169c1737f2bSArnaldo Carvalho de Melo __u64 offset; 2170485be0cbSArnaldo Carvalho de Melo #define I915_REG_READ_8B_WA (1ul << 0) 2171485be0cbSArnaldo Carvalho de Melo 2172c1737f2bSArnaldo Carvalho de Melo __u64 val; /* Return value */ 2173c1737f2bSArnaldo Carvalho de Melo }; 2174e6aff9f8SArnaldo Carvalho de Melo 2175c1737f2bSArnaldo Carvalho de Melo /* Known registers: 2176c1737f2bSArnaldo Carvalho de Melo * 2177c1737f2bSArnaldo Carvalho de Melo * Render engine timestamp - 0x2358 + 64bit - gen7+ 2178c1737f2bSArnaldo Carvalho de Melo * - Note this register returns an invalid value if using the default 2179485be0cbSArnaldo Carvalho de Melo * single instruction 8byte read, in order to workaround that pass 2180485be0cbSArnaldo Carvalho de Melo * flag I915_REG_READ_8B_WA in offset field. 2181c1737f2bSArnaldo Carvalho de Melo * 2182c1737f2bSArnaldo Carvalho de Melo */ 2183c1737f2bSArnaldo Carvalho de Melo 2184c1737f2bSArnaldo Carvalho de Melo struct drm_i915_reset_stats { 2185c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 2186c1737f2bSArnaldo Carvalho de Melo __u32 flags; 2187c1737f2bSArnaldo Carvalho de Melo 2188c1737f2bSArnaldo Carvalho de Melo /* All resets since boot/module reload, for all contexts */ 2189c1737f2bSArnaldo Carvalho de Melo __u32 reset_count; 2190c1737f2bSArnaldo Carvalho de Melo 2191c1737f2bSArnaldo Carvalho de Melo /* Number of batches lost when active in GPU, for this context */ 2192c1737f2bSArnaldo Carvalho de Melo __u32 batch_active; 2193c1737f2bSArnaldo Carvalho de Melo 2194c1737f2bSArnaldo Carvalho de Melo /* Number of batches lost pending for execution, for this context */ 2195c1737f2bSArnaldo Carvalho de Melo __u32 batch_pending; 2196c1737f2bSArnaldo Carvalho de Melo 2197c1737f2bSArnaldo Carvalho de Melo __u32 pad; 2198c1737f2bSArnaldo Carvalho de Melo }; 2199c1737f2bSArnaldo Carvalho de Melo 2200*4dc24d7cSArnaldo Carvalho de Melo /** 2201*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_userptr - Create GEM object from user allocated memory. 2202*4dc24d7cSArnaldo Carvalho de Melo * 2203*4dc24d7cSArnaldo Carvalho de Melo * Userptr objects have several restrictions on what ioctls can be used with the 2204*4dc24d7cSArnaldo Carvalho de Melo * object handle. 2205*4dc24d7cSArnaldo Carvalho de Melo */ 2206c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_userptr { 2207*4dc24d7cSArnaldo Carvalho de Melo /** 2208*4dc24d7cSArnaldo Carvalho de Melo * @user_ptr: The pointer to the allocated memory. 2209*4dc24d7cSArnaldo Carvalho de Melo * 2210*4dc24d7cSArnaldo Carvalho de Melo * Needs to be aligned to PAGE_SIZE. 2211*4dc24d7cSArnaldo Carvalho de Melo */ 2212c1737f2bSArnaldo Carvalho de Melo __u64 user_ptr; 2213*4dc24d7cSArnaldo Carvalho de Melo 2214*4dc24d7cSArnaldo Carvalho de Melo /** 2215*4dc24d7cSArnaldo Carvalho de Melo * @user_size: 2216*4dc24d7cSArnaldo Carvalho de Melo * 2217*4dc24d7cSArnaldo Carvalho de Melo * The size in bytes for the allocated memory. This will also become the 2218*4dc24d7cSArnaldo Carvalho de Melo * object size. 2219*4dc24d7cSArnaldo Carvalho de Melo * 2220*4dc24d7cSArnaldo Carvalho de Melo * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, 2221*4dc24d7cSArnaldo Carvalho de Melo * or larger. 2222*4dc24d7cSArnaldo Carvalho de Melo */ 2223c1737f2bSArnaldo Carvalho de Melo __u64 user_size; 2224*4dc24d7cSArnaldo Carvalho de Melo 2225*4dc24d7cSArnaldo Carvalho de Melo /** 2226*4dc24d7cSArnaldo Carvalho de Melo * @flags: 2227*4dc24d7cSArnaldo Carvalho de Melo * 2228*4dc24d7cSArnaldo Carvalho de Melo * Supported flags: 2229*4dc24d7cSArnaldo Carvalho de Melo * 2230*4dc24d7cSArnaldo Carvalho de Melo * I915_USERPTR_READ_ONLY: 2231*4dc24d7cSArnaldo Carvalho de Melo * 2232*4dc24d7cSArnaldo Carvalho de Melo * Mark the object as readonly, this also means GPU access can only be 2233*4dc24d7cSArnaldo Carvalho de Melo * readonly. This is only supported on HW which supports readonly access 2234*4dc24d7cSArnaldo Carvalho de Melo * through the GTT. If the HW can't support readonly access, an error is 2235*4dc24d7cSArnaldo Carvalho de Melo * returned. 2236*4dc24d7cSArnaldo Carvalho de Melo * 2237*4dc24d7cSArnaldo Carvalho de Melo * I915_USERPTR_PROBE: 2238*4dc24d7cSArnaldo Carvalho de Melo * 2239*4dc24d7cSArnaldo Carvalho de Melo * Probe the provided @user_ptr range and validate that the @user_ptr is 2240*4dc24d7cSArnaldo Carvalho de Melo * indeed pointing to normal memory and that the range is also valid. 2241*4dc24d7cSArnaldo Carvalho de Melo * For example if some garbage address is given to the kernel, then this 2242*4dc24d7cSArnaldo Carvalho de Melo * should complain. 2243*4dc24d7cSArnaldo Carvalho de Melo * 2244*4dc24d7cSArnaldo Carvalho de Melo * Returns -EFAULT if the probe failed. 2245*4dc24d7cSArnaldo Carvalho de Melo * 2246*4dc24d7cSArnaldo Carvalho de Melo * Note that this doesn't populate the backing pages, and also doesn't 2247*4dc24d7cSArnaldo Carvalho de Melo * guarantee that the object will remain valid when the object is 2248*4dc24d7cSArnaldo Carvalho de Melo * eventually used. 2249*4dc24d7cSArnaldo Carvalho de Melo * 2250*4dc24d7cSArnaldo Carvalho de Melo * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE 2251*4dc24d7cSArnaldo Carvalho de Melo * returns a non-zero value. 2252*4dc24d7cSArnaldo Carvalho de Melo * 2253*4dc24d7cSArnaldo Carvalho de Melo * I915_USERPTR_UNSYNCHRONIZED: 2254*4dc24d7cSArnaldo Carvalho de Melo * 2255*4dc24d7cSArnaldo Carvalho de Melo * NOT USED. Setting this flag will result in an error. 2256*4dc24d7cSArnaldo Carvalho de Melo */ 2257c1737f2bSArnaldo Carvalho de Melo __u32 flags; 2258c1737f2bSArnaldo Carvalho de Melo #define I915_USERPTR_READ_ONLY 0x1 2259*4dc24d7cSArnaldo Carvalho de Melo #define I915_USERPTR_PROBE 0x2 2260c1737f2bSArnaldo Carvalho de Melo #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 2261c1737f2bSArnaldo Carvalho de Melo /** 2262*4dc24d7cSArnaldo Carvalho de Melo * @handle: Returned handle for the object. 2263c1737f2bSArnaldo Carvalho de Melo * 2264c1737f2bSArnaldo Carvalho de Melo * Object handles are nonzero. 2265c1737f2bSArnaldo Carvalho de Melo */ 2266c1737f2bSArnaldo Carvalho de Melo __u32 handle; 2267c1737f2bSArnaldo Carvalho de Melo }; 2268c1737f2bSArnaldo Carvalho de Melo 2269c1737f2bSArnaldo Carvalho de Melo enum drm_i915_oa_format { 2270c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A13 = 1, /* HSW only */ 2271c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A29, /* HSW only */ 2272c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 2273c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_B4_C8, /* HSW only */ 2274c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 2275c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 2276c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_C4_B8, /* HSW+ */ 2277c1737f2bSArnaldo Carvalho de Melo 2278c1737f2bSArnaldo Carvalho de Melo /* Gen8+ */ 2279c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A12, 2280c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A12_B8_C8, 2281c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A32u40_A4u32_B8_C8, 2282c1737f2bSArnaldo Carvalho de Melo 2283c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_MAX /* non-ABI */ 2284c1737f2bSArnaldo Carvalho de Melo }; 2285c1737f2bSArnaldo Carvalho de Melo 2286c1737f2bSArnaldo Carvalho de Melo enum drm_i915_perf_property_id { 2287c1737f2bSArnaldo Carvalho de Melo /** 2288c1737f2bSArnaldo Carvalho de Melo * Open the stream for a specific context handle (as used with 2289c1737f2bSArnaldo Carvalho de Melo * execbuffer2). A stream opened for a specific context this way 2290c1737f2bSArnaldo Carvalho de Melo * won't typically require root privileges. 22910b3fca6aSArnaldo Carvalho de Melo * 22920b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2293c1737f2bSArnaldo Carvalho de Melo */ 2294c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_CTX_HANDLE = 1, 2295c1737f2bSArnaldo Carvalho de Melo 2296c1737f2bSArnaldo Carvalho de Melo /** 2297c1737f2bSArnaldo Carvalho de Melo * A value of 1 requests the inclusion of raw OA unit reports as 2298c1737f2bSArnaldo Carvalho de Melo * part of stream samples. 22990b3fca6aSArnaldo Carvalho de Melo * 23000b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2301c1737f2bSArnaldo Carvalho de Melo */ 2302c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_SAMPLE_OA, 2303c1737f2bSArnaldo Carvalho de Melo 2304c1737f2bSArnaldo Carvalho de Melo /** 2305c1737f2bSArnaldo Carvalho de Melo * The value specifies which set of OA unit metrics should be 2306d01541d0SArnaldo Carvalho de Melo * configured, defining the contents of any OA unit reports. 23070b3fca6aSArnaldo Carvalho de Melo * 23080b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2309c1737f2bSArnaldo Carvalho de Melo */ 2310c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_METRICS_SET, 2311c1737f2bSArnaldo Carvalho de Melo 2312c1737f2bSArnaldo Carvalho de Melo /** 2313c1737f2bSArnaldo Carvalho de Melo * The value specifies the size and layout of OA unit reports. 23140b3fca6aSArnaldo Carvalho de Melo * 23150b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2316c1737f2bSArnaldo Carvalho de Melo */ 2317c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_FORMAT, 2318c1737f2bSArnaldo Carvalho de Melo 2319c1737f2bSArnaldo Carvalho de Melo /** 2320c1737f2bSArnaldo Carvalho de Melo * Specifying this property implicitly requests periodic OA unit 2321c1737f2bSArnaldo Carvalho de Melo * sampling and (at least on Haswell) the sampling frequency is derived 2322c1737f2bSArnaldo Carvalho de Melo * from this exponent as follows: 2323c1737f2bSArnaldo Carvalho de Melo * 2324c1737f2bSArnaldo Carvalho de Melo * 80ns * 2^(period_exponent + 1) 23250b3fca6aSArnaldo Carvalho de Melo * 23260b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2327c1737f2bSArnaldo Carvalho de Melo */ 2328c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_EXPONENT, 2329c1737f2bSArnaldo Carvalho de Melo 23300b3fca6aSArnaldo Carvalho de Melo /** 23310b3fca6aSArnaldo Carvalho de Melo * Specifying this property is only valid when specify a context to 23320b3fca6aSArnaldo Carvalho de Melo * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property 23330b3fca6aSArnaldo Carvalho de Melo * will hold preemption of the particular context we want to gather 23340b3fca6aSArnaldo Carvalho de Melo * performance data about. The execbuf2 submissions must include a 23350b3fca6aSArnaldo Carvalho de Melo * drm_i915_gem_execbuffer_ext_perf parameter for this to apply. 23360b3fca6aSArnaldo Carvalho de Melo * 23370b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 3. 23380b3fca6aSArnaldo Carvalho de Melo */ 23390b3fca6aSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_HOLD_PREEMPTION, 23400b3fca6aSArnaldo Carvalho de Melo 2341377cb673SArnaldo Carvalho de Melo /** 2342377cb673SArnaldo Carvalho de Melo * Specifying this pins all contexts to the specified SSEU power 2343377cb673SArnaldo Carvalho de Melo * configuration for the duration of the recording. 2344377cb673SArnaldo Carvalho de Melo * 2345377cb673SArnaldo Carvalho de Melo * This parameter's value is a pointer to a struct 2346377cb673SArnaldo Carvalho de Melo * drm_i915_gem_context_param_sseu. 2347377cb673SArnaldo Carvalho de Melo * 2348377cb673SArnaldo Carvalho de Melo * This property is available in perf revision 4. 2349377cb673SArnaldo Carvalho de Melo */ 2350377cb673SArnaldo Carvalho de Melo DRM_I915_PERF_PROP_GLOBAL_SSEU, 2351377cb673SArnaldo Carvalho de Melo 2352377cb673SArnaldo Carvalho de Melo /** 2353377cb673SArnaldo Carvalho de Melo * This optional parameter specifies the timer interval in nanoseconds 2354377cb673SArnaldo Carvalho de Melo * at which the i915 driver will check the OA buffer for available data. 2355377cb673SArnaldo Carvalho de Melo * Minimum allowed value is 100 microseconds. A default value is used by 2356377cb673SArnaldo Carvalho de Melo * the driver if this parameter is not specified. Note that larger timer 2357377cb673SArnaldo Carvalho de Melo * values will reduce cpu consumption during OA perf captures. However, 2358377cb673SArnaldo Carvalho de Melo * excessively large values would potentially result in OA buffer 2359377cb673SArnaldo Carvalho de Melo * overwrites as captures reach end of the OA buffer. 2360377cb673SArnaldo Carvalho de Melo * 2361377cb673SArnaldo Carvalho de Melo * This property is available in perf revision 5. 2362377cb673SArnaldo Carvalho de Melo */ 2363377cb673SArnaldo Carvalho de Melo DRM_I915_PERF_PROP_POLL_OA_PERIOD, 2364377cb673SArnaldo Carvalho de Melo 2365c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_MAX /* non-ABI */ 2366c1737f2bSArnaldo Carvalho de Melo }; 2367c1737f2bSArnaldo Carvalho de Melo 2368c1737f2bSArnaldo Carvalho de Melo struct drm_i915_perf_open_param { 2369c1737f2bSArnaldo Carvalho de Melo __u32 flags; 2370c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 2371c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 2372c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_DISABLED (1<<2) 2373c1737f2bSArnaldo Carvalho de Melo 2374c1737f2bSArnaldo Carvalho de Melo /** The number of u64 (id, value) pairs */ 2375c1737f2bSArnaldo Carvalho de Melo __u32 num_properties; 2376c1737f2bSArnaldo Carvalho de Melo 2377c1737f2bSArnaldo Carvalho de Melo /** 2378c1737f2bSArnaldo Carvalho de Melo * Pointer to array of u64 (id, value) pairs configuring the stream 2379c1737f2bSArnaldo Carvalho de Melo * to open. 2380c1737f2bSArnaldo Carvalho de Melo */ 2381c1737f2bSArnaldo Carvalho de Melo __u64 properties_ptr; 2382c1737f2bSArnaldo Carvalho de Melo }; 2383c1737f2bSArnaldo Carvalho de Melo 23844a1cddeaSArnaldo Carvalho de Melo /* 2385c1737f2bSArnaldo Carvalho de Melo * Enable data capture for a stream that was either opened in a disabled state 2386c1737f2bSArnaldo Carvalho de Melo * via I915_PERF_FLAG_DISABLED or was later disabled via 2387c1737f2bSArnaldo Carvalho de Melo * I915_PERF_IOCTL_DISABLE. 2388c1737f2bSArnaldo Carvalho de Melo * 2389c1737f2bSArnaldo Carvalho de Melo * It is intended to be cheaper to disable and enable a stream than it may be 2390c1737f2bSArnaldo Carvalho de Melo * to close and re-open a stream with the same configuration. 2391c1737f2bSArnaldo Carvalho de Melo * 2392c1737f2bSArnaldo Carvalho de Melo * It's undefined whether any pending data for the stream will be lost. 23930b3fca6aSArnaldo Carvalho de Melo * 23940b3fca6aSArnaldo Carvalho de Melo * This ioctl is available in perf revision 1. 2395c1737f2bSArnaldo Carvalho de Melo */ 2396c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 2397c1737f2bSArnaldo Carvalho de Melo 23984a1cddeaSArnaldo Carvalho de Melo /* 2399c1737f2bSArnaldo Carvalho de Melo * Disable data capture for a stream. 2400c1737f2bSArnaldo Carvalho de Melo * 2401c1737f2bSArnaldo Carvalho de Melo * It is an error to try and read a stream that is disabled. 24020b3fca6aSArnaldo Carvalho de Melo * 24030b3fca6aSArnaldo Carvalho de Melo * This ioctl is available in perf revision 1. 2404c1737f2bSArnaldo Carvalho de Melo */ 2405c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 2406c1737f2bSArnaldo Carvalho de Melo 24074a1cddeaSArnaldo Carvalho de Melo /* 24080b3fca6aSArnaldo Carvalho de Melo * Change metrics_set captured by a stream. 24090b3fca6aSArnaldo Carvalho de Melo * 24100b3fca6aSArnaldo Carvalho de Melo * If the stream is bound to a specific context, the configuration change 24110b3fca6aSArnaldo Carvalho de Melo * will performed inline with that context such that it takes effect before 24120b3fca6aSArnaldo Carvalho de Melo * the next execbuf submission. 24130b3fca6aSArnaldo Carvalho de Melo * 24140b3fca6aSArnaldo Carvalho de Melo * Returns the previously bound metrics set id, or a negative error code. 24150b3fca6aSArnaldo Carvalho de Melo * 24160b3fca6aSArnaldo Carvalho de Melo * This ioctl is available in perf revision 2. 24170b3fca6aSArnaldo Carvalho de Melo */ 24180b3fca6aSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 24190b3fca6aSArnaldo Carvalho de Melo 24204a1cddeaSArnaldo Carvalho de Melo /* 2421c1737f2bSArnaldo Carvalho de Melo * Common to all i915 perf records 2422c1737f2bSArnaldo Carvalho de Melo */ 2423c1737f2bSArnaldo Carvalho de Melo struct drm_i915_perf_record_header { 2424c1737f2bSArnaldo Carvalho de Melo __u32 type; 2425c1737f2bSArnaldo Carvalho de Melo __u16 pad; 2426c1737f2bSArnaldo Carvalho de Melo __u16 size; 2427c1737f2bSArnaldo Carvalho de Melo }; 2428c1737f2bSArnaldo Carvalho de Melo 2429c1737f2bSArnaldo Carvalho de Melo enum drm_i915_perf_record_type { 2430c1737f2bSArnaldo Carvalho de Melo 2431c1737f2bSArnaldo Carvalho de Melo /** 2432c1737f2bSArnaldo Carvalho de Melo * Samples are the work horse record type whose contents are extensible 2433c1737f2bSArnaldo Carvalho de Melo * and defined when opening an i915 perf stream based on the given 2434c1737f2bSArnaldo Carvalho de Melo * properties. 2435c1737f2bSArnaldo Carvalho de Melo * 2436c1737f2bSArnaldo Carvalho de Melo * Boolean properties following the naming convention 2437c1737f2bSArnaldo Carvalho de Melo * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 2438c1737f2bSArnaldo Carvalho de Melo * every sample. 2439c1737f2bSArnaldo Carvalho de Melo * 2440c1737f2bSArnaldo Carvalho de Melo * The order of these sample properties given by userspace has no 2441c1737f2bSArnaldo Carvalho de Melo * affect on the ordering of data within a sample. The order is 2442c1737f2bSArnaldo Carvalho de Melo * documented here. 2443c1737f2bSArnaldo Carvalho de Melo * 2444c1737f2bSArnaldo Carvalho de Melo * struct { 2445c1737f2bSArnaldo Carvalho de Melo * struct drm_i915_perf_record_header header; 2446c1737f2bSArnaldo Carvalho de Melo * 2447c1737f2bSArnaldo Carvalho de Melo * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 2448c1737f2bSArnaldo Carvalho de Melo * }; 2449c1737f2bSArnaldo Carvalho de Melo */ 2450c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_SAMPLE = 1, 2451c1737f2bSArnaldo Carvalho de Melo 2452c1737f2bSArnaldo Carvalho de Melo /* 2453c1737f2bSArnaldo Carvalho de Melo * Indicates that one or more OA reports were not written by the 2454c1737f2bSArnaldo Carvalho de Melo * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 2455c1737f2bSArnaldo Carvalho de Melo * command collides with periodic sampling - which would be more likely 2456c1737f2bSArnaldo Carvalho de Melo * at higher sampling frequencies. 2457c1737f2bSArnaldo Carvalho de Melo */ 2458c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 2459c1737f2bSArnaldo Carvalho de Melo 2460c1737f2bSArnaldo Carvalho de Melo /** 2461c1737f2bSArnaldo Carvalho de Melo * An error occurred that resulted in all pending OA reports being lost. 2462c1737f2bSArnaldo Carvalho de Melo */ 2463c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 2464c1737f2bSArnaldo Carvalho de Melo 2465c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_MAX /* non-ABI */ 2466c1737f2bSArnaldo Carvalho de Melo }; 2467c1737f2bSArnaldo Carvalho de Melo 24684a1cddeaSArnaldo Carvalho de Melo /* 2469549a3976SIngo Molnar * Structure to upload perf dynamic configuration into the kernel. 2470549a3976SIngo Molnar */ 2471549a3976SIngo Molnar struct drm_i915_perf_oa_config { 2472549a3976SIngo Molnar /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ 2473549a3976SIngo Molnar char uuid[36]; 2474549a3976SIngo Molnar 2475549a3976SIngo Molnar __u32 n_mux_regs; 2476549a3976SIngo Molnar __u32 n_boolean_regs; 2477549a3976SIngo Molnar __u32 n_flex_regs; 2478549a3976SIngo Molnar 2479485be0cbSArnaldo Carvalho de Melo /* 248001f97511SArnaldo Carvalho de Melo * These fields are pointers to tuples of u32 values (register address, 248101f97511SArnaldo Carvalho de Melo * value). For example the expected length of the buffer pointed by 248201f97511SArnaldo Carvalho de Melo * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). 2483485be0cbSArnaldo Carvalho de Melo */ 2484485be0cbSArnaldo Carvalho de Melo __u64 mux_regs_ptr; 2485485be0cbSArnaldo Carvalho de Melo __u64 boolean_regs_ptr; 2486485be0cbSArnaldo Carvalho de Melo __u64 flex_regs_ptr; 2487549a3976SIngo Molnar }; 2488549a3976SIngo Molnar 24894a1cddeaSArnaldo Carvalho de Melo /** 24904a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_item - An individual query for the kernel to process. 24914a1cddeaSArnaldo Carvalho de Melo * 24924a1cddeaSArnaldo Carvalho de Melo * The behaviour is determined by the @query_id. Note that exactly what 24934a1cddeaSArnaldo Carvalho de Melo * @data_ptr is also depends on the specific @query_id. 24944a1cddeaSArnaldo Carvalho de Melo */ 249501f97511SArnaldo Carvalho de Melo struct drm_i915_query_item { 24964a1cddeaSArnaldo Carvalho de Melo /** @query_id: The id for this query */ 249701f97511SArnaldo Carvalho de Melo __u64 query_id; 249801f97511SArnaldo Carvalho de Melo #define DRM_I915_QUERY_TOPOLOGY_INFO 1 249995dc663aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_ENGINE_INFO 2 25000b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG 3 25014a1cddeaSArnaldo Carvalho de Melo #define DRM_I915_QUERY_MEMORY_REGIONS 4 2502e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes and well documented */ 250301f97511SArnaldo Carvalho de Melo 25044a1cddeaSArnaldo Carvalho de Melo /** 25054a1cddeaSArnaldo Carvalho de Melo * @length: 25064a1cddeaSArnaldo Carvalho de Melo * 250701f97511SArnaldo Carvalho de Melo * When set to zero by userspace, this is filled with the size of the 25084a1cddeaSArnaldo Carvalho de Melo * data to be written at the @data_ptr pointer. The kernel sets this 250901f97511SArnaldo Carvalho de Melo * value to a negative value to signal an error on a particular query 251001f97511SArnaldo Carvalho de Melo * item. 251101f97511SArnaldo Carvalho de Melo */ 251201f97511SArnaldo Carvalho de Melo __s32 length; 251301f97511SArnaldo Carvalho de Melo 25144a1cddeaSArnaldo Carvalho de Melo /** 25154a1cddeaSArnaldo Carvalho de Melo * @flags: 25164a1cddeaSArnaldo Carvalho de Melo * 25170b3fca6aSArnaldo Carvalho de Melo * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. 25180b3fca6aSArnaldo Carvalho de Melo * 25190b3fca6aSArnaldo Carvalho de Melo * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the 25200b3fca6aSArnaldo Carvalho de Melo * following: 25214a1cddeaSArnaldo Carvalho de Melo * 25220b3fca6aSArnaldo Carvalho de Melo * - DRM_I915_QUERY_PERF_CONFIG_LIST 25230b3fca6aSArnaldo Carvalho de Melo * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 25240b3fca6aSArnaldo Carvalho de Melo * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID 252501f97511SArnaldo Carvalho de Melo */ 252601f97511SArnaldo Carvalho de Melo __u32 flags; 25270b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 25280b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 25290b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 253001f97511SArnaldo Carvalho de Melo 25314a1cddeaSArnaldo Carvalho de Melo /** 25324a1cddeaSArnaldo Carvalho de Melo * @data_ptr: 25334a1cddeaSArnaldo Carvalho de Melo * 25344a1cddeaSArnaldo Carvalho de Melo * Data will be written at the location pointed by @data_ptr when the 25354a1cddeaSArnaldo Carvalho de Melo * value of @length matches the length of the data to be written by the 253601f97511SArnaldo Carvalho de Melo * kernel. 253701f97511SArnaldo Carvalho de Melo */ 253801f97511SArnaldo Carvalho de Melo __u64 data_ptr; 253901f97511SArnaldo Carvalho de Melo }; 254001f97511SArnaldo Carvalho de Melo 25414a1cddeaSArnaldo Carvalho de Melo /** 25424a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the 25434a1cddeaSArnaldo Carvalho de Melo * kernel to fill out. 25444a1cddeaSArnaldo Carvalho de Melo * 25454a1cddeaSArnaldo Carvalho de Melo * Note that this is generally a two step process for each struct 25464a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_item in the array: 25474a1cddeaSArnaldo Carvalho de Melo * 25484a1cddeaSArnaldo Carvalho de Melo * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct 25494a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The 25504a1cddeaSArnaldo Carvalho de Melo * kernel will then fill in the size, in bytes, which tells userspace how 25514a1cddeaSArnaldo Carvalho de Melo * memory it needs to allocate for the blob(say for an array of properties). 25524a1cddeaSArnaldo Carvalho de Melo * 25534a1cddeaSArnaldo Carvalho de Melo * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the 25544a1cddeaSArnaldo Carvalho de Melo * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that 25554a1cddeaSArnaldo Carvalho de Melo * the &drm_i915_query_item.length should still be the same as what the 25564a1cddeaSArnaldo Carvalho de Melo * kernel previously set. At this point the kernel can fill in the blob. 25574a1cddeaSArnaldo Carvalho de Melo * 25584a1cddeaSArnaldo Carvalho de Melo * Note that for some query items it can make sense for userspace to just pass 25594a1cddeaSArnaldo Carvalho de Melo * in a buffer/blob equal to or larger than the required size. In this case only 25604a1cddeaSArnaldo Carvalho de Melo * a single ioctl call is needed. For some smaller query items this can work 25614a1cddeaSArnaldo Carvalho de Melo * quite well. 25624a1cddeaSArnaldo Carvalho de Melo * 25634a1cddeaSArnaldo Carvalho de Melo */ 256401f97511SArnaldo Carvalho de Melo struct drm_i915_query { 25654a1cddeaSArnaldo Carvalho de Melo /** @num_items: The number of elements in the @items_ptr array */ 256601f97511SArnaldo Carvalho de Melo __u32 num_items; 256701f97511SArnaldo Carvalho de Melo 25684a1cddeaSArnaldo Carvalho de Melo /** 25694a1cddeaSArnaldo Carvalho de Melo * @flags: Unused for now. Must be cleared to zero. 257001f97511SArnaldo Carvalho de Melo */ 257101f97511SArnaldo Carvalho de Melo __u32 flags; 257201f97511SArnaldo Carvalho de Melo 25734a1cddeaSArnaldo Carvalho de Melo /** 25744a1cddeaSArnaldo Carvalho de Melo * @items_ptr: 25754a1cddeaSArnaldo Carvalho de Melo * 25764a1cddeaSArnaldo Carvalho de Melo * Pointer to an array of struct drm_i915_query_item. The number of 25774a1cddeaSArnaldo Carvalho de Melo * array elements is @num_items. 257801f97511SArnaldo Carvalho de Melo */ 257901f97511SArnaldo Carvalho de Melo __u64 items_ptr; 258001f97511SArnaldo Carvalho de Melo }; 258101f97511SArnaldo Carvalho de Melo 258201f97511SArnaldo Carvalho de Melo /* 258301f97511SArnaldo Carvalho de Melo * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : 258401f97511SArnaldo Carvalho de Melo * 258501f97511SArnaldo Carvalho de Melo * data: contains the 3 pieces of information : 258601f97511SArnaldo Carvalho de Melo * 258701f97511SArnaldo Carvalho de Melo * - the slice mask with one bit per slice telling whether a slice is 258801f97511SArnaldo Carvalho de Melo * available. The availability of slice X can be queried with the following 258901f97511SArnaldo Carvalho de Melo * formula : 259001f97511SArnaldo Carvalho de Melo * 259101f97511SArnaldo Carvalho de Melo * (data[X / 8] >> (X % 8)) & 1 259201f97511SArnaldo Carvalho de Melo * 259301f97511SArnaldo Carvalho de Melo * - the subslice mask for each slice with one bit per subslice telling 25940b3fca6aSArnaldo Carvalho de Melo * whether a subslice is available. Gen12 has dual-subslices, which are 25950b3fca6aSArnaldo Carvalho de Melo * similar to two gen11 subslices. For gen12, this array represents dual- 25960b3fca6aSArnaldo Carvalho de Melo * subslices. The availability of subslice Y in slice X can be queried 25970b3fca6aSArnaldo Carvalho de Melo * with the following formula : 259801f97511SArnaldo Carvalho de Melo * 259901f97511SArnaldo Carvalho de Melo * (data[subslice_offset + 260001f97511SArnaldo Carvalho de Melo * X * subslice_stride + 260101f97511SArnaldo Carvalho de Melo * Y / 8] >> (Y % 8)) & 1 260201f97511SArnaldo Carvalho de Melo * 260301f97511SArnaldo Carvalho de Melo * - the EU mask for each subslice in each slice with one bit per EU telling 260401f97511SArnaldo Carvalho de Melo * whether an EU is available. The availability of EU Z in subslice Y in 260501f97511SArnaldo Carvalho de Melo * slice X can be queried with the following formula : 260601f97511SArnaldo Carvalho de Melo * 260701f97511SArnaldo Carvalho de Melo * (data[eu_offset + 260801f97511SArnaldo Carvalho de Melo * (X * max_subslices + Y) * eu_stride + 260901f97511SArnaldo Carvalho de Melo * Z / 8] >> (Z % 8)) & 1 261001f97511SArnaldo Carvalho de Melo */ 261101f97511SArnaldo Carvalho de Melo struct drm_i915_query_topology_info { 261201f97511SArnaldo Carvalho de Melo /* 261301f97511SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 261401f97511SArnaldo Carvalho de Melo */ 261501f97511SArnaldo Carvalho de Melo __u16 flags; 261601f97511SArnaldo Carvalho de Melo 261701f97511SArnaldo Carvalho de Melo __u16 max_slices; 261801f97511SArnaldo Carvalho de Melo __u16 max_subslices; 261901f97511SArnaldo Carvalho de Melo __u16 max_eus_per_subslice; 262001f97511SArnaldo Carvalho de Melo 262101f97511SArnaldo Carvalho de Melo /* 262201f97511SArnaldo Carvalho de Melo * Offset in data[] at which the subslice masks are stored. 262301f97511SArnaldo Carvalho de Melo */ 262401f97511SArnaldo Carvalho de Melo __u16 subslice_offset; 262501f97511SArnaldo Carvalho de Melo 262601f97511SArnaldo Carvalho de Melo /* 262701f97511SArnaldo Carvalho de Melo * Stride at which each of the subslice masks for each slice are 262801f97511SArnaldo Carvalho de Melo * stored. 262901f97511SArnaldo Carvalho de Melo */ 263001f97511SArnaldo Carvalho de Melo __u16 subslice_stride; 263101f97511SArnaldo Carvalho de Melo 263201f97511SArnaldo Carvalho de Melo /* 263301f97511SArnaldo Carvalho de Melo * Offset in data[] at which the EU masks are stored. 263401f97511SArnaldo Carvalho de Melo */ 263501f97511SArnaldo Carvalho de Melo __u16 eu_offset; 263601f97511SArnaldo Carvalho de Melo 263701f97511SArnaldo Carvalho de Melo /* 263801f97511SArnaldo Carvalho de Melo * Stride at which each of the EU masks for each subslice are stored. 263901f97511SArnaldo Carvalho de Melo */ 264001f97511SArnaldo Carvalho de Melo __u16 eu_stride; 264101f97511SArnaldo Carvalho de Melo 264201f97511SArnaldo Carvalho de Melo __u8 data[]; 264301f97511SArnaldo Carvalho de Melo }; 264401f97511SArnaldo Carvalho de Melo 264595dc663aSArnaldo Carvalho de Melo /** 2646*4dc24d7cSArnaldo Carvalho de Melo * DOC: Engine Discovery uAPI 2647*4dc24d7cSArnaldo Carvalho de Melo * 2648*4dc24d7cSArnaldo Carvalho de Melo * Engine discovery uAPI is a way of enumerating physical engines present in a 2649*4dc24d7cSArnaldo Carvalho de Melo * GPU associated with an open i915 DRM file descriptor. This supersedes the old 2650*4dc24d7cSArnaldo Carvalho de Melo * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like 2651*4dc24d7cSArnaldo Carvalho de Melo * `I915_PARAM_HAS_BLT`. 2652*4dc24d7cSArnaldo Carvalho de Melo * 2653*4dc24d7cSArnaldo Carvalho de Melo * The need for this interface came starting with Icelake and newer GPUs, which 2654*4dc24d7cSArnaldo Carvalho de Melo * started to establish a pattern of having multiple engines of a same class, 2655*4dc24d7cSArnaldo Carvalho de Melo * where not all instances were always completely functionally equivalent. 2656*4dc24d7cSArnaldo Carvalho de Melo * 2657*4dc24d7cSArnaldo Carvalho de Melo * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the 2658*4dc24d7cSArnaldo Carvalho de Melo * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. 2659*4dc24d7cSArnaldo Carvalho de Melo * 2660*4dc24d7cSArnaldo Carvalho de Melo * Example for getting the list of engines: 2661*4dc24d7cSArnaldo Carvalho de Melo * 2662*4dc24d7cSArnaldo Carvalho de Melo * .. code-block:: C 2663*4dc24d7cSArnaldo Carvalho de Melo * 2664*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_query_engine_info *info; 2665*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_query_item item = { 2666*4dc24d7cSArnaldo Carvalho de Melo * .query_id = DRM_I915_QUERY_ENGINE_INFO; 2667*4dc24d7cSArnaldo Carvalho de Melo * }; 2668*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_query query = { 2669*4dc24d7cSArnaldo Carvalho de Melo * .num_items = 1, 2670*4dc24d7cSArnaldo Carvalho de Melo * .items_ptr = (uintptr_t)&item, 2671*4dc24d7cSArnaldo Carvalho de Melo * }; 2672*4dc24d7cSArnaldo Carvalho de Melo * int err, i; 2673*4dc24d7cSArnaldo Carvalho de Melo * 2674*4dc24d7cSArnaldo Carvalho de Melo * // First query the size of the blob we need, this needs to be large 2675*4dc24d7cSArnaldo Carvalho de Melo * // enough to hold our array of engines. The kernel will fill out the 2676*4dc24d7cSArnaldo Carvalho de Melo * // item.length for us, which is the number of bytes we need. 2677*4dc24d7cSArnaldo Carvalho de Melo * // 2678*4dc24d7cSArnaldo Carvalho de Melo * // Alternatively a large buffer can be allocated straight away enabling 2679*4dc24d7cSArnaldo Carvalho de Melo * // querying in one pass, in which case item.length should contain the 2680*4dc24d7cSArnaldo Carvalho de Melo * // length of the provided buffer. 2681*4dc24d7cSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 2682*4dc24d7cSArnaldo Carvalho de Melo * if (err) ... 2683*4dc24d7cSArnaldo Carvalho de Melo * 2684*4dc24d7cSArnaldo Carvalho de Melo * info = calloc(1, item.length); 2685*4dc24d7cSArnaldo Carvalho de Melo * // Now that we allocated the required number of bytes, we call the ioctl 2686*4dc24d7cSArnaldo Carvalho de Melo * // again, this time with the data_ptr pointing to our newly allocated 2687*4dc24d7cSArnaldo Carvalho de Melo * // blob, which the kernel can then populate with info on all engines. 2688*4dc24d7cSArnaldo Carvalho de Melo * item.data_ptr = (uintptr_t)&info, 2689*4dc24d7cSArnaldo Carvalho de Melo * 2690*4dc24d7cSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 2691*4dc24d7cSArnaldo Carvalho de Melo * if (err) ... 2692*4dc24d7cSArnaldo Carvalho de Melo * 2693*4dc24d7cSArnaldo Carvalho de Melo * // We can now access each engine in the array 2694*4dc24d7cSArnaldo Carvalho de Melo * for (i = 0; i < info->num_engines; i++) { 2695*4dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_engine_info einfo = info->engines[i]; 2696*4dc24d7cSArnaldo Carvalho de Melo * u16 class = einfo.engine.class; 2697*4dc24d7cSArnaldo Carvalho de Melo * u16 instance = einfo.engine.instance; 2698*4dc24d7cSArnaldo Carvalho de Melo * .... 2699*4dc24d7cSArnaldo Carvalho de Melo * } 2700*4dc24d7cSArnaldo Carvalho de Melo * 2701*4dc24d7cSArnaldo Carvalho de Melo * free(info); 2702*4dc24d7cSArnaldo Carvalho de Melo * 2703*4dc24d7cSArnaldo Carvalho de Melo * Each of the enumerated engines, apart from being defined by its class and 2704*4dc24d7cSArnaldo Carvalho de Melo * instance (see `struct i915_engine_class_instance`), also can have flags and 2705*4dc24d7cSArnaldo Carvalho de Melo * capabilities defined as documented in i915_drm.h. 2706*4dc24d7cSArnaldo Carvalho de Melo * 2707*4dc24d7cSArnaldo Carvalho de Melo * For instance video engines which support HEVC encoding will have the 2708*4dc24d7cSArnaldo Carvalho de Melo * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. 2709*4dc24d7cSArnaldo Carvalho de Melo * 2710*4dc24d7cSArnaldo Carvalho de Melo * Engine discovery only fully comes to its own when combined with the new way 2711*4dc24d7cSArnaldo Carvalho de Melo * of addressing engines when submitting batch buffers using contexts with 2712*4dc24d7cSArnaldo Carvalho de Melo * engine maps configured. 2713*4dc24d7cSArnaldo Carvalho de Melo */ 2714*4dc24d7cSArnaldo Carvalho de Melo 2715*4dc24d7cSArnaldo Carvalho de Melo /** 271695dc663aSArnaldo Carvalho de Melo * struct drm_i915_engine_info 271795dc663aSArnaldo Carvalho de Melo * 271895dc663aSArnaldo Carvalho de Melo * Describes one engine and it's capabilities as known to the driver. 271995dc663aSArnaldo Carvalho de Melo */ 272095dc663aSArnaldo Carvalho de Melo struct drm_i915_engine_info { 27214a1cddeaSArnaldo Carvalho de Melo /** @engine: Engine class and instance. */ 272295dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engine; 272395dc663aSArnaldo Carvalho de Melo 27244a1cddeaSArnaldo Carvalho de Melo /** @rsvd0: Reserved field. */ 272595dc663aSArnaldo Carvalho de Melo __u32 rsvd0; 272695dc663aSArnaldo Carvalho de Melo 27274a1cddeaSArnaldo Carvalho de Melo /** @flags: Engine flags. */ 272895dc663aSArnaldo Carvalho de Melo __u64 flags; 272995dc663aSArnaldo Carvalho de Melo 27304a1cddeaSArnaldo Carvalho de Melo /** @capabilities: Capabilities of this engine. */ 273195dc663aSArnaldo Carvalho de Melo __u64 capabilities; 273295dc663aSArnaldo Carvalho de Melo #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 273395dc663aSArnaldo Carvalho de Melo #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 273495dc663aSArnaldo Carvalho de Melo 27354a1cddeaSArnaldo Carvalho de Melo /** @rsvd1: Reserved fields. */ 273695dc663aSArnaldo Carvalho de Melo __u64 rsvd1[4]; 273795dc663aSArnaldo Carvalho de Melo }; 273895dc663aSArnaldo Carvalho de Melo 273995dc663aSArnaldo Carvalho de Melo /** 274095dc663aSArnaldo Carvalho de Melo * struct drm_i915_query_engine_info 274195dc663aSArnaldo Carvalho de Melo * 274295dc663aSArnaldo Carvalho de Melo * Engine info query enumerates all engines known to the driver by filling in 274395dc663aSArnaldo Carvalho de Melo * an array of struct drm_i915_engine_info structures. 274495dc663aSArnaldo Carvalho de Melo */ 274595dc663aSArnaldo Carvalho de Melo struct drm_i915_query_engine_info { 27464a1cddeaSArnaldo Carvalho de Melo /** @num_engines: Number of struct drm_i915_engine_info structs following. */ 274795dc663aSArnaldo Carvalho de Melo __u32 num_engines; 274895dc663aSArnaldo Carvalho de Melo 27494a1cddeaSArnaldo Carvalho de Melo /** @rsvd: MBZ */ 275095dc663aSArnaldo Carvalho de Melo __u32 rsvd[3]; 275195dc663aSArnaldo Carvalho de Melo 27524a1cddeaSArnaldo Carvalho de Melo /** @engines: Marker for drm_i915_engine_info structures. */ 275395dc663aSArnaldo Carvalho de Melo struct drm_i915_engine_info engines[]; 275495dc663aSArnaldo Carvalho de Melo }; 275595dc663aSArnaldo Carvalho de Melo 27560b3fca6aSArnaldo Carvalho de Melo /* 27570b3fca6aSArnaldo Carvalho de Melo * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG. 27580b3fca6aSArnaldo Carvalho de Melo */ 27590b3fca6aSArnaldo Carvalho de Melo struct drm_i915_query_perf_config { 27600b3fca6aSArnaldo Carvalho de Melo union { 27610b3fca6aSArnaldo Carvalho de Melo /* 27620b3fca6aSArnaldo Carvalho de Melo * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets 27630b3fca6aSArnaldo Carvalho de Melo * this fields to the number of configurations available. 27640b3fca6aSArnaldo Carvalho de Melo */ 27650b3fca6aSArnaldo Carvalho de Melo __u64 n_configs; 27660b3fca6aSArnaldo Carvalho de Melo 27670b3fca6aSArnaldo Carvalho de Melo /* 27680b3fca6aSArnaldo Carvalho de Melo * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, 27690b3fca6aSArnaldo Carvalho de Melo * i915 will use the value in this field as configuration 27700b3fca6aSArnaldo Carvalho de Melo * identifier to decide what data to write into config_ptr. 27710b3fca6aSArnaldo Carvalho de Melo */ 27720b3fca6aSArnaldo Carvalho de Melo __u64 config; 27730b3fca6aSArnaldo Carvalho de Melo 27740b3fca6aSArnaldo Carvalho de Melo /* 27750b3fca6aSArnaldo Carvalho de Melo * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, 27760b3fca6aSArnaldo Carvalho de Melo * i915 will use the value in this field as configuration 27770b3fca6aSArnaldo Carvalho de Melo * identifier to decide what data to write into config_ptr. 27780b3fca6aSArnaldo Carvalho de Melo * 27790b3fca6aSArnaldo Carvalho de Melo * String formatted like "%08x-%04x-%04x-%04x-%012x" 27800b3fca6aSArnaldo Carvalho de Melo */ 27810b3fca6aSArnaldo Carvalho de Melo char uuid[36]; 27820b3fca6aSArnaldo Carvalho de Melo }; 27830b3fca6aSArnaldo Carvalho de Melo 27840b3fca6aSArnaldo Carvalho de Melo /* 27850b3fca6aSArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 27860b3fca6aSArnaldo Carvalho de Melo */ 27870b3fca6aSArnaldo Carvalho de Melo __u32 flags; 27880b3fca6aSArnaldo Carvalho de Melo 27890b3fca6aSArnaldo Carvalho de Melo /* 27900b3fca6aSArnaldo Carvalho de Melo * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will 27910b3fca6aSArnaldo Carvalho de Melo * write an array of __u64 of configuration identifiers. 27920b3fca6aSArnaldo Carvalho de Melo * 27930b3fca6aSArnaldo Carvalho de Melo * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will 27940b3fca6aSArnaldo Carvalho de Melo * write a struct drm_i915_perf_oa_config. If the following fields of 27950b3fca6aSArnaldo Carvalho de Melo * drm_i915_perf_oa_config are set not set to 0, i915 will write into 27960b3fca6aSArnaldo Carvalho de Melo * the associated pointers the values of submitted when the 27970b3fca6aSArnaldo Carvalho de Melo * configuration was created : 27980b3fca6aSArnaldo Carvalho de Melo * 27990b3fca6aSArnaldo Carvalho de Melo * - n_mux_regs 28000b3fca6aSArnaldo Carvalho de Melo * - n_boolean_regs 28010b3fca6aSArnaldo Carvalho de Melo * - n_flex_regs 28020b3fca6aSArnaldo Carvalho de Melo */ 28030b3fca6aSArnaldo Carvalho de Melo __u8 data[]; 28040b3fca6aSArnaldo Carvalho de Melo }; 28050b3fca6aSArnaldo Carvalho de Melo 28064a1cddeaSArnaldo Carvalho de Melo /** 28074a1cddeaSArnaldo Carvalho de Melo * enum drm_i915_gem_memory_class - Supported memory classes 28084a1cddeaSArnaldo Carvalho de Melo */ 28094a1cddeaSArnaldo Carvalho de Melo enum drm_i915_gem_memory_class { 28104a1cddeaSArnaldo Carvalho de Melo /** @I915_MEMORY_CLASS_SYSTEM: System memory */ 28114a1cddeaSArnaldo Carvalho de Melo I915_MEMORY_CLASS_SYSTEM = 0, 28124a1cddeaSArnaldo Carvalho de Melo /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ 28134a1cddeaSArnaldo Carvalho de Melo I915_MEMORY_CLASS_DEVICE, 28144a1cddeaSArnaldo Carvalho de Melo }; 28154a1cddeaSArnaldo Carvalho de Melo 28164a1cddeaSArnaldo Carvalho de Melo /** 28174a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_memory_class_instance - Identify particular memory region 28184a1cddeaSArnaldo Carvalho de Melo */ 28194a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_memory_class_instance { 28204a1cddeaSArnaldo Carvalho de Melo /** @memory_class: See enum drm_i915_gem_memory_class */ 28214a1cddeaSArnaldo Carvalho de Melo __u16 memory_class; 28224a1cddeaSArnaldo Carvalho de Melo 28234a1cddeaSArnaldo Carvalho de Melo /** @memory_instance: Which instance */ 28244a1cddeaSArnaldo Carvalho de Melo __u16 memory_instance; 28254a1cddeaSArnaldo Carvalho de Melo }; 28264a1cddeaSArnaldo Carvalho de Melo 28274a1cddeaSArnaldo Carvalho de Melo /** 28284a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_memory_region_info - Describes one region as known to the 28294a1cddeaSArnaldo Carvalho de Melo * driver. 28304a1cddeaSArnaldo Carvalho de Melo * 28314a1cddeaSArnaldo Carvalho de Melo * Note that we reserve some stuff here for potential future work. As an example 28324a1cddeaSArnaldo Carvalho de Melo * we might want expose the capabilities for a given region, which could include 28334a1cddeaSArnaldo Carvalho de Melo * things like if the region is CPU mappable/accessible, what are the supported 28344a1cddeaSArnaldo Carvalho de Melo * mapping types etc. 28354a1cddeaSArnaldo Carvalho de Melo * 28364a1cddeaSArnaldo Carvalho de Melo * Note that to extend struct drm_i915_memory_region_info and struct 28374a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_memory_regions in the future the plan is to do the following: 28384a1cddeaSArnaldo Carvalho de Melo * 28394a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 28404a1cddeaSArnaldo Carvalho de Melo * 28414a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_memory_region_info { 28424a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_memory_class_instance region; 28434a1cddeaSArnaldo Carvalho de Melo * union { 28444a1cddeaSArnaldo Carvalho de Melo * __u32 rsvd0; 28454a1cddeaSArnaldo Carvalho de Melo * __u32 new_thing1; 28464a1cddeaSArnaldo Carvalho de Melo * }; 28474a1cddeaSArnaldo Carvalho de Melo * ... 28484a1cddeaSArnaldo Carvalho de Melo * union { 28494a1cddeaSArnaldo Carvalho de Melo * __u64 rsvd1[8]; 28504a1cddeaSArnaldo Carvalho de Melo * struct { 28514a1cddeaSArnaldo Carvalho de Melo * __u64 new_thing2; 28524a1cddeaSArnaldo Carvalho de Melo * __u64 new_thing3; 28534a1cddeaSArnaldo Carvalho de Melo * ... 28544a1cddeaSArnaldo Carvalho de Melo * }; 28554a1cddeaSArnaldo Carvalho de Melo * }; 28564a1cddeaSArnaldo Carvalho de Melo * }; 28574a1cddeaSArnaldo Carvalho de Melo * 28584a1cddeaSArnaldo Carvalho de Melo * With this things should remain source compatible between versions for 28594a1cddeaSArnaldo Carvalho de Melo * userspace, even as we add new fields. 28604a1cddeaSArnaldo Carvalho de Melo * 28614a1cddeaSArnaldo Carvalho de Melo * Note this is using both struct drm_i915_query_item and struct drm_i915_query. 28624a1cddeaSArnaldo Carvalho de Melo * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS 28634a1cddeaSArnaldo Carvalho de Melo * at &drm_i915_query_item.query_id. 28644a1cddeaSArnaldo Carvalho de Melo */ 28654a1cddeaSArnaldo Carvalho de Melo struct drm_i915_memory_region_info { 28664a1cddeaSArnaldo Carvalho de Melo /** @region: The class:instance pair encoding */ 28674a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_memory_class_instance region; 28684a1cddeaSArnaldo Carvalho de Melo 28694a1cddeaSArnaldo Carvalho de Melo /** @rsvd0: MBZ */ 28704a1cddeaSArnaldo Carvalho de Melo __u32 rsvd0; 28714a1cddeaSArnaldo Carvalho de Melo 28724a1cddeaSArnaldo Carvalho de Melo /** @probed_size: Memory probed by the driver (-1 = unknown) */ 28734a1cddeaSArnaldo Carvalho de Melo __u64 probed_size; 28744a1cddeaSArnaldo Carvalho de Melo 28754a1cddeaSArnaldo Carvalho de Melo /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ 28764a1cddeaSArnaldo Carvalho de Melo __u64 unallocated_size; 28774a1cddeaSArnaldo Carvalho de Melo 28784a1cddeaSArnaldo Carvalho de Melo /** @rsvd1: MBZ */ 28794a1cddeaSArnaldo Carvalho de Melo __u64 rsvd1[8]; 28804a1cddeaSArnaldo Carvalho de Melo }; 28814a1cddeaSArnaldo Carvalho de Melo 28824a1cddeaSArnaldo Carvalho de Melo /** 28834a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_memory_regions 28844a1cddeaSArnaldo Carvalho de Melo * 28854a1cddeaSArnaldo Carvalho de Melo * The region info query enumerates all regions known to the driver by filling 28864a1cddeaSArnaldo Carvalho de Melo * in an array of struct drm_i915_memory_region_info structures. 28874a1cddeaSArnaldo Carvalho de Melo * 28884a1cddeaSArnaldo Carvalho de Melo * Example for getting the list of supported regions: 28894a1cddeaSArnaldo Carvalho de Melo * 28904a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 28914a1cddeaSArnaldo Carvalho de Melo * 28924a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_memory_regions *info; 28934a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_item item = { 28944a1cddeaSArnaldo Carvalho de Melo * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; 28954a1cddeaSArnaldo Carvalho de Melo * }; 28964a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query query = { 28974a1cddeaSArnaldo Carvalho de Melo * .num_items = 1, 28984a1cddeaSArnaldo Carvalho de Melo * .items_ptr = (uintptr_t)&item, 28994a1cddeaSArnaldo Carvalho de Melo * }; 29004a1cddeaSArnaldo Carvalho de Melo * int err, i; 29014a1cddeaSArnaldo Carvalho de Melo * 29024a1cddeaSArnaldo Carvalho de Melo * // First query the size of the blob we need, this needs to be large 29034a1cddeaSArnaldo Carvalho de Melo * // enough to hold our array of regions. The kernel will fill out the 29044a1cddeaSArnaldo Carvalho de Melo * // item.length for us, which is the number of bytes we need. 29054a1cddeaSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 29064a1cddeaSArnaldo Carvalho de Melo * if (err) ... 29074a1cddeaSArnaldo Carvalho de Melo * 29084a1cddeaSArnaldo Carvalho de Melo * info = calloc(1, item.length); 29094a1cddeaSArnaldo Carvalho de Melo * // Now that we allocated the required number of bytes, we call the ioctl 29104a1cddeaSArnaldo Carvalho de Melo * // again, this time with the data_ptr pointing to our newly allocated 29114a1cddeaSArnaldo Carvalho de Melo * // blob, which the kernel can then populate with the all the region info. 29124a1cddeaSArnaldo Carvalho de Melo * item.data_ptr = (uintptr_t)&info, 29134a1cddeaSArnaldo Carvalho de Melo * 29144a1cddeaSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 29154a1cddeaSArnaldo Carvalho de Melo * if (err) ... 29164a1cddeaSArnaldo Carvalho de Melo * 29174a1cddeaSArnaldo Carvalho de Melo * // We can now access each region in the array 29184a1cddeaSArnaldo Carvalho de Melo * for (i = 0; i < info->num_regions; i++) { 29194a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_memory_region_info mr = info->regions[i]; 29204a1cddeaSArnaldo Carvalho de Melo * u16 class = mr.region.class; 29214a1cddeaSArnaldo Carvalho de Melo * u16 instance = mr.region.instance; 29224a1cddeaSArnaldo Carvalho de Melo * 29234a1cddeaSArnaldo Carvalho de Melo * .... 29244a1cddeaSArnaldo Carvalho de Melo * } 29254a1cddeaSArnaldo Carvalho de Melo * 29264a1cddeaSArnaldo Carvalho de Melo * free(info); 29274a1cddeaSArnaldo Carvalho de Melo */ 29284a1cddeaSArnaldo Carvalho de Melo struct drm_i915_query_memory_regions { 29294a1cddeaSArnaldo Carvalho de Melo /** @num_regions: Number of supported regions */ 29304a1cddeaSArnaldo Carvalho de Melo __u32 num_regions; 29314a1cddeaSArnaldo Carvalho de Melo 29324a1cddeaSArnaldo Carvalho de Melo /** @rsvd: MBZ */ 29334a1cddeaSArnaldo Carvalho de Melo __u32 rsvd[3]; 29344a1cddeaSArnaldo Carvalho de Melo 29354a1cddeaSArnaldo Carvalho de Melo /** @regions: Info about each supported region */ 29364a1cddeaSArnaldo Carvalho de Melo struct drm_i915_memory_region_info regions[]; 29374a1cddeaSArnaldo Carvalho de Melo }; 29384a1cddeaSArnaldo Carvalho de Melo 29394a1cddeaSArnaldo Carvalho de Melo /** 29404a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added 29414a1cddeaSArnaldo Carvalho de Melo * extension support using struct i915_user_extension. 29424a1cddeaSArnaldo Carvalho de Melo * 29434a1cddeaSArnaldo Carvalho de Melo * Note that in the future we want to have our buffer flags here, at least for 29444a1cddeaSArnaldo Carvalho de Melo * the stuff that is immutable. Previously we would have two ioctls, one to 29454a1cddeaSArnaldo Carvalho de Melo * create the object with gem_create, and another to apply various parameters, 29464a1cddeaSArnaldo Carvalho de Melo * however this creates some ambiguity for the params which are considered 29474a1cddeaSArnaldo Carvalho de Melo * immutable. Also in general we're phasing out the various SET/GET ioctls. 29484a1cddeaSArnaldo Carvalho de Melo */ 29494a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_create_ext { 29504a1cddeaSArnaldo Carvalho de Melo /** 29514a1cddeaSArnaldo Carvalho de Melo * @size: Requested size for the object. 29524a1cddeaSArnaldo Carvalho de Melo * 29534a1cddeaSArnaldo Carvalho de Melo * The (page-aligned) allocated size for the object will be returned. 29544a1cddeaSArnaldo Carvalho de Melo * 29554a1cddeaSArnaldo Carvalho de Melo * Note that for some devices we have might have further minimum 29564a1cddeaSArnaldo Carvalho de Melo * page-size restrictions(larger than 4K), like for device local-memory. 29574a1cddeaSArnaldo Carvalho de Melo * However in general the final size here should always reflect any 29584a1cddeaSArnaldo Carvalho de Melo * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS 29594a1cddeaSArnaldo Carvalho de Melo * extension to place the object in device local-memory. 29604a1cddeaSArnaldo Carvalho de Melo */ 29614a1cddeaSArnaldo Carvalho de Melo __u64 size; 29624a1cddeaSArnaldo Carvalho de Melo /** 29634a1cddeaSArnaldo Carvalho de Melo * @handle: Returned handle for the object. 29644a1cddeaSArnaldo Carvalho de Melo * 29654a1cddeaSArnaldo Carvalho de Melo * Object handles are nonzero. 29664a1cddeaSArnaldo Carvalho de Melo */ 29674a1cddeaSArnaldo Carvalho de Melo __u32 handle; 29684a1cddeaSArnaldo Carvalho de Melo /** @flags: MBZ */ 29694a1cddeaSArnaldo Carvalho de Melo __u32 flags; 29704a1cddeaSArnaldo Carvalho de Melo /** 29714a1cddeaSArnaldo Carvalho de Melo * @extensions: The chain of extensions to apply to this object. 29724a1cddeaSArnaldo Carvalho de Melo * 29734a1cddeaSArnaldo Carvalho de Melo * This will be useful in the future when we need to support several 29744a1cddeaSArnaldo Carvalho de Melo * different extensions, and we need to apply more than one when 29754a1cddeaSArnaldo Carvalho de Melo * creating the object. See struct i915_user_extension. 29764a1cddeaSArnaldo Carvalho de Melo * 29774a1cddeaSArnaldo Carvalho de Melo * If we don't supply any extensions then we get the same old gem_create 29784a1cddeaSArnaldo Carvalho de Melo * behaviour. 29794a1cddeaSArnaldo Carvalho de Melo * 29804a1cddeaSArnaldo Carvalho de Melo * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see 29814a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_memory_regions. 29824a1cddeaSArnaldo Carvalho de Melo */ 29834a1cddeaSArnaldo Carvalho de Melo #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 29844a1cddeaSArnaldo Carvalho de Melo __u64 extensions; 29854a1cddeaSArnaldo Carvalho de Melo }; 29864a1cddeaSArnaldo Carvalho de Melo 29874a1cddeaSArnaldo Carvalho de Melo /** 29884a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_memory_regions - The 29894a1cddeaSArnaldo Carvalho de Melo * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. 29904a1cddeaSArnaldo Carvalho de Melo * 29914a1cddeaSArnaldo Carvalho de Melo * Set the object with the desired set of placements/regions in priority 29924a1cddeaSArnaldo Carvalho de Melo * order. Each entry must be unique and supported by the device. 29934a1cddeaSArnaldo Carvalho de Melo * 29944a1cddeaSArnaldo Carvalho de Melo * This is provided as an array of struct drm_i915_gem_memory_class_instance, or 29954a1cddeaSArnaldo Carvalho de Melo * an equivalent layout of class:instance pair encodings. See struct 29964a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to 29974a1cddeaSArnaldo Carvalho de Melo * query the supported regions for a device. 29984a1cddeaSArnaldo Carvalho de Melo * 29994a1cddeaSArnaldo Carvalho de Melo * As an example, on discrete devices, if we wish to set the placement as 30004a1cddeaSArnaldo Carvalho de Melo * device local-memory we can do something like: 30014a1cddeaSArnaldo Carvalho de Melo * 30024a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 30034a1cddeaSArnaldo Carvalho de Melo * 30044a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_memory_class_instance region_lmem = { 30054a1cddeaSArnaldo Carvalho de Melo * .memory_class = I915_MEMORY_CLASS_DEVICE, 30064a1cddeaSArnaldo Carvalho de Melo * .memory_instance = 0, 30074a1cddeaSArnaldo Carvalho de Melo * }; 30084a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_memory_regions regions = { 30094a1cddeaSArnaldo Carvalho de Melo * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, 30104a1cddeaSArnaldo Carvalho de Melo * .regions = (uintptr_t)®ion_lmem, 30114a1cddeaSArnaldo Carvalho de Melo * .num_regions = 1, 30124a1cddeaSArnaldo Carvalho de Melo * }; 30134a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext create_ext = { 30144a1cddeaSArnaldo Carvalho de Melo * .size = 16 * PAGE_SIZE, 30154a1cddeaSArnaldo Carvalho de Melo * .extensions = (uintptr_t)®ions, 30164a1cddeaSArnaldo Carvalho de Melo * }; 30174a1cddeaSArnaldo Carvalho de Melo * 30184a1cddeaSArnaldo Carvalho de Melo * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 30194a1cddeaSArnaldo Carvalho de Melo * if (err) ... 30204a1cddeaSArnaldo Carvalho de Melo * 30214a1cddeaSArnaldo Carvalho de Melo * At which point we get the object handle in &drm_i915_gem_create_ext.handle, 30224a1cddeaSArnaldo Carvalho de Melo * along with the final object size in &drm_i915_gem_create_ext.size, which 30234a1cddeaSArnaldo Carvalho de Melo * should account for any rounding up, if required. 30244a1cddeaSArnaldo Carvalho de Melo */ 30254a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_create_ext_memory_regions { 30264a1cddeaSArnaldo Carvalho de Melo /** @base: Extension link. See struct i915_user_extension. */ 30274a1cddeaSArnaldo Carvalho de Melo struct i915_user_extension base; 30284a1cddeaSArnaldo Carvalho de Melo 30294a1cddeaSArnaldo Carvalho de Melo /** @pad: MBZ */ 30304a1cddeaSArnaldo Carvalho de Melo __u32 pad; 30314a1cddeaSArnaldo Carvalho de Melo /** @num_regions: Number of elements in the @regions array. */ 30324a1cddeaSArnaldo Carvalho de Melo __u32 num_regions; 30334a1cddeaSArnaldo Carvalho de Melo /** 30344a1cddeaSArnaldo Carvalho de Melo * @regions: The regions/placements array. 30354a1cddeaSArnaldo Carvalho de Melo * 30364a1cddeaSArnaldo Carvalho de Melo * An array of struct drm_i915_gem_memory_class_instance. 30374a1cddeaSArnaldo Carvalho de Melo */ 30384a1cddeaSArnaldo Carvalho de Melo __u64 regions; 30394a1cddeaSArnaldo Carvalho de Melo }; 30404a1cddeaSArnaldo Carvalho de Melo 3041c1737f2bSArnaldo Carvalho de Melo #if defined(__cplusplus) 3042c1737f2bSArnaldo Carvalho de Melo } 3043c1737f2bSArnaldo Carvalho de Melo #endif 3044c1737f2bSArnaldo Carvalho de Melo 3045c1737f2bSArnaldo Carvalho de Melo #endif /* _UAPI_I915_DRM_H_ */ 3046