1c1737f2bSArnaldo Carvalho de Melo /* 2c1737f2bSArnaldo Carvalho de Melo * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c1737f2bSArnaldo Carvalho de Melo * All Rights Reserved. 4c1737f2bSArnaldo Carvalho de Melo * 5c1737f2bSArnaldo Carvalho de Melo * Permission is hereby granted, free of charge, to any person obtaining a 6c1737f2bSArnaldo Carvalho de Melo * copy of this software and associated documentation files (the 7c1737f2bSArnaldo Carvalho de Melo * "Software"), to deal in the Software without restriction, including 8c1737f2bSArnaldo Carvalho de Melo * without limitation the rights to use, copy, modify, merge, publish, 9c1737f2bSArnaldo Carvalho de Melo * distribute, sub license, and/or sell copies of the Software, and to 10c1737f2bSArnaldo Carvalho de Melo * permit persons to whom the Software is furnished to do so, subject to 11c1737f2bSArnaldo Carvalho de Melo * the following conditions: 12c1737f2bSArnaldo Carvalho de Melo * 13c1737f2bSArnaldo Carvalho de Melo * The above copyright notice and this permission notice (including the 14c1737f2bSArnaldo Carvalho de Melo * next paragraph) shall be included in all copies or substantial portions 15c1737f2bSArnaldo Carvalho de Melo * of the Software. 16c1737f2bSArnaldo Carvalho de Melo * 17c1737f2bSArnaldo Carvalho de Melo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c1737f2bSArnaldo Carvalho de Melo * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c1737f2bSArnaldo Carvalho de Melo * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c1737f2bSArnaldo Carvalho de Melo * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c1737f2bSArnaldo Carvalho de Melo * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c1737f2bSArnaldo Carvalho de Melo * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c1737f2bSArnaldo Carvalho de Melo * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c1737f2bSArnaldo Carvalho de Melo * 25c1737f2bSArnaldo Carvalho de Melo */ 26c1737f2bSArnaldo Carvalho de Melo 27c1737f2bSArnaldo Carvalho de Melo #ifndef _UAPI_I915_DRM_H_ 28c1737f2bSArnaldo Carvalho de Melo #define _UAPI_I915_DRM_H_ 29c1737f2bSArnaldo Carvalho de Melo 30c1737f2bSArnaldo Carvalho de Melo #include "drm.h" 31c1737f2bSArnaldo Carvalho de Melo 32c1737f2bSArnaldo Carvalho de Melo #if defined(__cplusplus) 33c1737f2bSArnaldo Carvalho de Melo extern "C" { 34c1737f2bSArnaldo Carvalho de Melo #endif 35c1737f2bSArnaldo Carvalho de Melo 36c1737f2bSArnaldo Carvalho de Melo /* Please note that modifications to all structs defined here are 37c1737f2bSArnaldo Carvalho de Melo * subject to backwards-compatibility constraints. 38c1737f2bSArnaldo Carvalho de Melo */ 39c1737f2bSArnaldo Carvalho de Melo 40c1737f2bSArnaldo Carvalho de Melo /** 41c1737f2bSArnaldo Carvalho de Melo * DOC: uevents generated by i915 on it's device node 42c1737f2bSArnaldo Carvalho de Melo * 43c1737f2bSArnaldo Carvalho de Melo * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44c1737f2bSArnaldo Carvalho de Melo * event from the gpu l3 cache. Additional information supplied is ROW, 45c1737f2bSArnaldo Carvalho de Melo * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46c1737f2bSArnaldo Carvalho de Melo * track of these events and if a specific cache-line seems to have a 47c1737f2bSArnaldo Carvalho de Melo * persistent error remap it with the l3 remapping tool supplied in 48c1737f2bSArnaldo Carvalho de Melo * intel-gpu-tools. The value supplied with the event is always 1. 49c1737f2bSArnaldo Carvalho de Melo * 50c1737f2bSArnaldo Carvalho de Melo * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51c1737f2bSArnaldo Carvalho de Melo * hangcheck. The error detection event is a good indicator of when things 52c1737f2bSArnaldo Carvalho de Melo * began to go badly. The value supplied with the event is a 1 upon error 53c1737f2bSArnaldo Carvalho de Melo * detection, and a 0 upon reset completion, signifying no more error 54c1737f2bSArnaldo Carvalho de Melo * exists. NOTE: Disabling hangcheck or reset via module parameter will 55c1737f2bSArnaldo Carvalho de Melo * cause the related events to not be seen. 56c1737f2bSArnaldo Carvalho de Melo * 57c1737f2bSArnaldo Carvalho de Melo * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58c1737f2bSArnaldo Carvalho de Melo * the GPU. The value supplied with the event is always 1. NOTE: Disable 59c1737f2bSArnaldo Carvalho de Melo * reset via module parameter will cause this event to not be seen. 60c1737f2bSArnaldo Carvalho de Melo */ 61c1737f2bSArnaldo Carvalho de Melo #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62c1737f2bSArnaldo Carvalho de Melo #define I915_ERROR_UEVENT "ERROR" 63c1737f2bSArnaldo Carvalho de Melo #define I915_RESET_UEVENT "RESET" 64c1737f2bSArnaldo Carvalho de Melo 65c1737f2bSArnaldo Carvalho de Melo /* 66c1737f2bSArnaldo Carvalho de Melo * MOCS indexes used for GPU surfaces, defining the cacheability of the 67c1737f2bSArnaldo Carvalho de Melo * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 68c1737f2bSArnaldo Carvalho de Melo */ 69c1737f2bSArnaldo Carvalho de Melo enum i915_mocs_table_index { 70c1737f2bSArnaldo Carvalho de Melo /* 71c1737f2bSArnaldo Carvalho de Melo * Not cached anywhere, coherency between CPU and GPU accesses is 72c1737f2bSArnaldo Carvalho de Melo * guaranteed. 73c1737f2bSArnaldo Carvalho de Melo */ 74c1737f2bSArnaldo Carvalho de Melo I915_MOCS_UNCACHED, 75c1737f2bSArnaldo Carvalho de Melo /* 76c1737f2bSArnaldo Carvalho de Melo * Cacheability and coherency controlled by the kernel automatically 77c1737f2bSArnaldo Carvalho de Melo * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 78c1737f2bSArnaldo Carvalho de Melo * usage of the surface (used for display scanout or not). 79c1737f2bSArnaldo Carvalho de Melo */ 80c1737f2bSArnaldo Carvalho de Melo I915_MOCS_PTE, 81c1737f2bSArnaldo Carvalho de Melo /* 82c1737f2bSArnaldo Carvalho de Melo * Cached in all GPU caches available on the platform. 83c1737f2bSArnaldo Carvalho de Melo * Coherency between CPU and GPU accesses to the surface is not 84c1737f2bSArnaldo Carvalho de Melo * guaranteed without extra synchronization. 85c1737f2bSArnaldo Carvalho de Melo */ 86c1737f2bSArnaldo Carvalho de Melo I915_MOCS_CACHED, 87c1737f2bSArnaldo Carvalho de Melo }; 88c1737f2bSArnaldo Carvalho de Melo 89f091f1d6SIngo Molnar /* 90f091f1d6SIngo Molnar * Different engines serve different roles, and there may be more than one 91f091f1d6SIngo Molnar * engine serving each role. enum drm_i915_gem_engine_class provides a 92f091f1d6SIngo Molnar * classification of the role of the engine, which may be used when requesting 93f091f1d6SIngo Molnar * operations to be performed on a certain subset of engines, or for providing 94f091f1d6SIngo Molnar * information about that group. 95f091f1d6SIngo Molnar */ 96f091f1d6SIngo Molnar enum drm_i915_gem_engine_class { 97f091f1d6SIngo Molnar I915_ENGINE_CLASS_RENDER = 0, 98f091f1d6SIngo Molnar I915_ENGINE_CLASS_COPY = 1, 99f091f1d6SIngo Molnar I915_ENGINE_CLASS_VIDEO = 2, 100f091f1d6SIngo Molnar I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 101f091f1d6SIngo Molnar 102f091f1d6SIngo Molnar I915_ENGINE_CLASS_INVALID = -1 103f091f1d6SIngo Molnar }; 104f091f1d6SIngo Molnar 105f091f1d6SIngo Molnar /** 106f091f1d6SIngo Molnar * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 107f091f1d6SIngo Molnar * 108f091f1d6SIngo Molnar */ 109f091f1d6SIngo Molnar 110f091f1d6SIngo Molnar enum drm_i915_pmu_engine_sample { 111f091f1d6SIngo Molnar I915_SAMPLE_BUSY = 0, 112f091f1d6SIngo Molnar I915_SAMPLE_WAIT = 1, 113f091f1d6SIngo Molnar I915_SAMPLE_SEMA = 2 114f091f1d6SIngo Molnar }; 115f091f1d6SIngo Molnar 116f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_BITS (4) 117f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_MASK (0xf) 118f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 119f091f1d6SIngo Molnar #define I915_PMU_CLASS_SHIFT \ 120f091f1d6SIngo Molnar (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 121f091f1d6SIngo Molnar 122f091f1d6SIngo Molnar #define __I915_PMU_ENGINE(class, instance, sample) \ 123f091f1d6SIngo Molnar ((class) << I915_PMU_CLASS_SHIFT | \ 124f091f1d6SIngo Molnar (instance) << I915_PMU_SAMPLE_BITS | \ 125f091f1d6SIngo Molnar (sample)) 126f091f1d6SIngo Molnar 127f091f1d6SIngo Molnar #define I915_PMU_ENGINE_BUSY(class, instance) \ 128f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 129f091f1d6SIngo Molnar 130f091f1d6SIngo Molnar #define I915_PMU_ENGINE_WAIT(class, instance) \ 131f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 132f091f1d6SIngo Molnar 133f091f1d6SIngo Molnar #define I915_PMU_ENGINE_SEMA(class, instance) \ 134f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 135f091f1d6SIngo Molnar 136f091f1d6SIngo Molnar #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 137f091f1d6SIngo Molnar 138f091f1d6SIngo Molnar #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 139f091f1d6SIngo Molnar #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 140f091f1d6SIngo Molnar #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 141f091f1d6SIngo Molnar #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 142f091f1d6SIngo Molnar 143f091f1d6SIngo Molnar #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 144f091f1d6SIngo Molnar 145c1737f2bSArnaldo Carvalho de Melo /* Each region is a minimum of 16k, and there are at most 255 of them. 146c1737f2bSArnaldo Carvalho de Melo */ 147c1737f2bSArnaldo Carvalho de Melo #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 148c1737f2bSArnaldo Carvalho de Melo * of chars for next/prev indices */ 149c1737f2bSArnaldo Carvalho de Melo #define I915_LOG_MIN_TEX_REGION_SIZE 14 150c1737f2bSArnaldo Carvalho de Melo 151c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_init { 152c1737f2bSArnaldo Carvalho de Melo enum { 153c1737f2bSArnaldo Carvalho de Melo I915_INIT_DMA = 0x01, 154c1737f2bSArnaldo Carvalho de Melo I915_CLEANUP_DMA = 0x02, 155c1737f2bSArnaldo Carvalho de Melo I915_RESUME_DMA = 0x03 156c1737f2bSArnaldo Carvalho de Melo } func; 157c1737f2bSArnaldo Carvalho de Melo unsigned int mmio_offset; 158c1737f2bSArnaldo Carvalho de Melo int sarea_priv_offset; 159c1737f2bSArnaldo Carvalho de Melo unsigned int ring_start; 160c1737f2bSArnaldo Carvalho de Melo unsigned int ring_end; 161c1737f2bSArnaldo Carvalho de Melo unsigned int ring_size; 162c1737f2bSArnaldo Carvalho de Melo unsigned int front_offset; 163c1737f2bSArnaldo Carvalho de Melo unsigned int back_offset; 164c1737f2bSArnaldo Carvalho de Melo unsigned int depth_offset; 165c1737f2bSArnaldo Carvalho de Melo unsigned int w; 166c1737f2bSArnaldo Carvalho de Melo unsigned int h; 167c1737f2bSArnaldo Carvalho de Melo unsigned int pitch; 168c1737f2bSArnaldo Carvalho de Melo unsigned int pitch_bits; 169c1737f2bSArnaldo Carvalho de Melo unsigned int back_pitch; 170c1737f2bSArnaldo Carvalho de Melo unsigned int depth_pitch; 171c1737f2bSArnaldo Carvalho de Melo unsigned int cpp; 172c1737f2bSArnaldo Carvalho de Melo unsigned int chipset; 173c1737f2bSArnaldo Carvalho de Melo } drm_i915_init_t; 174c1737f2bSArnaldo Carvalho de Melo 175c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_sarea { 176c1737f2bSArnaldo Carvalho de Melo struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 177c1737f2bSArnaldo Carvalho de Melo int last_upload; /* last time texture was uploaded */ 178c1737f2bSArnaldo Carvalho de Melo int last_enqueue; /* last time a buffer was enqueued */ 179c1737f2bSArnaldo Carvalho de Melo int last_dispatch; /* age of the most recently dispatched buffer */ 180c1737f2bSArnaldo Carvalho de Melo int ctxOwner; /* last context to upload state */ 181c1737f2bSArnaldo Carvalho de Melo int texAge; 182c1737f2bSArnaldo Carvalho de Melo int pf_enabled; /* is pageflipping allowed? */ 183c1737f2bSArnaldo Carvalho de Melo int pf_active; 184c1737f2bSArnaldo Carvalho de Melo int pf_current_page; /* which buffer is being displayed? */ 185c1737f2bSArnaldo Carvalho de Melo int perf_boxes; /* performance boxes to be displayed */ 186c1737f2bSArnaldo Carvalho de Melo int width, height; /* screen size in pixels */ 187c1737f2bSArnaldo Carvalho de Melo 188c1737f2bSArnaldo Carvalho de Melo drm_handle_t front_handle; 189c1737f2bSArnaldo Carvalho de Melo int front_offset; 190c1737f2bSArnaldo Carvalho de Melo int front_size; 191c1737f2bSArnaldo Carvalho de Melo 192c1737f2bSArnaldo Carvalho de Melo drm_handle_t back_handle; 193c1737f2bSArnaldo Carvalho de Melo int back_offset; 194c1737f2bSArnaldo Carvalho de Melo int back_size; 195c1737f2bSArnaldo Carvalho de Melo 196c1737f2bSArnaldo Carvalho de Melo drm_handle_t depth_handle; 197c1737f2bSArnaldo Carvalho de Melo int depth_offset; 198c1737f2bSArnaldo Carvalho de Melo int depth_size; 199c1737f2bSArnaldo Carvalho de Melo 200c1737f2bSArnaldo Carvalho de Melo drm_handle_t tex_handle; 201c1737f2bSArnaldo Carvalho de Melo int tex_offset; 202c1737f2bSArnaldo Carvalho de Melo int tex_size; 203c1737f2bSArnaldo Carvalho de Melo int log_tex_granularity; 204c1737f2bSArnaldo Carvalho de Melo int pitch; 205c1737f2bSArnaldo Carvalho de Melo int rotation; /* 0, 90, 180 or 270 */ 206c1737f2bSArnaldo Carvalho de Melo int rotated_offset; 207c1737f2bSArnaldo Carvalho de Melo int rotated_size; 208c1737f2bSArnaldo Carvalho de Melo int rotated_pitch; 209c1737f2bSArnaldo Carvalho de Melo int virtualX, virtualY; 210c1737f2bSArnaldo Carvalho de Melo 211c1737f2bSArnaldo Carvalho de Melo unsigned int front_tiled; 212c1737f2bSArnaldo Carvalho de Melo unsigned int back_tiled; 213c1737f2bSArnaldo Carvalho de Melo unsigned int depth_tiled; 214c1737f2bSArnaldo Carvalho de Melo unsigned int rotated_tiled; 215c1737f2bSArnaldo Carvalho de Melo unsigned int rotated2_tiled; 216c1737f2bSArnaldo Carvalho de Melo 217c1737f2bSArnaldo Carvalho de Melo int pipeA_x; 218c1737f2bSArnaldo Carvalho de Melo int pipeA_y; 219c1737f2bSArnaldo Carvalho de Melo int pipeA_w; 220c1737f2bSArnaldo Carvalho de Melo int pipeA_h; 221c1737f2bSArnaldo Carvalho de Melo int pipeB_x; 222c1737f2bSArnaldo Carvalho de Melo int pipeB_y; 223c1737f2bSArnaldo Carvalho de Melo int pipeB_w; 224c1737f2bSArnaldo Carvalho de Melo int pipeB_h; 225c1737f2bSArnaldo Carvalho de Melo 226c1737f2bSArnaldo Carvalho de Melo /* fill out some space for old userspace triple buffer */ 227c1737f2bSArnaldo Carvalho de Melo drm_handle_t unused_handle; 228c1737f2bSArnaldo Carvalho de Melo __u32 unused1, unused2, unused3; 229c1737f2bSArnaldo Carvalho de Melo 230c1737f2bSArnaldo Carvalho de Melo /* buffer object handles for static buffers. May change 231c1737f2bSArnaldo Carvalho de Melo * over the lifetime of the client. 232c1737f2bSArnaldo Carvalho de Melo */ 233c1737f2bSArnaldo Carvalho de Melo __u32 front_bo_handle; 234c1737f2bSArnaldo Carvalho de Melo __u32 back_bo_handle; 235c1737f2bSArnaldo Carvalho de Melo __u32 unused_bo_handle; 236c1737f2bSArnaldo Carvalho de Melo __u32 depth_bo_handle; 237c1737f2bSArnaldo Carvalho de Melo 238c1737f2bSArnaldo Carvalho de Melo } drm_i915_sarea_t; 239c1737f2bSArnaldo Carvalho de Melo 240c1737f2bSArnaldo Carvalho de Melo /* due to userspace building against these headers we need some compat here */ 241c1737f2bSArnaldo Carvalho de Melo #define planeA_x pipeA_x 242c1737f2bSArnaldo Carvalho de Melo #define planeA_y pipeA_y 243c1737f2bSArnaldo Carvalho de Melo #define planeA_w pipeA_w 244c1737f2bSArnaldo Carvalho de Melo #define planeA_h pipeA_h 245c1737f2bSArnaldo Carvalho de Melo #define planeB_x pipeB_x 246c1737f2bSArnaldo Carvalho de Melo #define planeB_y pipeB_y 247c1737f2bSArnaldo Carvalho de Melo #define planeB_w pipeB_w 248c1737f2bSArnaldo Carvalho de Melo #define planeB_h pipeB_h 249c1737f2bSArnaldo Carvalho de Melo 250c1737f2bSArnaldo Carvalho de Melo /* Flags for perf_boxes 251c1737f2bSArnaldo Carvalho de Melo */ 252c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_RING_EMPTY 0x1 253c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_FLIP 0x2 254c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_WAIT 0x4 255c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_TEXTURE_LOAD 0x8 256c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_LOST_CONTEXT 0x10 257c1737f2bSArnaldo Carvalho de Melo 258c1737f2bSArnaldo Carvalho de Melo /* 259c1737f2bSArnaldo Carvalho de Melo * i915 specific ioctls. 260c1737f2bSArnaldo Carvalho de Melo * 261c1737f2bSArnaldo Carvalho de Melo * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 262c1737f2bSArnaldo Carvalho de Melo * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 263c1737f2bSArnaldo Carvalho de Melo * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 264c1737f2bSArnaldo Carvalho de Melo */ 265c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_INIT 0x00 266c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FLUSH 0x01 267c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FLIP 0x02 268c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_BATCHBUFFER 0x03 269c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_IRQ_EMIT 0x04 270c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_IRQ_WAIT 0x05 271c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GETPARAM 0x06 272c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SETPARAM 0x07 273c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_ALLOC 0x08 274c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FREE 0x09 275c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_INIT_HEAP 0x0a 276c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_CMDBUFFER 0x0b 277c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_DESTROY_HEAP 0x0c 278c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SET_VBLANK_PIPE 0x0d 279c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_VBLANK_PIPE 0x0e 280c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_SWAP 0x0f 281c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_HWS_ADDR 0x11 282c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_INIT 0x13 283c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER 0x14 284c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PIN 0x15 285c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_UNPIN 0x16 286c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_BUSY 0x17 287c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_THROTTLE 0x18 288c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_ENTERVT 0x19 289c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_LEAVEVT 0x1a 290c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CREATE 0x1b 291c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PREAD 0x1c 292c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PWRITE 0x1d 293c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MMAP 0x1e 294c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_DOMAIN 0x1f 295c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SW_FINISH 0x20 296c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_TILING 0x21 297c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_TILING 0x22 298c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_APERTURE 0x23 299c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MMAP_GTT 0x24 300c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 301c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MADVISE 0x26 302c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 303c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_OVERLAY_ATTRS 0x28 304c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER2 0x29 305c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 306c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 307c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 308c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_WAIT 0x2c 309c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 310c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 311c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_CACHING 0x2f 312c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_CACHING 0x30 313c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_REG_READ 0x31 314c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_RESET_STATS 0x32 315c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_USERPTR 0x33 316c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 317c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 318c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_PERF_OPEN 0x36 319549a3976SIngo Molnar #define DRM_I915_PERF_ADD_CONFIG 0x37 320549a3976SIngo Molnar #define DRM_I915_PERF_REMOVE_CONFIG 0x38 32101f97511SArnaldo Carvalho de Melo #define DRM_I915_QUERY 0x39 322c1737f2bSArnaldo Carvalho de Melo 323c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 324c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 325c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 326c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 327c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 328c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 329c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 330c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 331c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 332c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 333c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 334c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 335c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 336c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 337c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 338c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 339c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 340c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 341c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 342c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 343c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 344c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 345c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 346c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 347c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 348c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 349c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 350c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 351c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 352c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 353c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 354c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 355c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 356c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 357c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 358c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 359c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 360c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 361c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 362c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 363c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 364c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 365c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 366c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 367c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 368c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 369c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 370c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 371c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 372c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 373c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 374c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 375c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 376c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 377549a3976SIngo Molnar #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 378549a3976SIngo Molnar #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 37901f97511SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 380c1737f2bSArnaldo Carvalho de Melo 381c1737f2bSArnaldo Carvalho de Melo /* Allow drivers to submit batchbuffers directly to hardware, relying 382c1737f2bSArnaldo Carvalho de Melo * on the security mechanisms provided by hardware. 383c1737f2bSArnaldo Carvalho de Melo */ 384c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_batchbuffer { 385c1737f2bSArnaldo Carvalho de Melo int start; /* agp offset */ 386c1737f2bSArnaldo Carvalho de Melo int used; /* nr bytes in use */ 387c1737f2bSArnaldo Carvalho de Melo int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 388c1737f2bSArnaldo Carvalho de Melo int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 389c1737f2bSArnaldo Carvalho de Melo int num_cliprects; /* mulitpass with multiple cliprects? */ 390c1737f2bSArnaldo Carvalho de Melo struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 391c1737f2bSArnaldo Carvalho de Melo } drm_i915_batchbuffer_t; 392c1737f2bSArnaldo Carvalho de Melo 393c1737f2bSArnaldo Carvalho de Melo /* As above, but pass a pointer to userspace buffer which can be 394c1737f2bSArnaldo Carvalho de Melo * validated by the kernel prior to sending to hardware. 395c1737f2bSArnaldo Carvalho de Melo */ 396c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_cmdbuffer { 397c1737f2bSArnaldo Carvalho de Melo char __user *buf; /* pointer to userspace command buffer */ 398c1737f2bSArnaldo Carvalho de Melo int sz; /* nr bytes in buf */ 399c1737f2bSArnaldo Carvalho de Melo int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 400c1737f2bSArnaldo Carvalho de Melo int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 401c1737f2bSArnaldo Carvalho de Melo int num_cliprects; /* mulitpass with multiple cliprects? */ 402c1737f2bSArnaldo Carvalho de Melo struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 403c1737f2bSArnaldo Carvalho de Melo } drm_i915_cmdbuffer_t; 404c1737f2bSArnaldo Carvalho de Melo 405c1737f2bSArnaldo Carvalho de Melo /* Userspace can request & wait on irq's: 406c1737f2bSArnaldo Carvalho de Melo */ 407c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_irq_emit { 408c1737f2bSArnaldo Carvalho de Melo int __user *irq_seq; 409c1737f2bSArnaldo Carvalho de Melo } drm_i915_irq_emit_t; 410c1737f2bSArnaldo Carvalho de Melo 411c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_irq_wait { 412c1737f2bSArnaldo Carvalho de Melo int irq_seq; 413c1737f2bSArnaldo Carvalho de Melo } drm_i915_irq_wait_t; 414c1737f2bSArnaldo Carvalho de Melo 415c1737f2bSArnaldo Carvalho de Melo /* Ioctl to query kernel params: 416c1737f2bSArnaldo Carvalho de Melo */ 417c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_IRQ_ACTIVE 1 418c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_ALLOW_BATCHBUFFER 2 419c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_LAST_DISPATCH 3 420c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_CHIPSET_ID 4 421c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GEM 5 422c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_NUM_FENCES_AVAIL 6 423c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_OVERLAY 7 424c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PAGEFLIPPING 8 425c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXECBUF2 9 426c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BSD 10 427c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BLT 11 428c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RELAXED_FENCING 12 429c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_COHERENT_RINGS 13 430c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_CONSTANTS 14 431c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RELAXED_DELTA 15 432c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GEN7_SOL_RESET 16 433c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_LLC 17 434c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_ALIASING_PPGTT 18 435c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_WAIT_TIMEOUT 19 436c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SEMAPHORES 20 437c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 438c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_VEBOX 22 439c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SECURE_BATCHES 23 440c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PINNED_BATCHES 24 441c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_NO_RELOC 25 442c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 443c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_WT 27 444c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_CMD_PARSER_VERSION 28 445c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 446c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MMAP_VERSION 30 447c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BSD2 31 448c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_REVISION 32 449c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SUBSLICE_TOTAL 33 450c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_EU_TOTAL 34 451c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GPU_RESET 35 452c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RESOURCE_STREAMER 36 453c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_SOFTPIN 37 454c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_POOLED_EU 38 455c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MIN_EU_IN_POOL 39 456c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MMAP_GTT_VERSION 40 457c1737f2bSArnaldo Carvalho de Melo 458485be0cbSArnaldo Carvalho de Melo /* 459485be0cbSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 460c1737f2bSArnaldo Carvalho de Melo * priorities and the driver will attempt to execute batches in priority order. 461485be0cbSArnaldo Carvalho de Melo * The param returns a capability bitmask, nonzero implies that the scheduler 462485be0cbSArnaldo Carvalho de Melo * is enabled, with different features present according to the mask. 463485be0cbSArnaldo Carvalho de Melo * 464485be0cbSArnaldo Carvalho de Melo * The initial priority for each batch is supplied by the context and is 465485be0cbSArnaldo Carvalho de Melo * controlled via I915_CONTEXT_PARAM_PRIORITY. 466c1737f2bSArnaldo Carvalho de Melo */ 467c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SCHEDULER 41 468485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 469485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 470485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 471485be0cbSArnaldo Carvalho de Melo 472c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HUC_STATUS 42 473c1737f2bSArnaldo Carvalho de Melo 474c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 475c1737f2bSArnaldo Carvalho de Melo * synchronisation with implicit fencing on individual objects. 476c1737f2bSArnaldo Carvalho de Melo * See EXEC_OBJECT_ASYNC. 477c1737f2bSArnaldo Carvalho de Melo */ 478c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_ASYNC 43 479c1737f2bSArnaldo Carvalho de Melo 480c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 481c1737f2bSArnaldo Carvalho de Melo * both being able to pass in a sync_file fd to wait upon before executing, 482c1737f2bSArnaldo Carvalho de Melo * and being able to return a new sync_file fd that is signaled when the 483c1737f2bSArnaldo Carvalho de Melo * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 484c1737f2bSArnaldo Carvalho de Melo */ 485c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_FENCE 44 486c1737f2bSArnaldo Carvalho de Melo 487c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 488c1737f2bSArnaldo Carvalho de Melo * user specified bufffers for post-mortem debugging of GPU hangs. See 489c1737f2bSArnaldo Carvalho de Melo * EXEC_OBJECT_CAPTURE. 490c1737f2bSArnaldo Carvalho de Melo */ 491c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_CAPTURE 45 492c1737f2bSArnaldo Carvalho de Melo 493c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SLICE_MASK 46 494c1737f2bSArnaldo Carvalho de Melo 495c1737f2bSArnaldo Carvalho de Melo /* Assuming it's uniform for each slice, this queries the mask of subslices 496c1737f2bSArnaldo Carvalho de Melo * per-slice for this system. 497c1737f2bSArnaldo Carvalho de Melo */ 498c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SUBSLICE_MASK 47 499c1737f2bSArnaldo Carvalho de Melo 500c1737f2bSArnaldo Carvalho de Melo /* 501c1737f2bSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 502c1737f2bSArnaldo Carvalho de Melo * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 503c1737f2bSArnaldo Carvalho de Melo */ 504c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 505c1737f2bSArnaldo Carvalho de Melo 506549a3976SIngo Molnar /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 507549a3976SIngo Molnar * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 508549a3976SIngo Molnar */ 509549a3976SIngo Molnar #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 510549a3976SIngo Molnar 511f091f1d6SIngo Molnar /* 512f091f1d6SIngo Molnar * Query whether every context (both per-file default and user created) is 513f091f1d6SIngo Molnar * isolated (insofar as HW supports). If this parameter is not true, then 514f091f1d6SIngo Molnar * freshly created contexts may inherit values from an existing context, 515f091f1d6SIngo Molnar * rather than default HW values. If true, it also ensures (insofar as HW 516f091f1d6SIngo Molnar * supports) that all state set by this context will not leak to any other 517f091f1d6SIngo Molnar * context. 518f091f1d6SIngo Molnar * 519f091f1d6SIngo Molnar * As not every engine across every gen support contexts, the returned 520f091f1d6SIngo Molnar * value reports the support of context isolation for individual engines by 521f091f1d6SIngo Molnar * returning a bitmask of each engine class set to true if that class supports 522f091f1d6SIngo Molnar * isolation. 523f091f1d6SIngo Molnar */ 524f091f1d6SIngo Molnar #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 525f091f1d6SIngo Molnar 526f091f1d6SIngo Molnar /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 527f091f1d6SIngo Molnar * registers. This used to be fixed per platform but from CNL onwards, this 528f091f1d6SIngo Molnar * might vary depending on the parts. 529f091f1d6SIngo Molnar */ 530f091f1d6SIngo Molnar #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 531f091f1d6SIngo Molnar 532c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_getparam { 533c1737f2bSArnaldo Carvalho de Melo __s32 param; 534c1737f2bSArnaldo Carvalho de Melo /* 535c1737f2bSArnaldo Carvalho de Melo * WARNING: Using pointers instead of fixed-size u64 means we need to write 536c1737f2bSArnaldo Carvalho de Melo * compat32 code. Don't repeat this mistake. 537c1737f2bSArnaldo Carvalho de Melo */ 538c1737f2bSArnaldo Carvalho de Melo int __user *value; 539c1737f2bSArnaldo Carvalho de Melo } drm_i915_getparam_t; 540c1737f2bSArnaldo Carvalho de Melo 541c1737f2bSArnaldo Carvalho de Melo /* Ioctl to set kernel params: 542c1737f2bSArnaldo Carvalho de Melo */ 543c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 544c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 545c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 546c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_NUM_USED_FENCES 4 547c1737f2bSArnaldo Carvalho de Melo 548c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_setparam { 549c1737f2bSArnaldo Carvalho de Melo int param; 550c1737f2bSArnaldo Carvalho de Melo int value; 551c1737f2bSArnaldo Carvalho de Melo } drm_i915_setparam_t; 552c1737f2bSArnaldo Carvalho de Melo 553c1737f2bSArnaldo Carvalho de Melo /* A memory manager for regions of shared memory: 554c1737f2bSArnaldo Carvalho de Melo */ 555c1737f2bSArnaldo Carvalho de Melo #define I915_MEM_REGION_AGP 1 556c1737f2bSArnaldo Carvalho de Melo 557c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_alloc { 558c1737f2bSArnaldo Carvalho de Melo int region; 559c1737f2bSArnaldo Carvalho de Melo int alignment; 560c1737f2bSArnaldo Carvalho de Melo int size; 561c1737f2bSArnaldo Carvalho de Melo int __user *region_offset; /* offset from start of fb or agp */ 562c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_alloc_t; 563c1737f2bSArnaldo Carvalho de Melo 564c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_free { 565c1737f2bSArnaldo Carvalho de Melo int region; 566c1737f2bSArnaldo Carvalho de Melo int region_offset; 567c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_free_t; 568c1737f2bSArnaldo Carvalho de Melo 569c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_init_heap { 570c1737f2bSArnaldo Carvalho de Melo int region; 571c1737f2bSArnaldo Carvalho de Melo int size; 572c1737f2bSArnaldo Carvalho de Melo int start; 573c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_init_heap_t; 574c1737f2bSArnaldo Carvalho de Melo 575c1737f2bSArnaldo Carvalho de Melo /* Allow memory manager to be torn down and re-initialized (eg on 576c1737f2bSArnaldo Carvalho de Melo * rotate): 577c1737f2bSArnaldo Carvalho de Melo */ 578c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_destroy_heap { 579c1737f2bSArnaldo Carvalho de Melo int region; 580c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_destroy_heap_t; 581c1737f2bSArnaldo Carvalho de Melo 582c1737f2bSArnaldo Carvalho de Melo /* Allow X server to configure which pipes to monitor for vblank signals 583c1737f2bSArnaldo Carvalho de Melo */ 584c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_PIPE_A 1 585c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_PIPE_B 2 586c1737f2bSArnaldo Carvalho de Melo 587c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_vblank_pipe { 588c1737f2bSArnaldo Carvalho de Melo int pipe; 589c1737f2bSArnaldo Carvalho de Melo } drm_i915_vblank_pipe_t; 590c1737f2bSArnaldo Carvalho de Melo 591c1737f2bSArnaldo Carvalho de Melo /* Schedule buffer swap at given vertical blank: 592c1737f2bSArnaldo Carvalho de Melo */ 593c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_vblank_swap { 594c1737f2bSArnaldo Carvalho de Melo drm_drawable_t drawable; 595c1737f2bSArnaldo Carvalho de Melo enum drm_vblank_seq_type seqtype; 596c1737f2bSArnaldo Carvalho de Melo unsigned int sequence; 597c1737f2bSArnaldo Carvalho de Melo } drm_i915_vblank_swap_t; 598c1737f2bSArnaldo Carvalho de Melo 599c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_hws_addr { 600c1737f2bSArnaldo Carvalho de Melo __u64 addr; 601c1737f2bSArnaldo Carvalho de Melo } drm_i915_hws_addr_t; 602c1737f2bSArnaldo Carvalho de Melo 603c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_init { 604c1737f2bSArnaldo Carvalho de Melo /** 605c1737f2bSArnaldo Carvalho de Melo * Beginning offset in the GTT to be managed by the DRM memory 606c1737f2bSArnaldo Carvalho de Melo * manager. 607c1737f2bSArnaldo Carvalho de Melo */ 608c1737f2bSArnaldo Carvalho de Melo __u64 gtt_start; 609c1737f2bSArnaldo Carvalho de Melo /** 610c1737f2bSArnaldo Carvalho de Melo * Ending offset in the GTT to be managed by the DRM memory 611c1737f2bSArnaldo Carvalho de Melo * manager. 612c1737f2bSArnaldo Carvalho de Melo */ 613c1737f2bSArnaldo Carvalho de Melo __u64 gtt_end; 614c1737f2bSArnaldo Carvalho de Melo }; 615c1737f2bSArnaldo Carvalho de Melo 616c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_create { 617c1737f2bSArnaldo Carvalho de Melo /** 618c1737f2bSArnaldo Carvalho de Melo * Requested size for the object. 619c1737f2bSArnaldo Carvalho de Melo * 620c1737f2bSArnaldo Carvalho de Melo * The (page-aligned) allocated size for the object will be returned. 621c1737f2bSArnaldo Carvalho de Melo */ 622c1737f2bSArnaldo Carvalho de Melo __u64 size; 623c1737f2bSArnaldo Carvalho de Melo /** 624c1737f2bSArnaldo Carvalho de Melo * Returned handle for the object. 625c1737f2bSArnaldo Carvalho de Melo * 626c1737f2bSArnaldo Carvalho de Melo * Object handles are nonzero. 627c1737f2bSArnaldo Carvalho de Melo */ 628c1737f2bSArnaldo Carvalho de Melo __u32 handle; 629c1737f2bSArnaldo Carvalho de Melo __u32 pad; 630c1737f2bSArnaldo Carvalho de Melo }; 631c1737f2bSArnaldo Carvalho de Melo 632c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pread { 633c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being read. */ 634c1737f2bSArnaldo Carvalho de Melo __u32 handle; 635c1737f2bSArnaldo Carvalho de Melo __u32 pad; 636c1737f2bSArnaldo Carvalho de Melo /** Offset into the object to read from */ 637c1737f2bSArnaldo Carvalho de Melo __u64 offset; 638c1737f2bSArnaldo Carvalho de Melo /** Length of data to read */ 639c1737f2bSArnaldo Carvalho de Melo __u64 size; 640c1737f2bSArnaldo Carvalho de Melo /** 641c1737f2bSArnaldo Carvalho de Melo * Pointer to write the data into. 642c1737f2bSArnaldo Carvalho de Melo * 643c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 644c1737f2bSArnaldo Carvalho de Melo */ 645c1737f2bSArnaldo Carvalho de Melo __u64 data_ptr; 646c1737f2bSArnaldo Carvalho de Melo }; 647c1737f2bSArnaldo Carvalho de Melo 648c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pwrite { 649c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being written to. */ 650c1737f2bSArnaldo Carvalho de Melo __u32 handle; 651c1737f2bSArnaldo Carvalho de Melo __u32 pad; 652c1737f2bSArnaldo Carvalho de Melo /** Offset into the object to write to */ 653c1737f2bSArnaldo Carvalho de Melo __u64 offset; 654c1737f2bSArnaldo Carvalho de Melo /** Length of data to write */ 655c1737f2bSArnaldo Carvalho de Melo __u64 size; 656c1737f2bSArnaldo Carvalho de Melo /** 657c1737f2bSArnaldo Carvalho de Melo * Pointer to read the data from. 658c1737f2bSArnaldo Carvalho de Melo * 659c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 660c1737f2bSArnaldo Carvalho de Melo */ 661c1737f2bSArnaldo Carvalho de Melo __u64 data_ptr; 662c1737f2bSArnaldo Carvalho de Melo }; 663c1737f2bSArnaldo Carvalho de Melo 664c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_mmap { 665c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being mapped. */ 666c1737f2bSArnaldo Carvalho de Melo __u32 handle; 667c1737f2bSArnaldo Carvalho de Melo __u32 pad; 668c1737f2bSArnaldo Carvalho de Melo /** Offset in the object to map. */ 669c1737f2bSArnaldo Carvalho de Melo __u64 offset; 670c1737f2bSArnaldo Carvalho de Melo /** 671c1737f2bSArnaldo Carvalho de Melo * Length of data to map. 672c1737f2bSArnaldo Carvalho de Melo * 673c1737f2bSArnaldo Carvalho de Melo * The value will be page-aligned. 674c1737f2bSArnaldo Carvalho de Melo */ 675c1737f2bSArnaldo Carvalho de Melo __u64 size; 676c1737f2bSArnaldo Carvalho de Melo /** 677c1737f2bSArnaldo Carvalho de Melo * Returned pointer the data was mapped at. 678c1737f2bSArnaldo Carvalho de Melo * 679c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 680c1737f2bSArnaldo Carvalho de Melo */ 681c1737f2bSArnaldo Carvalho de Melo __u64 addr_ptr; 682c1737f2bSArnaldo Carvalho de Melo 683c1737f2bSArnaldo Carvalho de Melo /** 684c1737f2bSArnaldo Carvalho de Melo * Flags for extended behaviour. 685c1737f2bSArnaldo Carvalho de Melo * 686c1737f2bSArnaldo Carvalho de Melo * Added in version 2. 687c1737f2bSArnaldo Carvalho de Melo */ 688c1737f2bSArnaldo Carvalho de Melo __u64 flags; 689c1737f2bSArnaldo Carvalho de Melo #define I915_MMAP_WC 0x1 690c1737f2bSArnaldo Carvalho de Melo }; 691c1737f2bSArnaldo Carvalho de Melo 692c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_mmap_gtt { 693c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being mapped. */ 694c1737f2bSArnaldo Carvalho de Melo __u32 handle; 695c1737f2bSArnaldo Carvalho de Melo __u32 pad; 696c1737f2bSArnaldo Carvalho de Melo /** 697c1737f2bSArnaldo Carvalho de Melo * Fake offset to use for subsequent mmap call 698c1737f2bSArnaldo Carvalho de Melo * 699c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 700c1737f2bSArnaldo Carvalho de Melo */ 701c1737f2bSArnaldo Carvalho de Melo __u64 offset; 702c1737f2bSArnaldo Carvalho de Melo }; 703c1737f2bSArnaldo Carvalho de Melo 704c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_set_domain { 705c1737f2bSArnaldo Carvalho de Melo /** Handle for the object */ 706c1737f2bSArnaldo Carvalho de Melo __u32 handle; 707c1737f2bSArnaldo Carvalho de Melo 708c1737f2bSArnaldo Carvalho de Melo /** New read domains */ 709c1737f2bSArnaldo Carvalho de Melo __u32 read_domains; 710c1737f2bSArnaldo Carvalho de Melo 711c1737f2bSArnaldo Carvalho de Melo /** New write domain */ 712c1737f2bSArnaldo Carvalho de Melo __u32 write_domain; 713c1737f2bSArnaldo Carvalho de Melo }; 714c1737f2bSArnaldo Carvalho de Melo 715c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_sw_finish { 716c1737f2bSArnaldo Carvalho de Melo /** Handle for the object */ 717c1737f2bSArnaldo Carvalho de Melo __u32 handle; 718c1737f2bSArnaldo Carvalho de Melo }; 719c1737f2bSArnaldo Carvalho de Melo 720c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_relocation_entry { 721c1737f2bSArnaldo Carvalho de Melo /** 722c1737f2bSArnaldo Carvalho de Melo * Handle of the buffer being pointed to by this relocation entry. 723c1737f2bSArnaldo Carvalho de Melo * 724c1737f2bSArnaldo Carvalho de Melo * It's appealing to make this be an index into the mm_validate_entry 725c1737f2bSArnaldo Carvalho de Melo * list to refer to the buffer, but this allows the driver to create 726c1737f2bSArnaldo Carvalho de Melo * a relocation list for state buffers and not re-write it per 727c1737f2bSArnaldo Carvalho de Melo * exec using the buffer. 728c1737f2bSArnaldo Carvalho de Melo */ 729c1737f2bSArnaldo Carvalho de Melo __u32 target_handle; 730c1737f2bSArnaldo Carvalho de Melo 731c1737f2bSArnaldo Carvalho de Melo /** 732c1737f2bSArnaldo Carvalho de Melo * Value to be added to the offset of the target buffer to make up 733c1737f2bSArnaldo Carvalho de Melo * the relocation entry. 734c1737f2bSArnaldo Carvalho de Melo */ 735c1737f2bSArnaldo Carvalho de Melo __u32 delta; 736c1737f2bSArnaldo Carvalho de Melo 737c1737f2bSArnaldo Carvalho de Melo /** Offset in the buffer the relocation entry will be written into */ 738c1737f2bSArnaldo Carvalho de Melo __u64 offset; 739c1737f2bSArnaldo Carvalho de Melo 740c1737f2bSArnaldo Carvalho de Melo /** 741c1737f2bSArnaldo Carvalho de Melo * Offset value of the target buffer that the relocation entry was last 742c1737f2bSArnaldo Carvalho de Melo * written as. 743c1737f2bSArnaldo Carvalho de Melo * 744c1737f2bSArnaldo Carvalho de Melo * If the buffer has the same offset as last time, we can skip syncing 745c1737f2bSArnaldo Carvalho de Melo * and writing the relocation. This value is written back out by 746c1737f2bSArnaldo Carvalho de Melo * the execbuffer ioctl when the relocation is written. 747c1737f2bSArnaldo Carvalho de Melo */ 748c1737f2bSArnaldo Carvalho de Melo __u64 presumed_offset; 749c1737f2bSArnaldo Carvalho de Melo 750c1737f2bSArnaldo Carvalho de Melo /** 751c1737f2bSArnaldo Carvalho de Melo * Target memory domains read by this operation. 752c1737f2bSArnaldo Carvalho de Melo */ 753c1737f2bSArnaldo Carvalho de Melo __u32 read_domains; 754c1737f2bSArnaldo Carvalho de Melo 755c1737f2bSArnaldo Carvalho de Melo /** 756c1737f2bSArnaldo Carvalho de Melo * Target memory domains written by this operation. 757c1737f2bSArnaldo Carvalho de Melo * 758c1737f2bSArnaldo Carvalho de Melo * Note that only one domain may be written by the whole 759c1737f2bSArnaldo Carvalho de Melo * execbuffer operation, so that where there are conflicts, 760c1737f2bSArnaldo Carvalho de Melo * the application will get -EINVAL back. 761c1737f2bSArnaldo Carvalho de Melo */ 762c1737f2bSArnaldo Carvalho de Melo __u32 write_domain; 763c1737f2bSArnaldo Carvalho de Melo }; 764c1737f2bSArnaldo Carvalho de Melo 765c1737f2bSArnaldo Carvalho de Melo /** @{ 766c1737f2bSArnaldo Carvalho de Melo * Intel memory domains 767c1737f2bSArnaldo Carvalho de Melo * 768c1737f2bSArnaldo Carvalho de Melo * Most of these just align with the various caches in 769c1737f2bSArnaldo Carvalho de Melo * the system and are used to flush and invalidate as 770c1737f2bSArnaldo Carvalho de Melo * objects end up cached in different domains. 771c1737f2bSArnaldo Carvalho de Melo */ 772c1737f2bSArnaldo Carvalho de Melo /** CPU cache */ 773c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_CPU 0x00000001 774c1737f2bSArnaldo Carvalho de Melo /** Render cache, used by 2D and 3D drawing */ 775c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_RENDER 0x00000002 776c1737f2bSArnaldo Carvalho de Melo /** Sampler cache, used by texture engine */ 777c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_SAMPLER 0x00000004 778c1737f2bSArnaldo Carvalho de Melo /** Command queue, used to load batch buffers */ 779c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_COMMAND 0x00000008 780c1737f2bSArnaldo Carvalho de Melo /** Instruction cache, used by shader programs */ 781c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 782c1737f2bSArnaldo Carvalho de Melo /** Vertex address cache */ 783c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_VERTEX 0x00000020 784c1737f2bSArnaldo Carvalho de Melo /** GTT domain - aperture and scanout */ 785c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_GTT 0x00000040 786c1737f2bSArnaldo Carvalho de Melo /** WC domain - uncached access */ 787c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_WC 0x00000080 788c1737f2bSArnaldo Carvalho de Melo /** @} */ 789c1737f2bSArnaldo Carvalho de Melo 790c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_exec_object { 791c1737f2bSArnaldo Carvalho de Melo /** 792c1737f2bSArnaldo Carvalho de Melo * User's handle for a buffer to be bound into the GTT for this 793c1737f2bSArnaldo Carvalho de Melo * operation. 794c1737f2bSArnaldo Carvalho de Melo */ 795c1737f2bSArnaldo Carvalho de Melo __u32 handle; 796c1737f2bSArnaldo Carvalho de Melo 797c1737f2bSArnaldo Carvalho de Melo /** Number of relocations to be performed on this buffer */ 798c1737f2bSArnaldo Carvalho de Melo __u32 relocation_count; 799c1737f2bSArnaldo Carvalho de Melo /** 800c1737f2bSArnaldo Carvalho de Melo * Pointer to array of struct drm_i915_gem_relocation_entry containing 801c1737f2bSArnaldo Carvalho de Melo * the relocations to be performed in this buffer. 802c1737f2bSArnaldo Carvalho de Melo */ 803c1737f2bSArnaldo Carvalho de Melo __u64 relocs_ptr; 804c1737f2bSArnaldo Carvalho de Melo 805c1737f2bSArnaldo Carvalho de Melo /** Required alignment in graphics aperture */ 806c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 807c1737f2bSArnaldo Carvalho de Melo 808c1737f2bSArnaldo Carvalho de Melo /** 809c1737f2bSArnaldo Carvalho de Melo * Returned value of the updated offset of the object, for future 810c1737f2bSArnaldo Carvalho de Melo * presumed_offset writes. 811c1737f2bSArnaldo Carvalho de Melo */ 812c1737f2bSArnaldo Carvalho de Melo __u64 offset; 813c1737f2bSArnaldo Carvalho de Melo }; 814c1737f2bSArnaldo Carvalho de Melo 815c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer { 816c1737f2bSArnaldo Carvalho de Melo /** 817c1737f2bSArnaldo Carvalho de Melo * List of buffers to be validated with their relocations to be 818c1737f2bSArnaldo Carvalho de Melo * performend on them. 819c1737f2bSArnaldo Carvalho de Melo * 820c1737f2bSArnaldo Carvalho de Melo * This is a pointer to an array of struct drm_i915_gem_validate_entry. 821c1737f2bSArnaldo Carvalho de Melo * 822c1737f2bSArnaldo Carvalho de Melo * These buffers must be listed in an order such that all relocations 823c1737f2bSArnaldo Carvalho de Melo * a buffer is performing refer to buffers that have already appeared 824c1737f2bSArnaldo Carvalho de Melo * in the validate list. 825c1737f2bSArnaldo Carvalho de Melo */ 826c1737f2bSArnaldo Carvalho de Melo __u64 buffers_ptr; 827c1737f2bSArnaldo Carvalho de Melo __u32 buffer_count; 828c1737f2bSArnaldo Carvalho de Melo 829c1737f2bSArnaldo Carvalho de Melo /** Offset in the batchbuffer to start execution from. */ 830c1737f2bSArnaldo Carvalho de Melo __u32 batch_start_offset; 831c1737f2bSArnaldo Carvalho de Melo /** Bytes used in batchbuffer from batch_start_offset */ 832c1737f2bSArnaldo Carvalho de Melo __u32 batch_len; 833c1737f2bSArnaldo Carvalho de Melo __u32 DR1; 834c1737f2bSArnaldo Carvalho de Melo __u32 DR4; 835c1737f2bSArnaldo Carvalho de Melo __u32 num_cliprects; 836c1737f2bSArnaldo Carvalho de Melo /** This is a struct drm_clip_rect *cliprects */ 837c1737f2bSArnaldo Carvalho de Melo __u64 cliprects_ptr; 838c1737f2bSArnaldo Carvalho de Melo }; 839c1737f2bSArnaldo Carvalho de Melo 840c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_exec_object2 { 841c1737f2bSArnaldo Carvalho de Melo /** 842c1737f2bSArnaldo Carvalho de Melo * User's handle for a buffer to be bound into the GTT for this 843c1737f2bSArnaldo Carvalho de Melo * operation. 844c1737f2bSArnaldo Carvalho de Melo */ 845c1737f2bSArnaldo Carvalho de Melo __u32 handle; 846c1737f2bSArnaldo Carvalho de Melo 847c1737f2bSArnaldo Carvalho de Melo /** Number of relocations to be performed on this buffer */ 848c1737f2bSArnaldo Carvalho de Melo __u32 relocation_count; 849c1737f2bSArnaldo Carvalho de Melo /** 850c1737f2bSArnaldo Carvalho de Melo * Pointer to array of struct drm_i915_gem_relocation_entry containing 851c1737f2bSArnaldo Carvalho de Melo * the relocations to be performed in this buffer. 852c1737f2bSArnaldo Carvalho de Melo */ 853c1737f2bSArnaldo Carvalho de Melo __u64 relocs_ptr; 854c1737f2bSArnaldo Carvalho de Melo 855c1737f2bSArnaldo Carvalho de Melo /** Required alignment in graphics aperture */ 856c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 857c1737f2bSArnaldo Carvalho de Melo 858c1737f2bSArnaldo Carvalho de Melo /** 859c1737f2bSArnaldo Carvalho de Melo * When the EXEC_OBJECT_PINNED flag is specified this is populated by 860c1737f2bSArnaldo Carvalho de Melo * the user with the GTT offset at which this object will be pinned. 861c1737f2bSArnaldo Carvalho de Melo * When the I915_EXEC_NO_RELOC flag is specified this must contain the 862c1737f2bSArnaldo Carvalho de Melo * presumed_offset of the object. 863c1737f2bSArnaldo Carvalho de Melo * During execbuffer2 the kernel populates it with the value of the 864c1737f2bSArnaldo Carvalho de Melo * current GTT offset of the object, for future presumed_offset writes. 865c1737f2bSArnaldo Carvalho de Melo */ 866c1737f2bSArnaldo Carvalho de Melo __u64 offset; 867c1737f2bSArnaldo Carvalho de Melo 868c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 869c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_NEEDS_GTT (1<<1) 870c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_WRITE (1<<2) 871c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 872c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_PINNED (1<<4) 873c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 874c1737f2bSArnaldo Carvalho de Melo /* The kernel implicitly tracks GPU activity on all GEM objects, and 875c1737f2bSArnaldo Carvalho de Melo * synchronises operations with outstanding rendering. This includes 876c1737f2bSArnaldo Carvalho de Melo * rendering on other devices if exported via dma-buf. However, sometimes 877c1737f2bSArnaldo Carvalho de Melo * this tracking is too coarse and the user knows better. For example, 878c1737f2bSArnaldo Carvalho de Melo * if the object is split into non-overlapping ranges shared between different 879c1737f2bSArnaldo Carvalho de Melo * clients or engines (i.e. suballocating objects), the implicit tracking 880c1737f2bSArnaldo Carvalho de Melo * by kernel assumes that each operation affects the whole object rather 881c1737f2bSArnaldo Carvalho de Melo * than an individual range, causing needless synchronisation between clients. 882c1737f2bSArnaldo Carvalho de Melo * The kernel will also forgo any CPU cache flushes prior to rendering from 883c1737f2bSArnaldo Carvalho de Melo * the object as the client is expected to be also handling such domain 884c1737f2bSArnaldo Carvalho de Melo * tracking. 885c1737f2bSArnaldo Carvalho de Melo * 886c1737f2bSArnaldo Carvalho de Melo * The kernel maintains the implicit tracking in order to manage resources 887c1737f2bSArnaldo Carvalho de Melo * used by the GPU - this flag only disables the synchronisation prior to 888c1737f2bSArnaldo Carvalho de Melo * rendering with this object in this execbuf. 889c1737f2bSArnaldo Carvalho de Melo * 890c1737f2bSArnaldo Carvalho de Melo * Opting out of implicit synhronisation requires the user to do its own 891c1737f2bSArnaldo Carvalho de Melo * explicit tracking to avoid rendering corruption. See, for example, 892c1737f2bSArnaldo Carvalho de Melo * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 893c1737f2bSArnaldo Carvalho de Melo */ 894c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_ASYNC (1<<6) 895c1737f2bSArnaldo Carvalho de Melo /* Request that the contents of this execobject be copied into the error 896c1737f2bSArnaldo Carvalho de Melo * state upon a GPU hang involving this batch for post-mortem debugging. 897c1737f2bSArnaldo Carvalho de Melo * These buffers are recorded in no particular order as "user" in 898c1737f2bSArnaldo Carvalho de Melo * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 899c1737f2bSArnaldo Carvalho de Melo * if the kernel supports this flag. 900c1737f2bSArnaldo Carvalho de Melo */ 901c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_CAPTURE (1<<7) 902c1737f2bSArnaldo Carvalho de Melo /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 903c1737f2bSArnaldo Carvalho de Melo #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 904c1737f2bSArnaldo Carvalho de Melo __u64 flags; 905c1737f2bSArnaldo Carvalho de Melo 906c1737f2bSArnaldo Carvalho de Melo union { 907c1737f2bSArnaldo Carvalho de Melo __u64 rsvd1; 908c1737f2bSArnaldo Carvalho de Melo __u64 pad_to_size; 909c1737f2bSArnaldo Carvalho de Melo }; 910c1737f2bSArnaldo Carvalho de Melo __u64 rsvd2; 911c1737f2bSArnaldo Carvalho de Melo }; 912c1737f2bSArnaldo Carvalho de Melo 913549a3976SIngo Molnar struct drm_i915_gem_exec_fence { 914549a3976SIngo Molnar /** 915549a3976SIngo Molnar * User's handle for a drm_syncobj to wait on or signal. 916549a3976SIngo Molnar */ 917549a3976SIngo Molnar __u32 handle; 918549a3976SIngo Molnar 919549a3976SIngo Molnar #define I915_EXEC_FENCE_WAIT (1<<0) 920549a3976SIngo Molnar #define I915_EXEC_FENCE_SIGNAL (1<<1) 921505ee767SIngo Molnar #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 922549a3976SIngo Molnar __u32 flags; 923549a3976SIngo Molnar }; 924549a3976SIngo Molnar 925c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer2 { 926c1737f2bSArnaldo Carvalho de Melo /** 927c1737f2bSArnaldo Carvalho de Melo * List of gem_exec_object2 structs 928c1737f2bSArnaldo Carvalho de Melo */ 929c1737f2bSArnaldo Carvalho de Melo __u64 buffers_ptr; 930c1737f2bSArnaldo Carvalho de Melo __u32 buffer_count; 931c1737f2bSArnaldo Carvalho de Melo 932c1737f2bSArnaldo Carvalho de Melo /** Offset in the batchbuffer to start execution from. */ 933c1737f2bSArnaldo Carvalho de Melo __u32 batch_start_offset; 934c1737f2bSArnaldo Carvalho de Melo /** Bytes used in batchbuffer from batch_start_offset */ 935c1737f2bSArnaldo Carvalho de Melo __u32 batch_len; 936c1737f2bSArnaldo Carvalho de Melo __u32 DR1; 937c1737f2bSArnaldo Carvalho de Melo __u32 DR4; 938c1737f2bSArnaldo Carvalho de Melo __u32 num_cliprects; 939549a3976SIngo Molnar /** 940549a3976SIngo Molnar * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY 941549a3976SIngo Molnar * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a 942549a3976SIngo Molnar * struct drm_i915_gem_exec_fence *fences. 943549a3976SIngo Molnar */ 944c1737f2bSArnaldo Carvalho de Melo __u64 cliprects_ptr; 945c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RING_MASK (7<<0) 946c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_DEFAULT (0<<0) 947c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RENDER (1<<0) 948c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD (2<<0) 949c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BLT (3<<0) 950c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_VEBOX (4<<0) 951c1737f2bSArnaldo Carvalho de Melo 952c1737f2bSArnaldo Carvalho de Melo /* Used for switching the constants addressing mode on gen4+ RENDER ring. 953c1737f2bSArnaldo Carvalho de Melo * Gen6+ only supports relative addressing to dynamic state (default) and 954c1737f2bSArnaldo Carvalho de Melo * absolute addressing. 955c1737f2bSArnaldo Carvalho de Melo * 956c1737f2bSArnaldo Carvalho de Melo * These flags are ignored for the BSD and BLT rings. 957c1737f2bSArnaldo Carvalho de Melo */ 958c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_MASK (3<<6) 959c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 960c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 961c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 962c1737f2bSArnaldo Carvalho de Melo __u64 flags; 963c1737f2bSArnaldo Carvalho de Melo __u64 rsvd1; /* now used for context info */ 964c1737f2bSArnaldo Carvalho de Melo __u64 rsvd2; 965c1737f2bSArnaldo Carvalho de Melo }; 966c1737f2bSArnaldo Carvalho de Melo 967c1737f2bSArnaldo Carvalho de Melo /** Resets the SO write offset registers for transform feedback on gen7. */ 968c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_GEN7_SOL_RESET (1<<8) 969c1737f2bSArnaldo Carvalho de Melo 970c1737f2bSArnaldo Carvalho de Melo /** Request a privileged ("secure") batch buffer. Note only available for 971c1737f2bSArnaldo Carvalho de Melo * DRM_ROOT_ONLY | DRM_MASTER processes. 972c1737f2bSArnaldo Carvalho de Melo */ 973c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_SECURE (1<<9) 974c1737f2bSArnaldo Carvalho de Melo 975c1737f2bSArnaldo Carvalho de Melo /** Inform the kernel that the batch is and will always be pinned. This 976c1737f2bSArnaldo Carvalho de Melo * negates the requirement for a workaround to be performed to avoid 977c1737f2bSArnaldo Carvalho de Melo * an incoherent CS (such as can be found on 830/845). If this flag is 978c1737f2bSArnaldo Carvalho de Melo * not passed, the kernel will endeavour to make sure the batch is 979c1737f2bSArnaldo Carvalho de Melo * coherent with the CS before execution. If this flag is passed, 980c1737f2bSArnaldo Carvalho de Melo * userspace assumes the responsibility for ensuring the same. 981c1737f2bSArnaldo Carvalho de Melo */ 982c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_IS_PINNED (1<<10) 983c1737f2bSArnaldo Carvalho de Melo 984c1737f2bSArnaldo Carvalho de Melo /** Provide a hint to the kernel that the command stream and auxiliary 985c1737f2bSArnaldo Carvalho de Melo * state buffers already holds the correct presumed addresses and so the 986c1737f2bSArnaldo Carvalho de Melo * relocation process may be skipped if no buffers need to be moved in 987c1737f2bSArnaldo Carvalho de Melo * preparation for the execbuffer. 988c1737f2bSArnaldo Carvalho de Melo */ 989c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_NO_RELOC (1<<11) 990c1737f2bSArnaldo Carvalho de Melo 991c1737f2bSArnaldo Carvalho de Melo /** Use the reloc.handle as an index into the exec object array rather 992c1737f2bSArnaldo Carvalho de Melo * than as the per-file handle. 993c1737f2bSArnaldo Carvalho de Melo */ 994c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_HANDLE_LUT (1<<12) 995c1737f2bSArnaldo Carvalho de Melo 996c1737f2bSArnaldo Carvalho de Melo /** Used for switching BSD rings on the platforms with two BSD rings */ 997c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_SHIFT (13) 998c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 999c1737f2bSArnaldo Carvalho de Melo /* default ping-pong mode */ 1000c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1001c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1002c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 1003c1737f2bSArnaldo Carvalho de Melo 1004c1737f2bSArnaldo Carvalho de Melo /** Tell the kernel that the batchbuffer is processed by 1005c1737f2bSArnaldo Carvalho de Melo * the resource streamer. 1006c1737f2bSArnaldo Carvalho de Melo */ 1007c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1008c1737f2bSArnaldo Carvalho de Melo 1009c1737f2bSArnaldo Carvalho de Melo /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1010c1737f2bSArnaldo Carvalho de Melo * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1011c1737f2bSArnaldo Carvalho de Melo * the batch. 1012c1737f2bSArnaldo Carvalho de Melo * 1013c1737f2bSArnaldo Carvalho de Melo * Returns -EINVAL if the sync_file fd cannot be found. 1014c1737f2bSArnaldo Carvalho de Melo */ 1015c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_IN (1<<16) 1016c1737f2bSArnaldo Carvalho de Melo 1017c1737f2bSArnaldo Carvalho de Melo /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1018c1737f2bSArnaldo Carvalho de Melo * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1019c1737f2bSArnaldo Carvalho de Melo * to the caller, and it should be close() after use. (The fd is a regular 1020c1737f2bSArnaldo Carvalho de Melo * file descriptor and will be cleaned up on process termination. It holds 1021c1737f2bSArnaldo Carvalho de Melo * a reference to the request, but nothing else.) 1022c1737f2bSArnaldo Carvalho de Melo * 1023c1737f2bSArnaldo Carvalho de Melo * The sync_file fd can be combined with other sync_file and passed either 1024c1737f2bSArnaldo Carvalho de Melo * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1025c1737f2bSArnaldo Carvalho de Melo * will only occur after this request completes), or to other devices. 1026c1737f2bSArnaldo Carvalho de Melo * 1027c1737f2bSArnaldo Carvalho de Melo * Using I915_EXEC_FENCE_OUT requires use of 1028c1737f2bSArnaldo Carvalho de Melo * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1029c1737f2bSArnaldo Carvalho de Melo * back to userspace. Failure to do so will cause the out-fence to always 1030c1737f2bSArnaldo Carvalho de Melo * be reported as zero, and the real fence fd to be leaked. 1031c1737f2bSArnaldo Carvalho de Melo */ 1032c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_OUT (1<<17) 1033c1737f2bSArnaldo Carvalho de Melo 1034c1737f2bSArnaldo Carvalho de Melo /* 1035c1737f2bSArnaldo Carvalho de Melo * Traditionally the execbuf ioctl has only considered the final element in 1036c1737f2bSArnaldo Carvalho de Melo * the execobject[] to be the executable batch. Often though, the client 1037c1737f2bSArnaldo Carvalho de Melo * will known the batch object prior to construction and being able to place 1038c1737f2bSArnaldo Carvalho de Melo * it into the execobject[] array first can simplify the relocation tracking. 1039c1737f2bSArnaldo Carvalho de Melo * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 1040c1737f2bSArnaldo Carvalho de Melo * execobject[] as the * batch instead (the default is to use the last 1041c1737f2bSArnaldo Carvalho de Melo * element). 1042c1737f2bSArnaldo Carvalho de Melo */ 1043c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BATCH_FIRST (1<<18) 1044549a3976SIngo Molnar 1045549a3976SIngo Molnar /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1046549a3976SIngo Molnar * define an array of i915_gem_exec_fence structures which specify a set of 1047549a3976SIngo Molnar * dma fences to wait upon or signal. 1048549a3976SIngo Molnar */ 1049549a3976SIngo Molnar #define I915_EXEC_FENCE_ARRAY (1<<19) 1050549a3976SIngo Molnar 1051549a3976SIngo Molnar #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) 1052c1737f2bSArnaldo Carvalho de Melo 1053c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1054c1737f2bSArnaldo Carvalho de Melo #define i915_execbuffer2_set_context_id(eb2, context) \ 1055c1737f2bSArnaldo Carvalho de Melo (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1056c1737f2bSArnaldo Carvalho de Melo #define i915_execbuffer2_get_context_id(eb2) \ 1057c1737f2bSArnaldo Carvalho de Melo ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1058c1737f2bSArnaldo Carvalho de Melo 1059c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pin { 1060c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to be pinned. */ 1061c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1062c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1063c1737f2bSArnaldo Carvalho de Melo 1064c1737f2bSArnaldo Carvalho de Melo /** alignment required within the aperture */ 1065c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1066c1737f2bSArnaldo Carvalho de Melo 1067c1737f2bSArnaldo Carvalho de Melo /** Returned GTT offset of the buffer. */ 1068c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1069c1737f2bSArnaldo Carvalho de Melo }; 1070c1737f2bSArnaldo Carvalho de Melo 1071c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_unpin { 1072c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to be unpinned. */ 1073c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1074c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1075c1737f2bSArnaldo Carvalho de Melo }; 1076c1737f2bSArnaldo Carvalho de Melo 1077c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_busy { 1078c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to check for busy */ 1079c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1080c1737f2bSArnaldo Carvalho de Melo 1081c1737f2bSArnaldo Carvalho de Melo /** Return busy status 1082c1737f2bSArnaldo Carvalho de Melo * 1083c1737f2bSArnaldo Carvalho de Melo * A return of 0 implies that the object is idle (after 1084c1737f2bSArnaldo Carvalho de Melo * having flushed any pending activity), and a non-zero return that 1085c1737f2bSArnaldo Carvalho de Melo * the object is still in-flight on the GPU. (The GPU has not yet 1086c1737f2bSArnaldo Carvalho de Melo * signaled completion for all pending requests that reference the 1087c1737f2bSArnaldo Carvalho de Melo * object.) An object is guaranteed to become idle eventually (so 1088c1737f2bSArnaldo Carvalho de Melo * long as no new GPU commands are executed upon it). Due to the 1089c1737f2bSArnaldo Carvalho de Melo * asynchronous nature of the hardware, an object reported 1090c1737f2bSArnaldo Carvalho de Melo * as busy may become idle before the ioctl is completed. 1091c1737f2bSArnaldo Carvalho de Melo * 1092c1737f2bSArnaldo Carvalho de Melo * Furthermore, if the object is busy, which engine is busy is only 1093c1737f2bSArnaldo Carvalho de Melo * provided as a guide. There are race conditions which prevent the 1094c1737f2bSArnaldo Carvalho de Melo * report of which engines are busy from being always accurate. 1095c1737f2bSArnaldo Carvalho de Melo * However, the converse is not true. If the object is idle, the 1096c1737f2bSArnaldo Carvalho de Melo * result of the ioctl, that all engines are idle, is accurate. 1097c1737f2bSArnaldo Carvalho de Melo * 1098c1737f2bSArnaldo Carvalho de Melo * The returned dword is split into two fields to indicate both 1099c1737f2bSArnaldo Carvalho de Melo * the engines on which the object is being read, and the 1100c1737f2bSArnaldo Carvalho de Melo * engine on which it is currently being written (if any). 1101c1737f2bSArnaldo Carvalho de Melo * 1102c1737f2bSArnaldo Carvalho de Melo * The low word (bits 0:15) indicate if the object is being written 1103c1737f2bSArnaldo Carvalho de Melo * to by any engine (there can only be one, as the GEM implicit 1104c1737f2bSArnaldo Carvalho de Melo * synchronisation rules force writes to be serialised). Only the 1105c1737f2bSArnaldo Carvalho de Melo * engine for the last write is reported. 1106c1737f2bSArnaldo Carvalho de Melo * 1107c1737f2bSArnaldo Carvalho de Melo * The high word (bits 16:31) are a bitmask of which engines are 1108c1737f2bSArnaldo Carvalho de Melo * currently reading from the object. Multiple engines may be 1109c1737f2bSArnaldo Carvalho de Melo * reading from the object simultaneously. 1110c1737f2bSArnaldo Carvalho de Melo * 1111c1737f2bSArnaldo Carvalho de Melo * The value of each engine is the same as specified in the 1112c1737f2bSArnaldo Carvalho de Melo * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. 1113c1737f2bSArnaldo Carvalho de Melo * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to 1114c1737f2bSArnaldo Carvalho de Melo * the I915_EXEC_RENDER engine for execution, and so it is never 1115c1737f2bSArnaldo Carvalho de Melo * reported as active itself. Some hardware may have parallel 1116c1737f2bSArnaldo Carvalho de Melo * execution engines, e.g. multiple media engines, which are 1117c1737f2bSArnaldo Carvalho de Melo * mapped to the same identifier in the EXECBUFFER2 ioctl and 1118c1737f2bSArnaldo Carvalho de Melo * so are not separately reported for busyness. 1119c1737f2bSArnaldo Carvalho de Melo * 1120c1737f2bSArnaldo Carvalho de Melo * Caveat emptor: 1121c1737f2bSArnaldo Carvalho de Melo * Only the boolean result of this query is reliable; that is whether 1122c1737f2bSArnaldo Carvalho de Melo * the object is idle or busy. The report of which engines are busy 1123c1737f2bSArnaldo Carvalho de Melo * should be only used as a heuristic. 1124c1737f2bSArnaldo Carvalho de Melo */ 1125c1737f2bSArnaldo Carvalho de Melo __u32 busy; 1126c1737f2bSArnaldo Carvalho de Melo }; 1127c1737f2bSArnaldo Carvalho de Melo 1128c1737f2bSArnaldo Carvalho de Melo /** 1129c1737f2bSArnaldo Carvalho de Melo * I915_CACHING_NONE 1130c1737f2bSArnaldo Carvalho de Melo * 1131c1737f2bSArnaldo Carvalho de Melo * GPU access is not coherent with cpu caches. Default for machines without an 1132c1737f2bSArnaldo Carvalho de Melo * LLC. 1133c1737f2bSArnaldo Carvalho de Melo */ 1134c1737f2bSArnaldo Carvalho de Melo #define I915_CACHING_NONE 0 1135c1737f2bSArnaldo Carvalho de Melo /** 1136c1737f2bSArnaldo Carvalho de Melo * I915_CACHING_CACHED 1137c1737f2bSArnaldo Carvalho de Melo * 1138c1737f2bSArnaldo Carvalho de Melo * GPU access is coherent with cpu caches and furthermore the data is cached in 1139c1737f2bSArnaldo Carvalho de Melo * last-level caches shared between cpu cores and the gpu GT. Default on 1140c1737f2bSArnaldo Carvalho de Melo * machines with HAS_LLC. 1141c1737f2bSArnaldo Carvalho de Melo */ 1142c1737f2bSArnaldo Carvalho de Melo #define I915_CACHING_CACHED 1 1143c1737f2bSArnaldo Carvalho de Melo /** 1144c1737f2bSArnaldo Carvalho de Melo * I915_CACHING_DISPLAY 1145c1737f2bSArnaldo Carvalho de Melo * 1146c1737f2bSArnaldo Carvalho de Melo * Special GPU caching mode which is coherent with the scanout engines. 1147c1737f2bSArnaldo Carvalho de Melo * Transparently falls back to I915_CACHING_NONE on platforms where no special 1148c1737f2bSArnaldo Carvalho de Melo * cache mode (like write-through or gfdt flushing) is available. The kernel 1149c1737f2bSArnaldo Carvalho de Melo * automatically sets this mode when using a buffer as a scanout target. 1150c1737f2bSArnaldo Carvalho de Melo * Userspace can manually set this mode to avoid a costly stall and clflush in 1151c1737f2bSArnaldo Carvalho de Melo * the hotpath of drawing the first frame. 1152c1737f2bSArnaldo Carvalho de Melo */ 1153c1737f2bSArnaldo Carvalho de Melo #define I915_CACHING_DISPLAY 2 1154c1737f2bSArnaldo Carvalho de Melo 1155c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_caching { 1156c1737f2bSArnaldo Carvalho de Melo /** 1157c1737f2bSArnaldo Carvalho de Melo * Handle of the buffer to set/get the caching level of. */ 1158c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1159c1737f2bSArnaldo Carvalho de Melo 1160c1737f2bSArnaldo Carvalho de Melo /** 1161c1737f2bSArnaldo Carvalho de Melo * Cacheing level to apply or return value 1162c1737f2bSArnaldo Carvalho de Melo * 1163c1737f2bSArnaldo Carvalho de Melo * bits0-15 are for generic caching control (i.e. the above defined 1164c1737f2bSArnaldo Carvalho de Melo * values). bits16-31 are reserved for platform-specific variations 1165c1737f2bSArnaldo Carvalho de Melo * (e.g. l3$ caching on gen7). */ 1166c1737f2bSArnaldo Carvalho de Melo __u32 caching; 1167c1737f2bSArnaldo Carvalho de Melo }; 1168c1737f2bSArnaldo Carvalho de Melo 1169c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_NONE 0 1170c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_X 1 1171c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_Y 2 1172c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_LAST I915_TILING_Y 1173c1737f2bSArnaldo Carvalho de Melo 1174c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_NONE 0 1175c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9 1 1176c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10 2 1177c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_11 3 1178c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10_11 4 1179c1737f2bSArnaldo Carvalho de Melo /* Not seen by userland */ 1180c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1181c1737f2bSArnaldo Carvalho de Melo /* Seen by userland. */ 1182c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_17 6 1183c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10_17 7 1184c1737f2bSArnaldo Carvalho de Melo 1185c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_set_tiling { 1186c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to have its tiling state updated */ 1187c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1188c1737f2bSArnaldo Carvalho de Melo 1189c1737f2bSArnaldo Carvalho de Melo /** 1190c1737f2bSArnaldo Carvalho de Melo * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1191c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y). 1192c1737f2bSArnaldo Carvalho de Melo * 1193c1737f2bSArnaldo Carvalho de Melo * This value is to be set on request, and will be updated by the 1194c1737f2bSArnaldo Carvalho de Melo * kernel on successful return with the actual chosen tiling layout. 1195c1737f2bSArnaldo Carvalho de Melo * 1196c1737f2bSArnaldo Carvalho de Melo * The tiling mode may be demoted to I915_TILING_NONE when the system 1197c1737f2bSArnaldo Carvalho de Melo * has bit 6 swizzling that can't be managed correctly by GEM. 1198c1737f2bSArnaldo Carvalho de Melo * 1199c1737f2bSArnaldo Carvalho de Melo * Buffer contents become undefined when changing tiling_mode. 1200c1737f2bSArnaldo Carvalho de Melo */ 1201c1737f2bSArnaldo Carvalho de Melo __u32 tiling_mode; 1202c1737f2bSArnaldo Carvalho de Melo 1203c1737f2bSArnaldo Carvalho de Melo /** 1204c1737f2bSArnaldo Carvalho de Melo * Stride in bytes for the object when in I915_TILING_X or 1205c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y. 1206c1737f2bSArnaldo Carvalho de Melo */ 1207c1737f2bSArnaldo Carvalho de Melo __u32 stride; 1208c1737f2bSArnaldo Carvalho de Melo 1209c1737f2bSArnaldo Carvalho de Melo /** 1210c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1211c1737f2bSArnaldo Carvalho de Melo * mmap mapping. 1212c1737f2bSArnaldo Carvalho de Melo */ 1213c1737f2bSArnaldo Carvalho de Melo __u32 swizzle_mode; 1214c1737f2bSArnaldo Carvalho de Melo }; 1215c1737f2bSArnaldo Carvalho de Melo 1216c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_get_tiling { 1217c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to get tiling state for. */ 1218c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1219c1737f2bSArnaldo Carvalho de Melo 1220c1737f2bSArnaldo Carvalho de Melo /** 1221c1737f2bSArnaldo Carvalho de Melo * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1222c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y). 1223c1737f2bSArnaldo Carvalho de Melo */ 1224c1737f2bSArnaldo Carvalho de Melo __u32 tiling_mode; 1225c1737f2bSArnaldo Carvalho de Melo 1226c1737f2bSArnaldo Carvalho de Melo /** 1227c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1228c1737f2bSArnaldo Carvalho de Melo * mmap mapping. 1229c1737f2bSArnaldo Carvalho de Melo */ 1230c1737f2bSArnaldo Carvalho de Melo __u32 swizzle_mode; 1231c1737f2bSArnaldo Carvalho de Melo 1232c1737f2bSArnaldo Carvalho de Melo /** 1233c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1234c1737f2bSArnaldo Carvalho de Melo * mmap mapping whilst bound. 1235c1737f2bSArnaldo Carvalho de Melo */ 1236c1737f2bSArnaldo Carvalho de Melo __u32 phys_swizzle_mode; 1237c1737f2bSArnaldo Carvalho de Melo }; 1238c1737f2bSArnaldo Carvalho de Melo 1239c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_get_aperture { 1240c1737f2bSArnaldo Carvalho de Melo /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1241c1737f2bSArnaldo Carvalho de Melo __u64 aper_size; 1242c1737f2bSArnaldo Carvalho de Melo 1243c1737f2bSArnaldo Carvalho de Melo /** 1244c1737f2bSArnaldo Carvalho de Melo * Available space in the aperture used by i915_gem_execbuffer, in 1245c1737f2bSArnaldo Carvalho de Melo * bytes 1246c1737f2bSArnaldo Carvalho de Melo */ 1247c1737f2bSArnaldo Carvalho de Melo __u64 aper_available_size; 1248c1737f2bSArnaldo Carvalho de Melo }; 1249c1737f2bSArnaldo Carvalho de Melo 1250c1737f2bSArnaldo Carvalho de Melo struct drm_i915_get_pipe_from_crtc_id { 1251c1737f2bSArnaldo Carvalho de Melo /** ID of CRTC being requested **/ 1252c1737f2bSArnaldo Carvalho de Melo __u32 crtc_id; 1253c1737f2bSArnaldo Carvalho de Melo 1254c1737f2bSArnaldo Carvalho de Melo /** pipe of requested CRTC **/ 1255c1737f2bSArnaldo Carvalho de Melo __u32 pipe; 1256c1737f2bSArnaldo Carvalho de Melo }; 1257c1737f2bSArnaldo Carvalho de Melo 1258c1737f2bSArnaldo Carvalho de Melo #define I915_MADV_WILLNEED 0 1259c1737f2bSArnaldo Carvalho de Melo #define I915_MADV_DONTNEED 1 1260c1737f2bSArnaldo Carvalho de Melo #define __I915_MADV_PURGED 2 /* internal state */ 1261c1737f2bSArnaldo Carvalho de Melo 1262c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_madvise { 1263c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to change the backing store advice */ 1264c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1265c1737f2bSArnaldo Carvalho de Melo 1266c1737f2bSArnaldo Carvalho de Melo /* Advice: either the buffer will be needed again in the near future, 1267c1737f2bSArnaldo Carvalho de Melo * or wont be and could be discarded under memory pressure. 1268c1737f2bSArnaldo Carvalho de Melo */ 1269c1737f2bSArnaldo Carvalho de Melo __u32 madv; 1270c1737f2bSArnaldo Carvalho de Melo 1271c1737f2bSArnaldo Carvalho de Melo /** Whether the backing store still exists. */ 1272c1737f2bSArnaldo Carvalho de Melo __u32 retained; 1273c1737f2bSArnaldo Carvalho de Melo }; 1274c1737f2bSArnaldo Carvalho de Melo 1275c1737f2bSArnaldo Carvalho de Melo /* flags */ 1276c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_TYPE_MASK 0xff 1277c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV_PLANAR 0x01 1278c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV_PACKED 0x02 1279c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB 0x03 1280c1737f2bSArnaldo Carvalho de Melo 1281c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_DEPTH_MASK 0xff00 1282c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB24 0x1000 1283c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB16 0x2000 1284c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB15 0x3000 1285c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV422 0x0100 1286c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV411 0x0200 1287c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV420 0x0300 1288c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV410 0x0400 1289c1737f2bSArnaldo Carvalho de Melo 1290c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_SWAP_MASK 0xff0000 1291c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_NO_SWAP 0x000000 1292c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UV_SWAP 0x010000 1293c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_Y_SWAP 0x020000 1294c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1295c1737f2bSArnaldo Carvalho de Melo 1296c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_FLAGS_MASK 0xff000000 1297c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_ENABLE 0x01000000 1298c1737f2bSArnaldo Carvalho de Melo 1299c1737f2bSArnaldo Carvalho de Melo struct drm_intel_overlay_put_image { 1300c1737f2bSArnaldo Carvalho de Melo /* various flags and src format description */ 1301c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1302c1737f2bSArnaldo Carvalho de Melo /* source picture description */ 1303c1737f2bSArnaldo Carvalho de Melo __u32 bo_handle; 1304c1737f2bSArnaldo Carvalho de Melo /* stride values and offsets are in bytes, buffer relative */ 1305c1737f2bSArnaldo Carvalho de Melo __u16 stride_Y; /* stride for packed formats */ 1306c1737f2bSArnaldo Carvalho de Melo __u16 stride_UV; 1307c1737f2bSArnaldo Carvalho de Melo __u32 offset_Y; /* offset for packet formats */ 1308c1737f2bSArnaldo Carvalho de Melo __u32 offset_U; 1309c1737f2bSArnaldo Carvalho de Melo __u32 offset_V; 1310c1737f2bSArnaldo Carvalho de Melo /* in pixels */ 1311c1737f2bSArnaldo Carvalho de Melo __u16 src_width; 1312c1737f2bSArnaldo Carvalho de Melo __u16 src_height; 1313c1737f2bSArnaldo Carvalho de Melo /* to compensate the scaling factors for partially covered surfaces */ 1314c1737f2bSArnaldo Carvalho de Melo __u16 src_scan_width; 1315c1737f2bSArnaldo Carvalho de Melo __u16 src_scan_height; 1316c1737f2bSArnaldo Carvalho de Melo /* output crtc description */ 1317c1737f2bSArnaldo Carvalho de Melo __u32 crtc_id; 1318c1737f2bSArnaldo Carvalho de Melo __u16 dst_x; 1319c1737f2bSArnaldo Carvalho de Melo __u16 dst_y; 1320c1737f2bSArnaldo Carvalho de Melo __u16 dst_width; 1321c1737f2bSArnaldo Carvalho de Melo __u16 dst_height; 1322c1737f2bSArnaldo Carvalho de Melo }; 1323c1737f2bSArnaldo Carvalho de Melo 1324c1737f2bSArnaldo Carvalho de Melo /* flags */ 1325c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1326c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1327c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1328c1737f2bSArnaldo Carvalho de Melo struct drm_intel_overlay_attrs { 1329c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1330c1737f2bSArnaldo Carvalho de Melo __u32 color_key; 1331c1737f2bSArnaldo Carvalho de Melo __s32 brightness; 1332c1737f2bSArnaldo Carvalho de Melo __u32 contrast; 1333c1737f2bSArnaldo Carvalho de Melo __u32 saturation; 1334c1737f2bSArnaldo Carvalho de Melo __u32 gamma0; 1335c1737f2bSArnaldo Carvalho de Melo __u32 gamma1; 1336c1737f2bSArnaldo Carvalho de Melo __u32 gamma2; 1337c1737f2bSArnaldo Carvalho de Melo __u32 gamma3; 1338c1737f2bSArnaldo Carvalho de Melo __u32 gamma4; 1339c1737f2bSArnaldo Carvalho de Melo __u32 gamma5; 1340c1737f2bSArnaldo Carvalho de Melo }; 1341c1737f2bSArnaldo Carvalho de Melo 1342c1737f2bSArnaldo Carvalho de Melo /* 1343c1737f2bSArnaldo Carvalho de Melo * Intel sprite handling 1344c1737f2bSArnaldo Carvalho de Melo * 1345c1737f2bSArnaldo Carvalho de Melo * Color keying works with a min/mask/max tuple. Both source and destination 1346c1737f2bSArnaldo Carvalho de Melo * color keying is allowed. 1347c1737f2bSArnaldo Carvalho de Melo * 1348c1737f2bSArnaldo Carvalho de Melo * Source keying: 1349c1737f2bSArnaldo Carvalho de Melo * Sprite pixels within the min & max values, masked against the color channels 1350c1737f2bSArnaldo Carvalho de Melo * specified in the mask field, will be transparent. All other pixels will 1351c1737f2bSArnaldo Carvalho de Melo * be displayed on top of the primary plane. For RGB surfaces, only the min 1352c1737f2bSArnaldo Carvalho de Melo * and mask fields will be used; ranged compares are not allowed. 1353c1737f2bSArnaldo Carvalho de Melo * 1354c1737f2bSArnaldo Carvalho de Melo * Destination keying: 1355c1737f2bSArnaldo Carvalho de Melo * Primary plane pixels that match the min value, masked against the color 1356c1737f2bSArnaldo Carvalho de Melo * channels specified in the mask field, will be replaced by corresponding 1357c1737f2bSArnaldo Carvalho de Melo * pixels from the sprite plane. 1358c1737f2bSArnaldo Carvalho de Melo * 1359c1737f2bSArnaldo Carvalho de Melo * Note that source & destination keying are exclusive; only one can be 1360c1737f2bSArnaldo Carvalho de Melo * active on a given plane. 1361c1737f2bSArnaldo Carvalho de Melo */ 1362c1737f2bSArnaldo Carvalho de Melo 136301f97511SArnaldo Carvalho de Melo #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 136401f97511SArnaldo Carvalho de Melo * flags==0 to disable colorkeying. 136501f97511SArnaldo Carvalho de Melo */ 1366c1737f2bSArnaldo Carvalho de Melo #define I915_SET_COLORKEY_DESTINATION (1<<1) 1367c1737f2bSArnaldo Carvalho de Melo #define I915_SET_COLORKEY_SOURCE (1<<2) 1368c1737f2bSArnaldo Carvalho de Melo struct drm_intel_sprite_colorkey { 1369c1737f2bSArnaldo Carvalho de Melo __u32 plane_id; 1370c1737f2bSArnaldo Carvalho de Melo __u32 min_value; 1371c1737f2bSArnaldo Carvalho de Melo __u32 channel_mask; 1372c1737f2bSArnaldo Carvalho de Melo __u32 max_value; 1373c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1374c1737f2bSArnaldo Carvalho de Melo }; 1375c1737f2bSArnaldo Carvalho de Melo 1376c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_wait { 1377c1737f2bSArnaldo Carvalho de Melo /** Handle of BO we shall wait on */ 1378c1737f2bSArnaldo Carvalho de Melo __u32 bo_handle; 1379c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1380c1737f2bSArnaldo Carvalho de Melo /** Number of nanoseconds to wait, Returns time remaining. */ 1381c1737f2bSArnaldo Carvalho de Melo __s64 timeout_ns; 1382c1737f2bSArnaldo Carvalho de Melo }; 1383c1737f2bSArnaldo Carvalho de Melo 1384c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_create { 1385c1737f2bSArnaldo Carvalho de Melo /* output: id of new context*/ 1386c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 1387c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1388c1737f2bSArnaldo Carvalho de Melo }; 1389c1737f2bSArnaldo Carvalho de Melo 1390c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_destroy { 1391c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 1392c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1393c1737f2bSArnaldo Carvalho de Melo }; 1394c1737f2bSArnaldo Carvalho de Melo 1395c1737f2bSArnaldo Carvalho de Melo struct drm_i915_reg_read { 1396c1737f2bSArnaldo Carvalho de Melo /* 1397c1737f2bSArnaldo Carvalho de Melo * Register offset. 1398c1737f2bSArnaldo Carvalho de Melo * For 64bit wide registers where the upper 32bits don't immediately 1399c1737f2bSArnaldo Carvalho de Melo * follow the lower 32bits, the offset of the lower 32bits must 1400c1737f2bSArnaldo Carvalho de Melo * be specified 1401c1737f2bSArnaldo Carvalho de Melo */ 1402c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1403485be0cbSArnaldo Carvalho de Melo #define I915_REG_READ_8B_WA (1ul << 0) 1404485be0cbSArnaldo Carvalho de Melo 1405c1737f2bSArnaldo Carvalho de Melo __u64 val; /* Return value */ 1406c1737f2bSArnaldo Carvalho de Melo }; 1407c1737f2bSArnaldo Carvalho de Melo /* Known registers: 1408c1737f2bSArnaldo Carvalho de Melo * 1409c1737f2bSArnaldo Carvalho de Melo * Render engine timestamp - 0x2358 + 64bit - gen7+ 1410c1737f2bSArnaldo Carvalho de Melo * - Note this register returns an invalid value if using the default 1411485be0cbSArnaldo Carvalho de Melo * single instruction 8byte read, in order to workaround that pass 1412485be0cbSArnaldo Carvalho de Melo * flag I915_REG_READ_8B_WA in offset field. 1413c1737f2bSArnaldo Carvalho de Melo * 1414c1737f2bSArnaldo Carvalho de Melo */ 1415c1737f2bSArnaldo Carvalho de Melo 1416c1737f2bSArnaldo Carvalho de Melo struct drm_i915_reset_stats { 1417c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 1418c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1419c1737f2bSArnaldo Carvalho de Melo 1420c1737f2bSArnaldo Carvalho de Melo /* All resets since boot/module reload, for all contexts */ 1421c1737f2bSArnaldo Carvalho de Melo __u32 reset_count; 1422c1737f2bSArnaldo Carvalho de Melo 1423c1737f2bSArnaldo Carvalho de Melo /* Number of batches lost when active in GPU, for this context */ 1424c1737f2bSArnaldo Carvalho de Melo __u32 batch_active; 1425c1737f2bSArnaldo Carvalho de Melo 1426c1737f2bSArnaldo Carvalho de Melo /* Number of batches lost pending for execution, for this context */ 1427c1737f2bSArnaldo Carvalho de Melo __u32 batch_pending; 1428c1737f2bSArnaldo Carvalho de Melo 1429c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1430c1737f2bSArnaldo Carvalho de Melo }; 1431c1737f2bSArnaldo Carvalho de Melo 1432c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_userptr { 1433c1737f2bSArnaldo Carvalho de Melo __u64 user_ptr; 1434c1737f2bSArnaldo Carvalho de Melo __u64 user_size; 1435c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1436c1737f2bSArnaldo Carvalho de Melo #define I915_USERPTR_READ_ONLY 0x1 1437c1737f2bSArnaldo Carvalho de Melo #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1438c1737f2bSArnaldo Carvalho de Melo /** 1439c1737f2bSArnaldo Carvalho de Melo * Returned handle for the object. 1440c1737f2bSArnaldo Carvalho de Melo * 1441c1737f2bSArnaldo Carvalho de Melo * Object handles are nonzero. 1442c1737f2bSArnaldo Carvalho de Melo */ 1443c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1444c1737f2bSArnaldo Carvalho de Melo }; 1445c1737f2bSArnaldo Carvalho de Melo 1446c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_param { 1447c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 1448c1737f2bSArnaldo Carvalho de Melo __u32 size; 1449c1737f2bSArnaldo Carvalho de Melo __u64 param; 1450c1737f2bSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1451c1737f2bSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1452c1737f2bSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1453c1737f2bSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 1454c1737f2bSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_BANNABLE 0x5 1455485be0cbSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_PRIORITY 0x6 1456485be0cbSArnaldo Carvalho de Melo #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 1457485be0cbSArnaldo Carvalho de Melo #define I915_CONTEXT_DEFAULT_PRIORITY 0 1458485be0cbSArnaldo Carvalho de Melo #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 1459c1737f2bSArnaldo Carvalho de Melo __u64 value; 1460c1737f2bSArnaldo Carvalho de Melo }; 1461c1737f2bSArnaldo Carvalho de Melo 1462c1737f2bSArnaldo Carvalho de Melo enum drm_i915_oa_format { 1463c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A13 = 1, /* HSW only */ 1464c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A29, /* HSW only */ 1465c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 1466c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_B4_C8, /* HSW only */ 1467c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 1468c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 1469c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_C4_B8, /* HSW+ */ 1470c1737f2bSArnaldo Carvalho de Melo 1471c1737f2bSArnaldo Carvalho de Melo /* Gen8+ */ 1472c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A12, 1473c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A12_B8_C8, 1474c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A32u40_A4u32_B8_C8, 1475c1737f2bSArnaldo Carvalho de Melo 1476c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_MAX /* non-ABI */ 1477c1737f2bSArnaldo Carvalho de Melo }; 1478c1737f2bSArnaldo Carvalho de Melo 1479c1737f2bSArnaldo Carvalho de Melo enum drm_i915_perf_property_id { 1480c1737f2bSArnaldo Carvalho de Melo /** 1481c1737f2bSArnaldo Carvalho de Melo * Open the stream for a specific context handle (as used with 1482c1737f2bSArnaldo Carvalho de Melo * execbuffer2). A stream opened for a specific context this way 1483c1737f2bSArnaldo Carvalho de Melo * won't typically require root privileges. 1484c1737f2bSArnaldo Carvalho de Melo */ 1485c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_CTX_HANDLE = 1, 1486c1737f2bSArnaldo Carvalho de Melo 1487c1737f2bSArnaldo Carvalho de Melo /** 1488c1737f2bSArnaldo Carvalho de Melo * A value of 1 requests the inclusion of raw OA unit reports as 1489c1737f2bSArnaldo Carvalho de Melo * part of stream samples. 1490c1737f2bSArnaldo Carvalho de Melo */ 1491c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_SAMPLE_OA, 1492c1737f2bSArnaldo Carvalho de Melo 1493c1737f2bSArnaldo Carvalho de Melo /** 1494c1737f2bSArnaldo Carvalho de Melo * The value specifies which set of OA unit metrics should be 1495c1737f2bSArnaldo Carvalho de Melo * be configured, defining the contents of any OA unit reports. 1496c1737f2bSArnaldo Carvalho de Melo */ 1497c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_METRICS_SET, 1498c1737f2bSArnaldo Carvalho de Melo 1499c1737f2bSArnaldo Carvalho de Melo /** 1500c1737f2bSArnaldo Carvalho de Melo * The value specifies the size and layout of OA unit reports. 1501c1737f2bSArnaldo Carvalho de Melo */ 1502c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_FORMAT, 1503c1737f2bSArnaldo Carvalho de Melo 1504c1737f2bSArnaldo Carvalho de Melo /** 1505c1737f2bSArnaldo Carvalho de Melo * Specifying this property implicitly requests periodic OA unit 1506c1737f2bSArnaldo Carvalho de Melo * sampling and (at least on Haswell) the sampling frequency is derived 1507c1737f2bSArnaldo Carvalho de Melo * from this exponent as follows: 1508c1737f2bSArnaldo Carvalho de Melo * 1509c1737f2bSArnaldo Carvalho de Melo * 80ns * 2^(period_exponent + 1) 1510c1737f2bSArnaldo Carvalho de Melo */ 1511c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_EXPONENT, 1512c1737f2bSArnaldo Carvalho de Melo 1513c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_MAX /* non-ABI */ 1514c1737f2bSArnaldo Carvalho de Melo }; 1515c1737f2bSArnaldo Carvalho de Melo 1516c1737f2bSArnaldo Carvalho de Melo struct drm_i915_perf_open_param { 1517c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1518c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 1519c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 1520c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_DISABLED (1<<2) 1521c1737f2bSArnaldo Carvalho de Melo 1522c1737f2bSArnaldo Carvalho de Melo /** The number of u64 (id, value) pairs */ 1523c1737f2bSArnaldo Carvalho de Melo __u32 num_properties; 1524c1737f2bSArnaldo Carvalho de Melo 1525c1737f2bSArnaldo Carvalho de Melo /** 1526c1737f2bSArnaldo Carvalho de Melo * Pointer to array of u64 (id, value) pairs configuring the stream 1527c1737f2bSArnaldo Carvalho de Melo * to open. 1528c1737f2bSArnaldo Carvalho de Melo */ 1529c1737f2bSArnaldo Carvalho de Melo __u64 properties_ptr; 1530c1737f2bSArnaldo Carvalho de Melo }; 1531c1737f2bSArnaldo Carvalho de Melo 1532c1737f2bSArnaldo Carvalho de Melo /** 1533c1737f2bSArnaldo Carvalho de Melo * Enable data capture for a stream that was either opened in a disabled state 1534c1737f2bSArnaldo Carvalho de Melo * via I915_PERF_FLAG_DISABLED or was later disabled via 1535c1737f2bSArnaldo Carvalho de Melo * I915_PERF_IOCTL_DISABLE. 1536c1737f2bSArnaldo Carvalho de Melo * 1537c1737f2bSArnaldo Carvalho de Melo * It is intended to be cheaper to disable and enable a stream than it may be 1538c1737f2bSArnaldo Carvalho de Melo * to close and re-open a stream with the same configuration. 1539c1737f2bSArnaldo Carvalho de Melo * 1540c1737f2bSArnaldo Carvalho de Melo * It's undefined whether any pending data for the stream will be lost. 1541c1737f2bSArnaldo Carvalho de Melo */ 1542c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 1543c1737f2bSArnaldo Carvalho de Melo 1544c1737f2bSArnaldo Carvalho de Melo /** 1545c1737f2bSArnaldo Carvalho de Melo * Disable data capture for a stream. 1546c1737f2bSArnaldo Carvalho de Melo * 1547c1737f2bSArnaldo Carvalho de Melo * It is an error to try and read a stream that is disabled. 1548c1737f2bSArnaldo Carvalho de Melo */ 1549c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 1550c1737f2bSArnaldo Carvalho de Melo 1551c1737f2bSArnaldo Carvalho de Melo /** 1552c1737f2bSArnaldo Carvalho de Melo * Common to all i915 perf records 1553c1737f2bSArnaldo Carvalho de Melo */ 1554c1737f2bSArnaldo Carvalho de Melo struct drm_i915_perf_record_header { 1555c1737f2bSArnaldo Carvalho de Melo __u32 type; 1556c1737f2bSArnaldo Carvalho de Melo __u16 pad; 1557c1737f2bSArnaldo Carvalho de Melo __u16 size; 1558c1737f2bSArnaldo Carvalho de Melo }; 1559c1737f2bSArnaldo Carvalho de Melo 1560c1737f2bSArnaldo Carvalho de Melo enum drm_i915_perf_record_type { 1561c1737f2bSArnaldo Carvalho de Melo 1562c1737f2bSArnaldo Carvalho de Melo /** 1563c1737f2bSArnaldo Carvalho de Melo * Samples are the work horse record type whose contents are extensible 1564c1737f2bSArnaldo Carvalho de Melo * and defined when opening an i915 perf stream based on the given 1565c1737f2bSArnaldo Carvalho de Melo * properties. 1566c1737f2bSArnaldo Carvalho de Melo * 1567c1737f2bSArnaldo Carvalho de Melo * Boolean properties following the naming convention 1568c1737f2bSArnaldo Carvalho de Melo * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 1569c1737f2bSArnaldo Carvalho de Melo * every sample. 1570c1737f2bSArnaldo Carvalho de Melo * 1571c1737f2bSArnaldo Carvalho de Melo * The order of these sample properties given by userspace has no 1572c1737f2bSArnaldo Carvalho de Melo * affect on the ordering of data within a sample. The order is 1573c1737f2bSArnaldo Carvalho de Melo * documented here. 1574c1737f2bSArnaldo Carvalho de Melo * 1575c1737f2bSArnaldo Carvalho de Melo * struct { 1576c1737f2bSArnaldo Carvalho de Melo * struct drm_i915_perf_record_header header; 1577c1737f2bSArnaldo Carvalho de Melo * 1578c1737f2bSArnaldo Carvalho de Melo * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 1579c1737f2bSArnaldo Carvalho de Melo * }; 1580c1737f2bSArnaldo Carvalho de Melo */ 1581c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_SAMPLE = 1, 1582c1737f2bSArnaldo Carvalho de Melo 1583c1737f2bSArnaldo Carvalho de Melo /* 1584c1737f2bSArnaldo Carvalho de Melo * Indicates that one or more OA reports were not written by the 1585c1737f2bSArnaldo Carvalho de Melo * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 1586c1737f2bSArnaldo Carvalho de Melo * command collides with periodic sampling - which would be more likely 1587c1737f2bSArnaldo Carvalho de Melo * at higher sampling frequencies. 1588c1737f2bSArnaldo Carvalho de Melo */ 1589c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 1590c1737f2bSArnaldo Carvalho de Melo 1591c1737f2bSArnaldo Carvalho de Melo /** 1592c1737f2bSArnaldo Carvalho de Melo * An error occurred that resulted in all pending OA reports being lost. 1593c1737f2bSArnaldo Carvalho de Melo */ 1594c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 1595c1737f2bSArnaldo Carvalho de Melo 1596c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_MAX /* non-ABI */ 1597c1737f2bSArnaldo Carvalho de Melo }; 1598c1737f2bSArnaldo Carvalho de Melo 1599549a3976SIngo Molnar /** 1600549a3976SIngo Molnar * Structure to upload perf dynamic configuration into the kernel. 1601549a3976SIngo Molnar */ 1602549a3976SIngo Molnar struct drm_i915_perf_oa_config { 1603549a3976SIngo Molnar /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ 1604549a3976SIngo Molnar char uuid[36]; 1605549a3976SIngo Molnar 1606549a3976SIngo Molnar __u32 n_mux_regs; 1607549a3976SIngo Molnar __u32 n_boolean_regs; 1608549a3976SIngo Molnar __u32 n_flex_regs; 1609549a3976SIngo Molnar 1610485be0cbSArnaldo Carvalho de Melo /* 161101f97511SArnaldo Carvalho de Melo * These fields are pointers to tuples of u32 values (register address, 161201f97511SArnaldo Carvalho de Melo * value). For example the expected length of the buffer pointed by 161301f97511SArnaldo Carvalho de Melo * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). 1614485be0cbSArnaldo Carvalho de Melo */ 1615485be0cbSArnaldo Carvalho de Melo __u64 mux_regs_ptr; 1616485be0cbSArnaldo Carvalho de Melo __u64 boolean_regs_ptr; 1617485be0cbSArnaldo Carvalho de Melo __u64 flex_regs_ptr; 1618549a3976SIngo Molnar }; 1619549a3976SIngo Molnar 162001f97511SArnaldo Carvalho de Melo struct drm_i915_query_item { 162101f97511SArnaldo Carvalho de Melo __u64 query_id; 162201f97511SArnaldo Carvalho de Melo #define DRM_I915_QUERY_TOPOLOGY_INFO 1 162301f97511SArnaldo Carvalho de Melo 162401f97511SArnaldo Carvalho de Melo /* 162501f97511SArnaldo Carvalho de Melo * When set to zero by userspace, this is filled with the size of the 162601f97511SArnaldo Carvalho de Melo * data to be written at the data_ptr pointer. The kernel sets this 162701f97511SArnaldo Carvalho de Melo * value to a negative value to signal an error on a particular query 162801f97511SArnaldo Carvalho de Melo * item. 162901f97511SArnaldo Carvalho de Melo */ 163001f97511SArnaldo Carvalho de Melo __s32 length; 163101f97511SArnaldo Carvalho de Melo 163201f97511SArnaldo Carvalho de Melo /* 163301f97511SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 163401f97511SArnaldo Carvalho de Melo */ 163501f97511SArnaldo Carvalho de Melo __u32 flags; 163601f97511SArnaldo Carvalho de Melo 163701f97511SArnaldo Carvalho de Melo /* 163801f97511SArnaldo Carvalho de Melo * Data will be written at the location pointed by data_ptr when the 163901f97511SArnaldo Carvalho de Melo * value of length matches the length of the data to be written by the 164001f97511SArnaldo Carvalho de Melo * kernel. 164101f97511SArnaldo Carvalho de Melo */ 164201f97511SArnaldo Carvalho de Melo __u64 data_ptr; 164301f97511SArnaldo Carvalho de Melo }; 164401f97511SArnaldo Carvalho de Melo 164501f97511SArnaldo Carvalho de Melo struct drm_i915_query { 164601f97511SArnaldo Carvalho de Melo __u32 num_items; 164701f97511SArnaldo Carvalho de Melo 164801f97511SArnaldo Carvalho de Melo /* 164901f97511SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 165001f97511SArnaldo Carvalho de Melo */ 165101f97511SArnaldo Carvalho de Melo __u32 flags; 165201f97511SArnaldo Carvalho de Melo 165301f97511SArnaldo Carvalho de Melo /* 165401f97511SArnaldo Carvalho de Melo * This points to an array of num_items drm_i915_query_item structures. 165501f97511SArnaldo Carvalho de Melo */ 165601f97511SArnaldo Carvalho de Melo __u64 items_ptr; 165701f97511SArnaldo Carvalho de Melo }; 165801f97511SArnaldo Carvalho de Melo 165901f97511SArnaldo Carvalho de Melo /* 166001f97511SArnaldo Carvalho de Melo * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : 166101f97511SArnaldo Carvalho de Melo * 166201f97511SArnaldo Carvalho de Melo * data: contains the 3 pieces of information : 166301f97511SArnaldo Carvalho de Melo * 166401f97511SArnaldo Carvalho de Melo * - the slice mask with one bit per slice telling whether a slice is 166501f97511SArnaldo Carvalho de Melo * available. The availability of slice X can be queried with the following 166601f97511SArnaldo Carvalho de Melo * formula : 166701f97511SArnaldo Carvalho de Melo * 166801f97511SArnaldo Carvalho de Melo * (data[X / 8] >> (X % 8)) & 1 166901f97511SArnaldo Carvalho de Melo * 167001f97511SArnaldo Carvalho de Melo * - the subslice mask for each slice with one bit per subslice telling 167101f97511SArnaldo Carvalho de Melo * whether a subslice is available. The availability of subslice Y in slice 167201f97511SArnaldo Carvalho de Melo * X can be queried with the following formula : 167301f97511SArnaldo Carvalho de Melo * 167401f97511SArnaldo Carvalho de Melo * (data[subslice_offset + 167501f97511SArnaldo Carvalho de Melo * X * subslice_stride + 167601f97511SArnaldo Carvalho de Melo * Y / 8] >> (Y % 8)) & 1 167701f97511SArnaldo Carvalho de Melo * 167801f97511SArnaldo Carvalho de Melo * - the EU mask for each subslice in each slice with one bit per EU telling 167901f97511SArnaldo Carvalho de Melo * whether an EU is available. The availability of EU Z in subslice Y in 168001f97511SArnaldo Carvalho de Melo * slice X can be queried with the following formula : 168101f97511SArnaldo Carvalho de Melo * 168201f97511SArnaldo Carvalho de Melo * (data[eu_offset + 168301f97511SArnaldo Carvalho de Melo * (X * max_subslices + Y) * eu_stride + 168401f97511SArnaldo Carvalho de Melo * Z / 8] >> (Z % 8)) & 1 168501f97511SArnaldo Carvalho de Melo */ 168601f97511SArnaldo Carvalho de Melo struct drm_i915_query_topology_info { 168701f97511SArnaldo Carvalho de Melo /* 168801f97511SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 168901f97511SArnaldo Carvalho de Melo */ 169001f97511SArnaldo Carvalho de Melo __u16 flags; 169101f97511SArnaldo Carvalho de Melo 169201f97511SArnaldo Carvalho de Melo __u16 max_slices; 169301f97511SArnaldo Carvalho de Melo __u16 max_subslices; 169401f97511SArnaldo Carvalho de Melo __u16 max_eus_per_subslice; 169501f97511SArnaldo Carvalho de Melo 169601f97511SArnaldo Carvalho de Melo /* 169701f97511SArnaldo Carvalho de Melo * Offset in data[] at which the subslice masks are stored. 169801f97511SArnaldo Carvalho de Melo */ 169901f97511SArnaldo Carvalho de Melo __u16 subslice_offset; 170001f97511SArnaldo Carvalho de Melo 170101f97511SArnaldo Carvalho de Melo /* 170201f97511SArnaldo Carvalho de Melo * Stride at which each of the subslice masks for each slice are 170301f97511SArnaldo Carvalho de Melo * stored. 170401f97511SArnaldo Carvalho de Melo */ 170501f97511SArnaldo Carvalho de Melo __u16 subslice_stride; 170601f97511SArnaldo Carvalho de Melo 170701f97511SArnaldo Carvalho de Melo /* 170801f97511SArnaldo Carvalho de Melo * Offset in data[] at which the EU masks are stored. 170901f97511SArnaldo Carvalho de Melo */ 171001f97511SArnaldo Carvalho de Melo __u16 eu_offset; 171101f97511SArnaldo Carvalho de Melo 171201f97511SArnaldo Carvalho de Melo /* 171301f97511SArnaldo Carvalho de Melo * Stride at which each of the EU masks for each subslice are stored. 171401f97511SArnaldo Carvalho de Melo */ 171501f97511SArnaldo Carvalho de Melo __u16 eu_stride; 171601f97511SArnaldo Carvalho de Melo 171701f97511SArnaldo Carvalho de Melo __u8 data[]; 171801f97511SArnaldo Carvalho de Melo }; 171901f97511SArnaldo Carvalho de Melo 1720c1737f2bSArnaldo Carvalho de Melo #if defined(__cplusplus) 1721c1737f2bSArnaldo Carvalho de Melo } 1722c1737f2bSArnaldo Carvalho de Melo #endif 1723c1737f2bSArnaldo Carvalho de Melo 1724c1737f2bSArnaldo Carvalho de Melo #endif /* _UAPI_I915_DRM_H_ */ 1725