1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_INDEX_H 3 #define _ASM_X86_MSR_INDEX_H 4 5 #include <linux/bits.h> 6 7 /* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14 /* x86-64 specific MSRs */ 15 #define MSR_EFER 0xc0000080 /* extended feature register */ 16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25 /* EFER bits: */ 26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27 #define _EFER_LME 8 /* Long mode enable */ 28 #define _EFER_LMA 10 /* Long mode active (read-only) */ 29 #define _EFER_NX 11 /* No execute enable */ 30 #define _EFER_SVME 12 /* Enable virtualization */ 31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34 #define EFER_SCE (1<<_EFER_SCE) 35 #define EFER_LME (1<<_EFER_LME) 36 #define EFER_LMA (1<<_EFER_LMA) 37 #define EFER_NX (1<<_EFER_NX) 38 #define EFER_SVME (1<<_EFER_SVME) 39 #define EFER_LMSLE (1<<_EFER_LMSLE) 40 #define EFER_FFXSR (1<<_EFER_FFXSR) 41 42 /* Intel MSRs. Some also available on other CPUs */ 43 44 #define MSR_TEST_CTRL 0x00000033 45 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54 55 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 57 58 #define MSR_PPIN_CTL 0x0000004e 59 #define MSR_PPIN 0x0000004f 60 61 #define MSR_IA32_PERFCTR0 0x000000c1 62 #define MSR_IA32_PERFCTR1 0x000000c2 63 #define MSR_FSB_FREQ 0x000000cd 64 #define MSR_PLATFORM_INFO 0x000000ce 65 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 66 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67 68 #define MSR_IA32_UMWAIT_CONTROL 0xe1 69 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71 /* 72 * The time field is bit[31:2], but representing a 32bit value with 73 * bit[1:0] zero. 74 */ 75 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76 77 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 78 #define MSR_IA32_CORE_CAPS 0x000000cf 79 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 80 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 81 82 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 83 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 84 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 85 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 86 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 87 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 88 89 #define MSR_MTRRcap 0x000000fe 90 91 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 92 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 93 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 94 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95 #define ARCH_CAP_SSB_NO BIT(4) /* 96 * Not susceptible to Speculative Store Bypass 97 * attack, so no Speculative Store Bypass 98 * control required. 99 */ 100 #define ARCH_CAP_MDS_NO BIT(5) /* 101 * Not susceptible to 102 * Microarchitectural Data 103 * Sampling (MDS) vulnerabilities. 104 */ 105 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 106 * The processor is not susceptible to a 107 * machine check error due to modifying the 108 * code page size along with either the 109 * physical address or cache type 110 * without TLB invalidation. 111 */ 112 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 113 #define ARCH_CAP_TAA_NO BIT(8) /* 114 * Not susceptible to 115 * TSX Async Abort (TAA) vulnerabilities. 116 */ 117 118 #define MSR_IA32_FLUSH_CMD 0x0000010b 119 #define L1D_FLUSH BIT(0) /* 120 * Writeback and invalidate the 121 * L1 data cache. 122 */ 123 124 #define MSR_IA32_BBL_CR_CTL 0x00000119 125 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 126 127 #define MSR_IA32_TSX_CTRL 0x00000122 128 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 129 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 130 131 #define MSR_IA32_SYSENTER_CS 0x00000174 132 #define MSR_IA32_SYSENTER_ESP 0x00000175 133 #define MSR_IA32_SYSENTER_EIP 0x00000176 134 135 #define MSR_IA32_MCG_CAP 0x00000179 136 #define MSR_IA32_MCG_STATUS 0x0000017a 137 #define MSR_IA32_MCG_CTL 0x0000017b 138 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 139 140 #define MSR_OFFCORE_RSP_0 0x000001a6 141 #define MSR_OFFCORE_RSP_1 0x000001a7 142 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 143 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 144 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 145 146 #define MSR_LBR_SELECT 0x000001c8 147 #define MSR_LBR_TOS 0x000001c9 148 #define MSR_LBR_NHM_FROM 0x00000680 149 #define MSR_LBR_NHM_TO 0x000006c0 150 #define MSR_LBR_CORE_FROM 0x00000040 151 #define MSR_LBR_CORE_TO 0x00000060 152 153 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 154 #define LBR_INFO_MISPRED BIT_ULL(63) 155 #define LBR_INFO_IN_TX BIT_ULL(62) 156 #define LBR_INFO_ABORT BIT_ULL(61) 157 #define LBR_INFO_CYCLES 0xffff 158 159 #define MSR_IA32_PEBS_ENABLE 0x000003f1 160 #define MSR_PEBS_DATA_CFG 0x000003f2 161 #define MSR_IA32_DS_AREA 0x00000600 162 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 163 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 164 165 #define MSR_IA32_RTIT_CTL 0x00000570 166 #define RTIT_CTL_TRACEEN BIT(0) 167 #define RTIT_CTL_CYCLEACC BIT(1) 168 #define RTIT_CTL_OS BIT(2) 169 #define RTIT_CTL_USR BIT(3) 170 #define RTIT_CTL_PWR_EVT_EN BIT(4) 171 #define RTIT_CTL_FUP_ON_PTW BIT(5) 172 #define RTIT_CTL_FABRIC_EN BIT(6) 173 #define RTIT_CTL_CR3EN BIT(7) 174 #define RTIT_CTL_TOPA BIT(8) 175 #define RTIT_CTL_MTC_EN BIT(9) 176 #define RTIT_CTL_TSC_EN BIT(10) 177 #define RTIT_CTL_DISRETC BIT(11) 178 #define RTIT_CTL_PTW_EN BIT(12) 179 #define RTIT_CTL_BRANCH_EN BIT(13) 180 #define RTIT_CTL_MTC_RANGE_OFFSET 14 181 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 182 #define RTIT_CTL_CYC_THRESH_OFFSET 19 183 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 184 #define RTIT_CTL_PSB_FREQ_OFFSET 24 185 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 186 #define RTIT_CTL_ADDR0_OFFSET 32 187 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 188 #define RTIT_CTL_ADDR1_OFFSET 36 189 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 190 #define RTIT_CTL_ADDR2_OFFSET 40 191 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 192 #define RTIT_CTL_ADDR3_OFFSET 44 193 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 194 #define MSR_IA32_RTIT_STATUS 0x00000571 195 #define RTIT_STATUS_FILTEREN BIT(0) 196 #define RTIT_STATUS_CONTEXTEN BIT(1) 197 #define RTIT_STATUS_TRIGGEREN BIT(2) 198 #define RTIT_STATUS_BUFFOVF BIT(3) 199 #define RTIT_STATUS_ERROR BIT(4) 200 #define RTIT_STATUS_STOPPED BIT(5) 201 #define RTIT_STATUS_BYTECNT_OFFSET 32 202 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 203 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 204 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 205 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 206 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 207 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 208 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 209 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 210 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 211 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 212 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 213 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 214 215 #define MSR_MTRRfix64K_00000 0x00000250 216 #define MSR_MTRRfix16K_80000 0x00000258 217 #define MSR_MTRRfix16K_A0000 0x00000259 218 #define MSR_MTRRfix4K_C0000 0x00000268 219 #define MSR_MTRRfix4K_C8000 0x00000269 220 #define MSR_MTRRfix4K_D0000 0x0000026a 221 #define MSR_MTRRfix4K_D8000 0x0000026b 222 #define MSR_MTRRfix4K_E0000 0x0000026c 223 #define MSR_MTRRfix4K_E8000 0x0000026d 224 #define MSR_MTRRfix4K_F0000 0x0000026e 225 #define MSR_MTRRfix4K_F8000 0x0000026f 226 #define MSR_MTRRdefType 0x000002ff 227 228 #define MSR_IA32_CR_PAT 0x00000277 229 230 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 231 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 232 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 233 #define MSR_IA32_LASTINTFROMIP 0x000001dd 234 #define MSR_IA32_LASTINTTOIP 0x000001de 235 236 /* DEBUGCTLMSR bits (others vary by model): */ 237 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 238 #define DEBUGCTLMSR_BTF_SHIFT 1 239 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 240 #define DEBUGCTLMSR_TR (1UL << 6) 241 #define DEBUGCTLMSR_BTS (1UL << 7) 242 #define DEBUGCTLMSR_BTINT (1UL << 8) 243 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 244 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 245 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 246 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 247 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 248 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 249 250 #define MSR_PEBS_FRONTEND 0x000003f7 251 252 #define MSR_IA32_POWER_CTL 0x000001fc 253 254 #define MSR_IA32_MC0_CTL 0x00000400 255 #define MSR_IA32_MC0_STATUS 0x00000401 256 #define MSR_IA32_MC0_ADDR 0x00000402 257 #define MSR_IA32_MC0_MISC 0x00000403 258 259 /* C-state Residency Counters */ 260 #define MSR_PKG_C3_RESIDENCY 0x000003f8 261 #define MSR_PKG_C6_RESIDENCY 0x000003f9 262 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 263 #define MSR_PKG_C7_RESIDENCY 0x000003fa 264 #define MSR_CORE_C3_RESIDENCY 0x000003fc 265 #define MSR_CORE_C6_RESIDENCY 0x000003fd 266 #define MSR_CORE_C7_RESIDENCY 0x000003fe 267 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 268 #define MSR_PKG_C2_RESIDENCY 0x0000060d 269 #define MSR_PKG_C8_RESIDENCY 0x00000630 270 #define MSR_PKG_C9_RESIDENCY 0x00000631 271 #define MSR_PKG_C10_RESIDENCY 0x00000632 272 273 /* Interrupt Response Limit */ 274 #define MSR_PKGC3_IRTL 0x0000060a 275 #define MSR_PKGC6_IRTL 0x0000060b 276 #define MSR_PKGC7_IRTL 0x0000060c 277 #define MSR_PKGC8_IRTL 0x00000633 278 #define MSR_PKGC9_IRTL 0x00000634 279 #define MSR_PKGC10_IRTL 0x00000635 280 281 /* Run Time Average Power Limiting (RAPL) Interface */ 282 283 #define MSR_RAPL_POWER_UNIT 0x00000606 284 285 #define MSR_PKG_POWER_LIMIT 0x00000610 286 #define MSR_PKG_ENERGY_STATUS 0x00000611 287 #define MSR_PKG_PERF_STATUS 0x00000613 288 #define MSR_PKG_POWER_INFO 0x00000614 289 290 #define MSR_DRAM_POWER_LIMIT 0x00000618 291 #define MSR_DRAM_ENERGY_STATUS 0x00000619 292 #define MSR_DRAM_PERF_STATUS 0x0000061b 293 #define MSR_DRAM_POWER_INFO 0x0000061c 294 295 #define MSR_PP0_POWER_LIMIT 0x00000638 296 #define MSR_PP0_ENERGY_STATUS 0x00000639 297 #define MSR_PP0_POLICY 0x0000063a 298 #define MSR_PP0_PERF_STATUS 0x0000063b 299 300 #define MSR_PP1_POWER_LIMIT 0x00000640 301 #define MSR_PP1_ENERGY_STATUS 0x00000641 302 #define MSR_PP1_POLICY 0x00000642 303 304 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 305 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 306 307 /* Config TDP MSRs */ 308 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 309 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 310 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 311 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 312 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 313 314 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 315 316 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 317 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 318 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 319 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 320 321 #define MSR_CORE_C1_RES 0x00000660 322 #define MSR_MODULE_C6_RES_MS 0x00000664 323 324 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 325 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 326 327 #define MSR_ATOM_CORE_RATIOS 0x0000066a 328 #define MSR_ATOM_CORE_VIDS 0x0000066b 329 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 330 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 331 332 333 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 334 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 335 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 336 337 /* Hardware P state interface */ 338 #define MSR_PPERF 0x0000064e 339 #define MSR_PERF_LIMIT_REASONS 0x0000064f 340 #define MSR_PM_ENABLE 0x00000770 341 #define MSR_HWP_CAPABILITIES 0x00000771 342 #define MSR_HWP_REQUEST_PKG 0x00000772 343 #define MSR_HWP_INTERRUPT 0x00000773 344 #define MSR_HWP_REQUEST 0x00000774 345 #define MSR_HWP_STATUS 0x00000777 346 347 /* CPUID.6.EAX */ 348 #define HWP_BASE_BIT (1<<7) 349 #define HWP_NOTIFICATIONS_BIT (1<<8) 350 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 351 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 352 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 353 354 /* IA32_HWP_CAPABILITIES */ 355 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 356 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 357 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 358 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 359 360 /* IA32_HWP_REQUEST */ 361 #define HWP_MIN_PERF(x) (x & 0xff) 362 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 363 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 364 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 365 #define HWP_EPP_PERFORMANCE 0x00 366 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 367 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 368 #define HWP_EPP_POWERSAVE 0xFF 369 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 370 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 371 372 /* IA32_HWP_STATUS */ 373 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 374 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 375 376 /* IA32_HWP_INTERRUPT */ 377 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 378 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 379 380 #define MSR_AMD64_MC0_MASK 0xc0010044 381 382 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 383 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 384 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 385 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 386 387 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 388 389 /* These are consecutive and not in the normal 4er MCE bank block */ 390 #define MSR_IA32_MC0_CTL2 0x00000280 391 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 392 393 #define MSR_P6_PERFCTR0 0x000000c1 394 #define MSR_P6_PERFCTR1 0x000000c2 395 #define MSR_P6_EVNTSEL0 0x00000186 396 #define MSR_P6_EVNTSEL1 0x00000187 397 398 #define MSR_KNC_PERFCTR0 0x00000020 399 #define MSR_KNC_PERFCTR1 0x00000021 400 #define MSR_KNC_EVNTSEL0 0x00000028 401 #define MSR_KNC_EVNTSEL1 0x00000029 402 403 /* Alternative perfctr range with full access. */ 404 #define MSR_IA32_PMC0 0x000004c1 405 406 /* Auto-reload via MSR instead of DS area */ 407 #define MSR_RELOAD_PMC0 0x000014c1 408 #define MSR_RELOAD_FIXED_CTR0 0x00001309 409 410 /* 411 * AMD64 MSRs. Not complete. See the architecture manual for a more 412 * complete list. 413 */ 414 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 415 #define MSR_AMD64_TSC_RATIO 0xc0000104 416 #define MSR_AMD64_NB_CFG 0xc001001f 417 #define MSR_AMD64_CPUID_FN_1 0xc0011004 418 #define MSR_AMD64_PATCH_LOADER 0xc0010020 419 #define MSR_AMD_PERF_CTL 0xc0010062 420 #define MSR_AMD_PERF_STATUS 0xc0010063 421 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 422 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 423 #define MSR_AMD64_OSVW_STATUS 0xc0010141 424 #define MSR_AMD_PPIN_CTL 0xc00102f0 425 #define MSR_AMD_PPIN 0xc00102f1 426 #define MSR_AMD64_LS_CFG 0xc0011020 427 #define MSR_AMD64_DC_CFG 0xc0011022 428 #define MSR_AMD64_BU_CFG2 0xc001102a 429 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 430 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 431 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 432 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 433 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 434 #define MSR_AMD64_IBSOPCTL 0xc0011033 435 #define MSR_AMD64_IBSOPRIP 0xc0011034 436 #define MSR_AMD64_IBSOPDATA 0xc0011035 437 #define MSR_AMD64_IBSOPDATA2 0xc0011036 438 #define MSR_AMD64_IBSOPDATA3 0xc0011037 439 #define MSR_AMD64_IBSDCLINAD 0xc0011038 440 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 441 #define MSR_AMD64_IBSOP_REG_COUNT 7 442 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 443 #define MSR_AMD64_IBSCTL 0xc001103a 444 #define MSR_AMD64_IBSBRTARGET 0xc001103b 445 #define MSR_AMD64_IBSOPDATA4 0xc001103d 446 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 447 #define MSR_AMD64_SEV 0xc0010131 448 #define MSR_AMD64_SEV_ENABLED_BIT 0 449 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 450 451 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 452 453 /* Fam 17h MSRs */ 454 #define MSR_F17H_IRPERF 0xc00000e9 455 456 /* Fam 16h MSRs */ 457 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 458 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 459 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 460 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 461 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 462 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 463 464 /* Fam 15h MSRs */ 465 #define MSR_F15H_PERF_CTL 0xc0010200 466 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 467 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 468 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 469 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 470 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 471 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 472 473 #define MSR_F15H_PERF_CTR 0xc0010201 474 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 475 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 476 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 477 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 478 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 479 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 480 481 #define MSR_F15H_NB_PERF_CTL 0xc0010240 482 #define MSR_F15H_NB_PERF_CTR 0xc0010241 483 #define MSR_F15H_PTSC 0xc0010280 484 #define MSR_F15H_IC_CFG 0xc0011021 485 #define MSR_F15H_EX_CFG 0xc001102c 486 487 /* Fam 10h MSRs */ 488 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 489 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 490 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 491 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 492 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 493 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 494 #define MSR_FAM10H_NODE_ID 0xc001100c 495 #define MSR_F10H_DECFG 0xc0011029 496 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 497 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 498 499 /* K8 MSRs */ 500 #define MSR_K8_TOP_MEM1 0xc001001a 501 #define MSR_K8_TOP_MEM2 0xc001001d 502 #define MSR_K8_SYSCFG 0xc0010010 503 #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 504 #define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 505 #define MSR_K8_INT_PENDING_MSG 0xc0010055 506 /* C1E active bits in int pending message */ 507 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 508 #define MSR_K8_TSEG_ADDR 0xc0010112 509 #define MSR_K8_TSEG_MASK 0xc0010113 510 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 511 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 512 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 513 514 /* K7 MSRs */ 515 #define MSR_K7_EVNTSEL0 0xc0010000 516 #define MSR_K7_PERFCTR0 0xc0010004 517 #define MSR_K7_EVNTSEL1 0xc0010001 518 #define MSR_K7_PERFCTR1 0xc0010005 519 #define MSR_K7_EVNTSEL2 0xc0010002 520 #define MSR_K7_PERFCTR2 0xc0010006 521 #define MSR_K7_EVNTSEL3 0xc0010003 522 #define MSR_K7_PERFCTR3 0xc0010007 523 #define MSR_K7_CLK_CTL 0xc001001b 524 #define MSR_K7_HWCR 0xc0010015 525 #define MSR_K7_HWCR_SMMLOCK_BIT 0 526 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 527 #define MSR_K7_HWCR_IRPERF_EN_BIT 30 528 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 529 #define MSR_K7_FID_VID_CTL 0xc0010041 530 #define MSR_K7_FID_VID_STATUS 0xc0010042 531 532 /* K6 MSRs */ 533 #define MSR_K6_WHCR 0xc0000082 534 #define MSR_K6_UWCCR 0xc0000085 535 #define MSR_K6_EPMR 0xc0000086 536 #define MSR_K6_PSOR 0xc0000087 537 #define MSR_K6_PFIR 0xc0000088 538 539 /* Centaur-Hauls/IDT defined MSRs. */ 540 #define MSR_IDT_FCR1 0x00000107 541 #define MSR_IDT_FCR2 0x00000108 542 #define MSR_IDT_FCR3 0x00000109 543 #define MSR_IDT_FCR4 0x0000010a 544 545 #define MSR_IDT_MCR0 0x00000110 546 #define MSR_IDT_MCR1 0x00000111 547 #define MSR_IDT_MCR2 0x00000112 548 #define MSR_IDT_MCR3 0x00000113 549 #define MSR_IDT_MCR4 0x00000114 550 #define MSR_IDT_MCR5 0x00000115 551 #define MSR_IDT_MCR6 0x00000116 552 #define MSR_IDT_MCR7 0x00000117 553 #define MSR_IDT_MCR_CTRL 0x00000120 554 555 /* VIA Cyrix defined MSRs*/ 556 #define MSR_VIA_FCR 0x00001107 557 #define MSR_VIA_LONGHAUL 0x0000110a 558 #define MSR_VIA_RNG 0x0000110b 559 #define MSR_VIA_BCR2 0x00001147 560 561 /* Transmeta defined MSRs */ 562 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 563 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 564 #define MSR_TMTA_LRTI_READOUT 0x80868018 565 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 566 567 /* Intel defined MSRs. */ 568 #define MSR_IA32_P5_MC_ADDR 0x00000000 569 #define MSR_IA32_P5_MC_TYPE 0x00000001 570 #define MSR_IA32_TSC 0x00000010 571 #define MSR_IA32_PLATFORM_ID 0x00000017 572 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 573 #define MSR_EBC_FREQUENCY_ID 0x0000002c 574 #define MSR_SMI_COUNT 0x00000034 575 576 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 577 #define MSR_IA32_FEAT_CTL 0x0000003a 578 #define FEAT_CTL_LOCKED BIT(0) 579 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 580 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 581 #define FEAT_CTL_LMCE_ENABLED BIT(20) 582 583 #define MSR_IA32_TSC_ADJUST 0x0000003b 584 #define MSR_IA32_BNDCFGS 0x00000d90 585 586 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 587 588 #define MSR_IA32_XSS 0x00000da0 589 590 #define MSR_IA32_APICBASE 0x0000001b 591 #define MSR_IA32_APICBASE_BSP (1<<8) 592 #define MSR_IA32_APICBASE_ENABLE (1<<11) 593 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 594 595 #define MSR_IA32_TSCDEADLINE 0x000006e0 596 597 #define MSR_IA32_UCODE_WRITE 0x00000079 598 #define MSR_IA32_UCODE_REV 0x0000008b 599 600 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 601 #define MSR_IA32_SMBASE 0x0000009e 602 603 #define MSR_IA32_PERF_STATUS 0x00000198 604 #define MSR_IA32_PERF_CTL 0x00000199 605 #define INTEL_PERF_CTL_MASK 0xffff 606 607 #define MSR_IA32_MPERF 0x000000e7 608 #define MSR_IA32_APERF 0x000000e8 609 610 #define MSR_IA32_THERM_CONTROL 0x0000019a 611 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 612 613 #define THERM_INT_HIGH_ENABLE (1 << 0) 614 #define THERM_INT_LOW_ENABLE (1 << 1) 615 #define THERM_INT_PLN_ENABLE (1 << 24) 616 617 #define MSR_IA32_THERM_STATUS 0x0000019c 618 619 #define THERM_STATUS_PROCHOT (1 << 0) 620 #define THERM_STATUS_POWER_LIMIT (1 << 10) 621 622 #define MSR_THERM2_CTL 0x0000019d 623 624 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 625 626 #define MSR_IA32_MISC_ENABLE 0x000001a0 627 628 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 629 630 #define MSR_MISC_FEATURE_CONTROL 0x000001a4 631 #define MSR_MISC_PWR_MGMT 0x000001aa 632 633 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 634 #define ENERGY_PERF_BIAS_PERFORMANCE 0 635 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 636 #define ENERGY_PERF_BIAS_NORMAL 6 637 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 638 #define ENERGY_PERF_BIAS_POWERSAVE 15 639 640 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 641 642 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 643 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 644 645 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 646 647 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 648 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 649 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 650 651 /* Thermal Thresholds Support */ 652 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 653 #define THERM_SHIFT_THRESHOLD0 8 654 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 655 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 656 #define THERM_SHIFT_THRESHOLD1 16 657 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 658 #define THERM_STATUS_THRESHOLD0 (1 << 6) 659 #define THERM_LOG_THRESHOLD0 (1 << 7) 660 #define THERM_STATUS_THRESHOLD1 (1 << 8) 661 #define THERM_LOG_THRESHOLD1 (1 << 9) 662 663 /* MISC_ENABLE bits: architectural */ 664 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 665 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 666 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 667 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 668 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 669 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 670 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 671 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 672 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 673 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 674 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 675 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 676 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 677 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 678 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 679 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 680 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 681 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 682 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 683 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 684 685 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 686 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 687 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 688 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 689 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 690 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 691 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 692 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 693 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 694 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 695 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 696 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 697 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 698 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 699 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 700 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 701 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 702 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 703 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 704 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 705 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 706 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 707 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 708 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 709 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 710 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 711 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 712 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 713 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 714 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 715 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 716 717 /* MISC_FEATURES_ENABLES non-architectural features */ 718 #define MSR_MISC_FEATURES_ENABLES 0x00000140 719 720 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 721 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 722 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 723 724 #define MSR_IA32_TSC_DEADLINE 0x000006E0 725 726 727 #define MSR_TSX_FORCE_ABORT 0x0000010F 728 729 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 730 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 731 732 /* P4/Xeon+ specific */ 733 #define MSR_IA32_MCG_EAX 0x00000180 734 #define MSR_IA32_MCG_EBX 0x00000181 735 #define MSR_IA32_MCG_ECX 0x00000182 736 #define MSR_IA32_MCG_EDX 0x00000183 737 #define MSR_IA32_MCG_ESI 0x00000184 738 #define MSR_IA32_MCG_EDI 0x00000185 739 #define MSR_IA32_MCG_EBP 0x00000186 740 #define MSR_IA32_MCG_ESP 0x00000187 741 #define MSR_IA32_MCG_EFLAGS 0x00000188 742 #define MSR_IA32_MCG_EIP 0x00000189 743 #define MSR_IA32_MCG_RESERVED 0x0000018a 744 745 /* Pentium IV performance counter MSRs */ 746 #define MSR_P4_BPU_PERFCTR0 0x00000300 747 #define MSR_P4_BPU_PERFCTR1 0x00000301 748 #define MSR_P4_BPU_PERFCTR2 0x00000302 749 #define MSR_P4_BPU_PERFCTR3 0x00000303 750 #define MSR_P4_MS_PERFCTR0 0x00000304 751 #define MSR_P4_MS_PERFCTR1 0x00000305 752 #define MSR_P4_MS_PERFCTR2 0x00000306 753 #define MSR_P4_MS_PERFCTR3 0x00000307 754 #define MSR_P4_FLAME_PERFCTR0 0x00000308 755 #define MSR_P4_FLAME_PERFCTR1 0x00000309 756 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 757 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 758 #define MSR_P4_IQ_PERFCTR0 0x0000030c 759 #define MSR_P4_IQ_PERFCTR1 0x0000030d 760 #define MSR_P4_IQ_PERFCTR2 0x0000030e 761 #define MSR_P4_IQ_PERFCTR3 0x0000030f 762 #define MSR_P4_IQ_PERFCTR4 0x00000310 763 #define MSR_P4_IQ_PERFCTR5 0x00000311 764 #define MSR_P4_BPU_CCCR0 0x00000360 765 #define MSR_P4_BPU_CCCR1 0x00000361 766 #define MSR_P4_BPU_CCCR2 0x00000362 767 #define MSR_P4_BPU_CCCR3 0x00000363 768 #define MSR_P4_MS_CCCR0 0x00000364 769 #define MSR_P4_MS_CCCR1 0x00000365 770 #define MSR_P4_MS_CCCR2 0x00000366 771 #define MSR_P4_MS_CCCR3 0x00000367 772 #define MSR_P4_FLAME_CCCR0 0x00000368 773 #define MSR_P4_FLAME_CCCR1 0x00000369 774 #define MSR_P4_FLAME_CCCR2 0x0000036a 775 #define MSR_P4_FLAME_CCCR3 0x0000036b 776 #define MSR_P4_IQ_CCCR0 0x0000036c 777 #define MSR_P4_IQ_CCCR1 0x0000036d 778 #define MSR_P4_IQ_CCCR2 0x0000036e 779 #define MSR_P4_IQ_CCCR3 0x0000036f 780 #define MSR_P4_IQ_CCCR4 0x00000370 781 #define MSR_P4_IQ_CCCR5 0x00000371 782 #define MSR_P4_ALF_ESCR0 0x000003ca 783 #define MSR_P4_ALF_ESCR1 0x000003cb 784 #define MSR_P4_BPU_ESCR0 0x000003b2 785 #define MSR_P4_BPU_ESCR1 0x000003b3 786 #define MSR_P4_BSU_ESCR0 0x000003a0 787 #define MSR_P4_BSU_ESCR1 0x000003a1 788 #define MSR_P4_CRU_ESCR0 0x000003b8 789 #define MSR_P4_CRU_ESCR1 0x000003b9 790 #define MSR_P4_CRU_ESCR2 0x000003cc 791 #define MSR_P4_CRU_ESCR3 0x000003cd 792 #define MSR_P4_CRU_ESCR4 0x000003e0 793 #define MSR_P4_CRU_ESCR5 0x000003e1 794 #define MSR_P4_DAC_ESCR0 0x000003a8 795 #define MSR_P4_DAC_ESCR1 0x000003a9 796 #define MSR_P4_FIRM_ESCR0 0x000003a4 797 #define MSR_P4_FIRM_ESCR1 0x000003a5 798 #define MSR_P4_FLAME_ESCR0 0x000003a6 799 #define MSR_P4_FLAME_ESCR1 0x000003a7 800 #define MSR_P4_FSB_ESCR0 0x000003a2 801 #define MSR_P4_FSB_ESCR1 0x000003a3 802 #define MSR_P4_IQ_ESCR0 0x000003ba 803 #define MSR_P4_IQ_ESCR1 0x000003bb 804 #define MSR_P4_IS_ESCR0 0x000003b4 805 #define MSR_P4_IS_ESCR1 0x000003b5 806 #define MSR_P4_ITLB_ESCR0 0x000003b6 807 #define MSR_P4_ITLB_ESCR1 0x000003b7 808 #define MSR_P4_IX_ESCR0 0x000003c8 809 #define MSR_P4_IX_ESCR1 0x000003c9 810 #define MSR_P4_MOB_ESCR0 0x000003aa 811 #define MSR_P4_MOB_ESCR1 0x000003ab 812 #define MSR_P4_MS_ESCR0 0x000003c0 813 #define MSR_P4_MS_ESCR1 0x000003c1 814 #define MSR_P4_PMH_ESCR0 0x000003ac 815 #define MSR_P4_PMH_ESCR1 0x000003ad 816 #define MSR_P4_RAT_ESCR0 0x000003bc 817 #define MSR_P4_RAT_ESCR1 0x000003bd 818 #define MSR_P4_SAAT_ESCR0 0x000003ae 819 #define MSR_P4_SAAT_ESCR1 0x000003af 820 #define MSR_P4_SSU_ESCR0 0x000003be 821 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 822 823 #define MSR_P4_TBPU_ESCR0 0x000003c2 824 #define MSR_P4_TBPU_ESCR1 0x000003c3 825 #define MSR_P4_TC_ESCR0 0x000003c4 826 #define MSR_P4_TC_ESCR1 0x000003c5 827 #define MSR_P4_U2L_ESCR0 0x000003b0 828 #define MSR_P4_U2L_ESCR1 0x000003b1 829 830 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 831 832 /* Intel Core-based CPU performance counters */ 833 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 834 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 835 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 836 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 837 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 838 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 839 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 840 841 /* PERF_GLOBAL_OVF_CTL bits */ 842 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 843 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 844 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 845 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 846 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 847 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 848 849 /* Geode defined MSRs */ 850 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 851 852 /* Intel VT MSRs */ 853 #define MSR_IA32_VMX_BASIC 0x00000480 854 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 855 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 856 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 857 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 858 #define MSR_IA32_VMX_MISC 0x00000485 859 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 860 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 861 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 862 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 863 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 864 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 865 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 866 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 867 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 868 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 869 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 870 #define MSR_IA32_VMX_VMFUNC 0x00000491 871 872 /* VMX_BASIC bits and bitmasks */ 873 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 874 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 875 #define VMX_BASIC_64 0x0001000000000000LLU 876 #define VMX_BASIC_MEM_TYPE_SHIFT 50 877 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 878 #define VMX_BASIC_MEM_TYPE_WB 6LLU 879 #define VMX_BASIC_INOUT 0x0040000000000000LLU 880 881 /* MSR_IA32_VMX_MISC bits */ 882 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 883 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 884 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 885 /* AMD-V MSRs */ 886 887 #define MSR_VM_CR 0xc0010114 888 #define MSR_VM_IGNNE 0xc0010115 889 #define MSR_VM_HSAVE_PA 0xc0010117 890 891 #endif /* _ASM_X86_MSR_INDEX_H */ 892