1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_INDEX_H 3 #define _ASM_X86_MSR_INDEX_H 4 5 #include <linux/bits.h> 6 7 /* CPU model specific register (MSR) numbers. */ 8 9 /* x86-64 specific MSRs */ 10 #define MSR_EFER 0xc0000080 /* extended feature register */ 11 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19 20 /* EFER bits: */ 21 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22 #define _EFER_LME 8 /* Long mode enable */ 23 #define _EFER_LMA 10 /* Long mode active (read-only) */ 24 #define _EFER_NX 11 /* No execute enable */ 25 #define _EFER_SVME 12 /* Enable virtualization */ 26 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 28 29 #define EFER_SCE (1<<_EFER_SCE) 30 #define EFER_LME (1<<_EFER_LME) 31 #define EFER_LMA (1<<_EFER_LMA) 32 #define EFER_NX (1<<_EFER_NX) 33 #define EFER_SVME (1<<_EFER_SVME) 34 #define EFER_LMSLE (1<<_EFER_LMSLE) 35 #define EFER_FFXSR (1<<_EFER_FFXSR) 36 37 /* Intel MSRs. Some also available on other CPUs */ 38 39 #define MSR_TEST_CTRL 0x00000033 40 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 41 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 42 43 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 44 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 45 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 46 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 47 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 48 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 49 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 50 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 51 52 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 53 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 54 55 #define MSR_PPIN_CTL 0x0000004e 56 #define MSR_PPIN 0x0000004f 57 58 #define MSR_IA32_PERFCTR0 0x000000c1 59 #define MSR_IA32_PERFCTR1 0x000000c2 60 #define MSR_FSB_FREQ 0x000000cd 61 #define MSR_PLATFORM_INFO 0x000000ce 62 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 63 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 64 65 #define MSR_IA32_UMWAIT_CONTROL 0xe1 66 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 67 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 68 /* 69 * The time field is bit[31:2], but representing a 32bit value with 70 * bit[1:0] zero. 71 */ 72 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 73 74 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 75 #define MSR_IA32_CORE_CAPS 0x000000cf 76 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 77 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 78 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 79 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 80 81 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 82 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 83 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 84 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 85 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 86 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 87 88 #define MSR_MTRRcap 0x000000fe 89 90 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 91 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 92 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 93 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 94 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95 #define ARCH_CAP_SSB_NO BIT(4) /* 96 * Not susceptible to Speculative Store Bypass 97 * attack, so no Speculative Store Bypass 98 * control required. 99 */ 100 #define ARCH_CAP_MDS_NO BIT(5) /* 101 * Not susceptible to 102 * Microarchitectural Data 103 * Sampling (MDS) vulnerabilities. 104 */ 105 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 106 * The processor is not susceptible to a 107 * machine check error due to modifying the 108 * code page size along with either the 109 * physical address or cache type 110 * without TLB invalidation. 111 */ 112 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 113 #define ARCH_CAP_TAA_NO BIT(8) /* 114 * Not susceptible to 115 * TSX Async Abort (TAA) vulnerabilities. 116 */ 117 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 118 * Not susceptible to SBDR and SSDP 119 * variants of Processor MMIO stale data 120 * vulnerabilities. 121 */ 122 #define ARCH_CAP_FBSDP_NO BIT(14) /* 123 * Not susceptible to FBSDP variant of 124 * Processor MMIO stale data 125 * vulnerabilities. 126 */ 127 #define ARCH_CAP_PSDP_NO BIT(15) /* 128 * Not susceptible to PSDP variant of 129 * Processor MMIO stale data 130 * vulnerabilities. 131 */ 132 #define ARCH_CAP_FB_CLEAR BIT(17) /* 133 * VERW clears CPU fill buffer 134 * even on MDS_NO CPUs. 135 */ 136 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 137 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 138 * bit available to control VERW 139 * behavior. 140 */ 141 #define ARCH_CAP_RRSBA BIT(19) /* 142 * Indicates RET may use predictors 143 * other than the RSB. With eIBRS 144 * enabled predictions in kernel mode 145 * are restricted to targets in 146 * kernel. 147 */ 148 #define ARCH_CAP_PBRSB_NO BIT(24) /* 149 * Not susceptible to Post-Barrier 150 * Return Stack Buffer Predictions. 151 */ 152 153 #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 154 * IA32_XAPIC_DISABLE_STATUS MSR 155 * supported 156 */ 157 158 #define MSR_IA32_FLUSH_CMD 0x0000010b 159 #define L1D_FLUSH BIT(0) /* 160 * Writeback and invalidate the 161 * L1 data cache. 162 */ 163 164 #define MSR_IA32_BBL_CR_CTL 0x00000119 165 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 166 167 #define MSR_IA32_TSX_CTRL 0x00000122 168 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 169 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 170 171 #define MSR_IA32_MCU_OPT_CTRL 0x00000123 172 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 173 #define RTM_ALLOW BIT(1) /* TSX development mode */ 174 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 175 176 #define MSR_IA32_SYSENTER_CS 0x00000174 177 #define MSR_IA32_SYSENTER_ESP 0x00000175 178 #define MSR_IA32_SYSENTER_EIP 0x00000176 179 180 #define MSR_IA32_MCG_CAP 0x00000179 181 #define MSR_IA32_MCG_STATUS 0x0000017a 182 #define MSR_IA32_MCG_CTL 0x0000017b 183 #define MSR_ERROR_CONTROL 0x0000017f 184 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 185 186 #define MSR_OFFCORE_RSP_0 0x000001a6 187 #define MSR_OFFCORE_RSP_1 0x000001a7 188 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 189 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 190 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 191 192 #define MSR_LBR_SELECT 0x000001c8 193 #define MSR_LBR_TOS 0x000001c9 194 195 #define MSR_IA32_POWER_CTL 0x000001fc 196 #define MSR_IA32_POWER_CTL_BIT_EE 19 197 198 /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 199 #define MSR_INTEGRITY_CAPS 0x000002d9 200 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 201 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 202 203 #define MSR_LBR_NHM_FROM 0x00000680 204 #define MSR_LBR_NHM_TO 0x000006c0 205 #define MSR_LBR_CORE_FROM 0x00000040 206 #define MSR_LBR_CORE_TO 0x00000060 207 208 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 209 #define LBR_INFO_MISPRED BIT_ULL(63) 210 #define LBR_INFO_IN_TX BIT_ULL(62) 211 #define LBR_INFO_ABORT BIT_ULL(61) 212 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 213 #define LBR_INFO_CYCLES 0xffff 214 #define LBR_INFO_BR_TYPE_OFFSET 56 215 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 216 217 #define MSR_ARCH_LBR_CTL 0x000014ce 218 #define ARCH_LBR_CTL_LBREN BIT(0) 219 #define ARCH_LBR_CTL_CPL_OFFSET 1 220 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 221 #define ARCH_LBR_CTL_STACK_OFFSET 3 222 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 223 #define ARCH_LBR_CTL_FILTER_OFFSET 16 224 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 225 #define MSR_ARCH_LBR_DEPTH 0x000014cf 226 #define MSR_ARCH_LBR_FROM_0 0x00001500 227 #define MSR_ARCH_LBR_TO_0 0x00001600 228 #define MSR_ARCH_LBR_INFO_0 0x00001200 229 230 #define MSR_IA32_PEBS_ENABLE 0x000003f1 231 #define MSR_PEBS_DATA_CFG 0x000003f2 232 #define MSR_IA32_DS_AREA 0x00000600 233 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 234 #define PERF_CAP_METRICS_IDX 15 235 #define PERF_CAP_PT_IDX 16 236 237 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 238 #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 239 #define PERF_CAP_ARCH_REG BIT_ULL(7) 240 #define PERF_CAP_PEBS_FORMAT 0xf00 241 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 242 #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 243 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 244 245 #define MSR_IA32_RTIT_CTL 0x00000570 246 #define RTIT_CTL_TRACEEN BIT(0) 247 #define RTIT_CTL_CYCLEACC BIT(1) 248 #define RTIT_CTL_OS BIT(2) 249 #define RTIT_CTL_USR BIT(3) 250 #define RTIT_CTL_PWR_EVT_EN BIT(4) 251 #define RTIT_CTL_FUP_ON_PTW BIT(5) 252 #define RTIT_CTL_FABRIC_EN BIT(6) 253 #define RTIT_CTL_CR3EN BIT(7) 254 #define RTIT_CTL_TOPA BIT(8) 255 #define RTIT_CTL_MTC_EN BIT(9) 256 #define RTIT_CTL_TSC_EN BIT(10) 257 #define RTIT_CTL_DISRETC BIT(11) 258 #define RTIT_CTL_PTW_EN BIT(12) 259 #define RTIT_CTL_BRANCH_EN BIT(13) 260 #define RTIT_CTL_EVENT_EN BIT(31) 261 #define RTIT_CTL_NOTNT BIT_ULL(55) 262 #define RTIT_CTL_MTC_RANGE_OFFSET 14 263 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 264 #define RTIT_CTL_CYC_THRESH_OFFSET 19 265 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 266 #define RTIT_CTL_PSB_FREQ_OFFSET 24 267 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 268 #define RTIT_CTL_ADDR0_OFFSET 32 269 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 270 #define RTIT_CTL_ADDR1_OFFSET 36 271 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 272 #define RTIT_CTL_ADDR2_OFFSET 40 273 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 274 #define RTIT_CTL_ADDR3_OFFSET 44 275 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 276 #define MSR_IA32_RTIT_STATUS 0x00000571 277 #define RTIT_STATUS_FILTEREN BIT(0) 278 #define RTIT_STATUS_CONTEXTEN BIT(1) 279 #define RTIT_STATUS_TRIGGEREN BIT(2) 280 #define RTIT_STATUS_BUFFOVF BIT(3) 281 #define RTIT_STATUS_ERROR BIT(4) 282 #define RTIT_STATUS_STOPPED BIT(5) 283 #define RTIT_STATUS_BYTECNT_OFFSET 32 284 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 285 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 286 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 287 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 288 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 289 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 290 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 291 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 292 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 293 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 294 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 295 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 296 297 #define MSR_MTRRfix64K_00000 0x00000250 298 #define MSR_MTRRfix16K_80000 0x00000258 299 #define MSR_MTRRfix16K_A0000 0x00000259 300 #define MSR_MTRRfix4K_C0000 0x00000268 301 #define MSR_MTRRfix4K_C8000 0x00000269 302 #define MSR_MTRRfix4K_D0000 0x0000026a 303 #define MSR_MTRRfix4K_D8000 0x0000026b 304 #define MSR_MTRRfix4K_E0000 0x0000026c 305 #define MSR_MTRRfix4K_E8000 0x0000026d 306 #define MSR_MTRRfix4K_F0000 0x0000026e 307 #define MSR_MTRRfix4K_F8000 0x0000026f 308 #define MSR_MTRRdefType 0x000002ff 309 310 #define MSR_IA32_CR_PAT 0x00000277 311 312 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 313 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 314 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 315 #define MSR_IA32_LASTINTFROMIP 0x000001dd 316 #define MSR_IA32_LASTINTTOIP 0x000001de 317 318 #define MSR_IA32_PASID 0x00000d93 319 #define MSR_IA32_PASID_VALID BIT_ULL(31) 320 321 /* DEBUGCTLMSR bits (others vary by model): */ 322 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 323 #define DEBUGCTLMSR_BTF_SHIFT 1 324 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 325 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 326 #define DEBUGCTLMSR_TR (1UL << 6) 327 #define DEBUGCTLMSR_BTS (1UL << 7) 328 #define DEBUGCTLMSR_BTINT (1UL << 8) 329 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 330 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 331 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 332 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 333 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 334 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 335 336 #define MSR_PEBS_FRONTEND 0x000003f7 337 338 #define MSR_IA32_MC0_CTL 0x00000400 339 #define MSR_IA32_MC0_STATUS 0x00000401 340 #define MSR_IA32_MC0_ADDR 0x00000402 341 #define MSR_IA32_MC0_MISC 0x00000403 342 343 /* C-state Residency Counters */ 344 #define MSR_PKG_C3_RESIDENCY 0x000003f8 345 #define MSR_PKG_C6_RESIDENCY 0x000003f9 346 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 347 #define MSR_PKG_C7_RESIDENCY 0x000003fa 348 #define MSR_CORE_C3_RESIDENCY 0x000003fc 349 #define MSR_CORE_C6_RESIDENCY 0x000003fd 350 #define MSR_CORE_C7_RESIDENCY 0x000003fe 351 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 352 #define MSR_PKG_C2_RESIDENCY 0x0000060d 353 #define MSR_PKG_C8_RESIDENCY 0x00000630 354 #define MSR_PKG_C9_RESIDENCY 0x00000631 355 #define MSR_PKG_C10_RESIDENCY 0x00000632 356 357 /* Interrupt Response Limit */ 358 #define MSR_PKGC3_IRTL 0x0000060a 359 #define MSR_PKGC6_IRTL 0x0000060b 360 #define MSR_PKGC7_IRTL 0x0000060c 361 #define MSR_PKGC8_IRTL 0x00000633 362 #define MSR_PKGC9_IRTL 0x00000634 363 #define MSR_PKGC10_IRTL 0x00000635 364 365 /* Run Time Average Power Limiting (RAPL) Interface */ 366 367 #define MSR_VR_CURRENT_CONFIG 0x00000601 368 #define MSR_RAPL_POWER_UNIT 0x00000606 369 370 #define MSR_PKG_POWER_LIMIT 0x00000610 371 #define MSR_PKG_ENERGY_STATUS 0x00000611 372 #define MSR_PKG_PERF_STATUS 0x00000613 373 #define MSR_PKG_POWER_INFO 0x00000614 374 375 #define MSR_DRAM_POWER_LIMIT 0x00000618 376 #define MSR_DRAM_ENERGY_STATUS 0x00000619 377 #define MSR_DRAM_PERF_STATUS 0x0000061b 378 #define MSR_DRAM_POWER_INFO 0x0000061c 379 380 #define MSR_PP0_POWER_LIMIT 0x00000638 381 #define MSR_PP0_ENERGY_STATUS 0x00000639 382 #define MSR_PP0_POLICY 0x0000063a 383 #define MSR_PP0_PERF_STATUS 0x0000063b 384 385 #define MSR_PP1_POWER_LIMIT 0x00000640 386 #define MSR_PP1_ENERGY_STATUS 0x00000641 387 #define MSR_PP1_POLICY 0x00000642 388 389 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 390 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 391 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 392 393 /* Config TDP MSRs */ 394 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 395 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 396 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 397 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 398 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 399 400 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 401 #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 402 403 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 404 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 405 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 406 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 407 408 #define MSR_CORE_C1_RES 0x00000660 409 #define MSR_MODULE_C6_RES_MS 0x00000664 410 411 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 412 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 413 414 #define MSR_ATOM_CORE_RATIOS 0x0000066a 415 #define MSR_ATOM_CORE_VIDS 0x0000066b 416 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 417 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 418 419 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 420 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 421 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 422 423 /* Control-flow Enforcement Technology MSRs */ 424 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 425 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 426 #define CET_SHSTK_EN BIT_ULL(0) 427 #define CET_WRSS_EN BIT_ULL(1) 428 #define CET_ENDBR_EN BIT_ULL(2) 429 #define CET_LEG_IW_EN BIT_ULL(3) 430 #define CET_NO_TRACK_EN BIT_ULL(4) 431 #define CET_SUPPRESS_DISABLE BIT_ULL(5) 432 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 433 #define CET_SUPPRESS BIT_ULL(10) 434 #define CET_WAIT_ENDBR BIT_ULL(11) 435 436 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 437 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 438 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 439 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 440 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 441 442 /* Hardware P state interface */ 443 #define MSR_PPERF 0x0000064e 444 #define MSR_PERF_LIMIT_REASONS 0x0000064f 445 #define MSR_PM_ENABLE 0x00000770 446 #define MSR_HWP_CAPABILITIES 0x00000771 447 #define MSR_HWP_REQUEST_PKG 0x00000772 448 #define MSR_HWP_INTERRUPT 0x00000773 449 #define MSR_HWP_REQUEST 0x00000774 450 #define MSR_HWP_STATUS 0x00000777 451 452 /* CPUID.6.EAX */ 453 #define HWP_BASE_BIT (1<<7) 454 #define HWP_NOTIFICATIONS_BIT (1<<8) 455 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 456 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 457 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 458 459 /* IA32_HWP_CAPABILITIES */ 460 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 461 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 462 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 463 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 464 465 /* IA32_HWP_REQUEST */ 466 #define HWP_MIN_PERF(x) (x & 0xff) 467 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 468 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 469 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 470 #define HWP_EPP_PERFORMANCE 0x00 471 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 472 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 473 #define HWP_EPP_POWERSAVE 0xFF 474 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 475 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 476 477 /* IA32_HWP_STATUS */ 478 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 479 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 480 481 /* IA32_HWP_INTERRUPT */ 482 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 483 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 484 485 #define MSR_AMD64_MC0_MASK 0xc0010044 486 487 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 488 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 489 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 490 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 491 492 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 493 494 /* These are consecutive and not in the normal 4er MCE bank block */ 495 #define MSR_IA32_MC0_CTL2 0x00000280 496 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 497 498 #define MSR_P6_PERFCTR0 0x000000c1 499 #define MSR_P6_PERFCTR1 0x000000c2 500 #define MSR_P6_EVNTSEL0 0x00000186 501 #define MSR_P6_EVNTSEL1 0x00000187 502 503 #define MSR_KNC_PERFCTR0 0x00000020 504 #define MSR_KNC_PERFCTR1 0x00000021 505 #define MSR_KNC_EVNTSEL0 0x00000028 506 #define MSR_KNC_EVNTSEL1 0x00000029 507 508 /* Alternative perfctr range with full access. */ 509 #define MSR_IA32_PMC0 0x000004c1 510 511 /* Auto-reload via MSR instead of DS area */ 512 #define MSR_RELOAD_PMC0 0x000014c1 513 #define MSR_RELOAD_FIXED_CTR0 0x00001309 514 515 /* 516 * AMD64 MSRs. Not complete. See the architecture manual for a more 517 * complete list. 518 */ 519 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 520 #define MSR_AMD64_TSC_RATIO 0xc0000104 521 #define MSR_AMD64_NB_CFG 0xc001001f 522 #define MSR_AMD64_PATCH_LOADER 0xc0010020 523 #define MSR_AMD_PERF_CTL 0xc0010062 524 #define MSR_AMD_PERF_STATUS 0xc0010063 525 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 526 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 527 #define MSR_AMD64_OSVW_STATUS 0xc0010141 528 #define MSR_AMD_PPIN_CTL 0xc00102f0 529 #define MSR_AMD_PPIN 0xc00102f1 530 #define MSR_AMD64_CPUID_FN_1 0xc0011004 531 #define MSR_AMD64_LS_CFG 0xc0011020 532 #define MSR_AMD64_DC_CFG 0xc0011022 533 534 #define MSR_AMD64_DE_CFG 0xc0011029 535 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 536 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 537 538 #define MSR_AMD64_BU_CFG2 0xc001102a 539 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 540 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 541 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 542 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 543 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 544 #define MSR_AMD64_IBSOPCTL 0xc0011033 545 #define MSR_AMD64_IBSOPRIP 0xc0011034 546 #define MSR_AMD64_IBSOPDATA 0xc0011035 547 #define MSR_AMD64_IBSOPDATA2 0xc0011036 548 #define MSR_AMD64_IBSOPDATA3 0xc0011037 549 #define MSR_AMD64_IBSDCLINAD 0xc0011038 550 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 551 #define MSR_AMD64_IBSOP_REG_COUNT 7 552 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 553 #define MSR_AMD64_IBSCTL 0xc001103a 554 #define MSR_AMD64_IBSBRTARGET 0xc001103b 555 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 556 #define MSR_AMD64_IBSOPDATA4 0xc001103d 557 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 558 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 559 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 560 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 561 #define MSR_AMD64_SEV 0xc0010131 562 #define MSR_AMD64_SEV_ENABLED_BIT 0 563 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 564 #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 565 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 566 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 567 #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 568 569 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 570 571 /* AMD Collaborative Processor Performance Control MSRs */ 572 #define MSR_AMD_CPPC_CAP1 0xc00102b0 573 #define MSR_AMD_CPPC_ENABLE 0xc00102b1 574 #define MSR_AMD_CPPC_CAP2 0xc00102b2 575 #define MSR_AMD_CPPC_REQ 0xc00102b3 576 #define MSR_AMD_CPPC_STATUS 0xc00102b4 577 578 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 579 #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 580 #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 581 #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 582 583 #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 584 #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 585 #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 586 #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 587 588 /* AMD Performance Counter Global Status and Control MSRs */ 589 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 590 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 591 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 592 593 /* AMD Last Branch Record MSRs */ 594 #define MSR_AMD64_LBR_SELECT 0xc000010e 595 596 /* Fam 17h MSRs */ 597 #define MSR_F17H_IRPERF 0xc00000e9 598 599 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 600 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 601 602 /* Fam 16h MSRs */ 603 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 604 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 605 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 606 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 607 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 608 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 609 610 /* Fam 15h MSRs */ 611 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 612 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 613 #define MSR_F15H_PERF_CTL 0xc0010200 614 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 615 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 616 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 617 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 618 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 619 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 620 621 #define MSR_F15H_PERF_CTR 0xc0010201 622 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 623 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 624 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 625 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 626 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 627 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 628 629 #define MSR_F15H_NB_PERF_CTL 0xc0010240 630 #define MSR_F15H_NB_PERF_CTR 0xc0010241 631 #define MSR_F15H_PTSC 0xc0010280 632 #define MSR_F15H_IC_CFG 0xc0011021 633 #define MSR_F15H_EX_CFG 0xc001102c 634 635 /* Fam 10h MSRs */ 636 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 637 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 638 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 639 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 640 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 641 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 642 #define MSR_FAM10H_NODE_ID 0xc001100c 643 644 /* K8 MSRs */ 645 #define MSR_K8_TOP_MEM1 0xc001001a 646 #define MSR_K8_TOP_MEM2 0xc001001d 647 #define MSR_AMD64_SYSCFG 0xc0010010 648 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 649 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 650 #define MSR_K8_INT_PENDING_MSG 0xc0010055 651 /* C1E active bits in int pending message */ 652 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 653 #define MSR_K8_TSEG_ADDR 0xc0010112 654 #define MSR_K8_TSEG_MASK 0xc0010113 655 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 656 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 657 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 658 659 /* K7 MSRs */ 660 #define MSR_K7_EVNTSEL0 0xc0010000 661 #define MSR_K7_PERFCTR0 0xc0010004 662 #define MSR_K7_EVNTSEL1 0xc0010001 663 #define MSR_K7_PERFCTR1 0xc0010005 664 #define MSR_K7_EVNTSEL2 0xc0010002 665 #define MSR_K7_PERFCTR2 0xc0010006 666 #define MSR_K7_EVNTSEL3 0xc0010003 667 #define MSR_K7_PERFCTR3 0xc0010007 668 #define MSR_K7_CLK_CTL 0xc001001b 669 #define MSR_K7_HWCR 0xc0010015 670 #define MSR_K7_HWCR_SMMLOCK_BIT 0 671 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 672 #define MSR_K7_HWCR_IRPERF_EN_BIT 30 673 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 674 #define MSR_K7_FID_VID_CTL 0xc0010041 675 #define MSR_K7_FID_VID_STATUS 0xc0010042 676 677 /* K6 MSRs */ 678 #define MSR_K6_WHCR 0xc0000082 679 #define MSR_K6_UWCCR 0xc0000085 680 #define MSR_K6_EPMR 0xc0000086 681 #define MSR_K6_PSOR 0xc0000087 682 #define MSR_K6_PFIR 0xc0000088 683 684 /* Centaur-Hauls/IDT defined MSRs. */ 685 #define MSR_IDT_FCR1 0x00000107 686 #define MSR_IDT_FCR2 0x00000108 687 #define MSR_IDT_FCR3 0x00000109 688 #define MSR_IDT_FCR4 0x0000010a 689 690 #define MSR_IDT_MCR0 0x00000110 691 #define MSR_IDT_MCR1 0x00000111 692 #define MSR_IDT_MCR2 0x00000112 693 #define MSR_IDT_MCR3 0x00000113 694 #define MSR_IDT_MCR4 0x00000114 695 #define MSR_IDT_MCR5 0x00000115 696 #define MSR_IDT_MCR6 0x00000116 697 #define MSR_IDT_MCR7 0x00000117 698 #define MSR_IDT_MCR_CTRL 0x00000120 699 700 /* VIA Cyrix defined MSRs*/ 701 #define MSR_VIA_FCR 0x00001107 702 #define MSR_VIA_LONGHAUL 0x0000110a 703 #define MSR_VIA_RNG 0x0000110b 704 #define MSR_VIA_BCR2 0x00001147 705 706 /* Transmeta defined MSRs */ 707 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 708 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 709 #define MSR_TMTA_LRTI_READOUT 0x80868018 710 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 711 712 /* Intel defined MSRs. */ 713 #define MSR_IA32_P5_MC_ADDR 0x00000000 714 #define MSR_IA32_P5_MC_TYPE 0x00000001 715 #define MSR_IA32_TSC 0x00000010 716 #define MSR_IA32_PLATFORM_ID 0x00000017 717 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 718 #define MSR_EBC_FREQUENCY_ID 0x0000002c 719 #define MSR_SMI_COUNT 0x00000034 720 721 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 722 #define MSR_IA32_FEAT_CTL 0x0000003a 723 #define FEAT_CTL_LOCKED BIT(0) 724 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 725 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 726 #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 727 #define FEAT_CTL_SGX_ENABLED BIT(18) 728 #define FEAT_CTL_LMCE_ENABLED BIT(20) 729 730 #define MSR_IA32_TSC_ADJUST 0x0000003b 731 #define MSR_IA32_BNDCFGS 0x00000d90 732 733 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 734 735 #define MSR_IA32_XFD 0x000001c4 736 #define MSR_IA32_XFD_ERR 0x000001c5 737 #define MSR_IA32_XSS 0x00000da0 738 739 #define MSR_IA32_APICBASE 0x0000001b 740 #define MSR_IA32_APICBASE_BSP (1<<8) 741 #define MSR_IA32_APICBASE_ENABLE (1<<11) 742 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 743 744 #define MSR_IA32_UCODE_WRITE 0x00000079 745 #define MSR_IA32_UCODE_REV 0x0000008b 746 747 /* Intel SGX Launch Enclave Public Key Hash MSRs */ 748 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 749 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 750 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 751 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 752 753 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 754 #define MSR_IA32_SMBASE 0x0000009e 755 756 #define MSR_IA32_PERF_STATUS 0x00000198 757 #define MSR_IA32_PERF_CTL 0x00000199 758 #define INTEL_PERF_CTL_MASK 0xffff 759 760 /* AMD Branch Sampling configuration */ 761 #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 762 #define MSR_AMD_SAMP_BR_FROM 0xc0010300 763 764 #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 765 766 #define MSR_IA32_MPERF 0x000000e7 767 #define MSR_IA32_APERF 0x000000e8 768 769 #define MSR_IA32_THERM_CONTROL 0x0000019a 770 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 771 772 #define THERM_INT_HIGH_ENABLE (1 << 0) 773 #define THERM_INT_LOW_ENABLE (1 << 1) 774 #define THERM_INT_PLN_ENABLE (1 << 24) 775 776 #define MSR_IA32_THERM_STATUS 0x0000019c 777 778 #define THERM_STATUS_PROCHOT (1 << 0) 779 #define THERM_STATUS_POWER_LIMIT (1 << 10) 780 781 #define MSR_THERM2_CTL 0x0000019d 782 783 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 784 785 #define MSR_IA32_MISC_ENABLE 0x000001a0 786 787 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 788 789 #define MSR_MISC_FEATURE_CONTROL 0x000001a4 790 #define MSR_MISC_PWR_MGMT 0x000001aa 791 792 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 793 #define ENERGY_PERF_BIAS_PERFORMANCE 0 794 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 795 #define ENERGY_PERF_BIAS_NORMAL 6 796 #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 797 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 798 #define ENERGY_PERF_BIAS_POWERSAVE 15 799 800 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 801 802 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 803 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 804 #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 805 806 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 807 808 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 809 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 810 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 811 #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 812 813 /* Thermal Thresholds Support */ 814 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 815 #define THERM_SHIFT_THRESHOLD0 8 816 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 817 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 818 #define THERM_SHIFT_THRESHOLD1 16 819 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 820 #define THERM_STATUS_THRESHOLD0 (1 << 6) 821 #define THERM_LOG_THRESHOLD0 (1 << 7) 822 #define THERM_STATUS_THRESHOLD1 (1 << 8) 823 #define THERM_LOG_THRESHOLD1 (1 << 9) 824 825 /* MISC_ENABLE bits: architectural */ 826 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 827 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 828 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 829 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 830 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 831 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 832 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 833 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 834 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 835 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 836 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 837 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 838 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 839 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 840 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 841 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 842 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 843 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 844 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 845 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 846 847 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 848 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 849 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 850 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 851 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 852 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 853 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 854 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 855 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 856 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 857 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 858 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 859 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 860 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 861 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 862 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 863 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 864 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 865 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 866 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 867 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 868 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 869 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 870 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 871 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 872 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 873 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 874 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 875 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 876 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 877 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 878 879 /* MISC_FEATURES_ENABLES non-architectural features */ 880 #define MSR_MISC_FEATURES_ENABLES 0x00000140 881 882 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 883 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 884 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 885 886 #define MSR_IA32_TSC_DEADLINE 0x000006E0 887 888 889 #define MSR_TSX_FORCE_ABORT 0x0000010F 890 891 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 892 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 893 #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 894 #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 895 #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 896 #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 897 898 /* P4/Xeon+ specific */ 899 #define MSR_IA32_MCG_EAX 0x00000180 900 #define MSR_IA32_MCG_EBX 0x00000181 901 #define MSR_IA32_MCG_ECX 0x00000182 902 #define MSR_IA32_MCG_EDX 0x00000183 903 #define MSR_IA32_MCG_ESI 0x00000184 904 #define MSR_IA32_MCG_EDI 0x00000185 905 #define MSR_IA32_MCG_EBP 0x00000186 906 #define MSR_IA32_MCG_ESP 0x00000187 907 #define MSR_IA32_MCG_EFLAGS 0x00000188 908 #define MSR_IA32_MCG_EIP 0x00000189 909 #define MSR_IA32_MCG_RESERVED 0x0000018a 910 911 /* Pentium IV performance counter MSRs */ 912 #define MSR_P4_BPU_PERFCTR0 0x00000300 913 #define MSR_P4_BPU_PERFCTR1 0x00000301 914 #define MSR_P4_BPU_PERFCTR2 0x00000302 915 #define MSR_P4_BPU_PERFCTR3 0x00000303 916 #define MSR_P4_MS_PERFCTR0 0x00000304 917 #define MSR_P4_MS_PERFCTR1 0x00000305 918 #define MSR_P4_MS_PERFCTR2 0x00000306 919 #define MSR_P4_MS_PERFCTR3 0x00000307 920 #define MSR_P4_FLAME_PERFCTR0 0x00000308 921 #define MSR_P4_FLAME_PERFCTR1 0x00000309 922 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 923 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 924 #define MSR_P4_IQ_PERFCTR0 0x0000030c 925 #define MSR_P4_IQ_PERFCTR1 0x0000030d 926 #define MSR_P4_IQ_PERFCTR2 0x0000030e 927 #define MSR_P4_IQ_PERFCTR3 0x0000030f 928 #define MSR_P4_IQ_PERFCTR4 0x00000310 929 #define MSR_P4_IQ_PERFCTR5 0x00000311 930 #define MSR_P4_BPU_CCCR0 0x00000360 931 #define MSR_P4_BPU_CCCR1 0x00000361 932 #define MSR_P4_BPU_CCCR2 0x00000362 933 #define MSR_P4_BPU_CCCR3 0x00000363 934 #define MSR_P4_MS_CCCR0 0x00000364 935 #define MSR_P4_MS_CCCR1 0x00000365 936 #define MSR_P4_MS_CCCR2 0x00000366 937 #define MSR_P4_MS_CCCR3 0x00000367 938 #define MSR_P4_FLAME_CCCR0 0x00000368 939 #define MSR_P4_FLAME_CCCR1 0x00000369 940 #define MSR_P4_FLAME_CCCR2 0x0000036a 941 #define MSR_P4_FLAME_CCCR3 0x0000036b 942 #define MSR_P4_IQ_CCCR0 0x0000036c 943 #define MSR_P4_IQ_CCCR1 0x0000036d 944 #define MSR_P4_IQ_CCCR2 0x0000036e 945 #define MSR_P4_IQ_CCCR3 0x0000036f 946 #define MSR_P4_IQ_CCCR4 0x00000370 947 #define MSR_P4_IQ_CCCR5 0x00000371 948 #define MSR_P4_ALF_ESCR0 0x000003ca 949 #define MSR_P4_ALF_ESCR1 0x000003cb 950 #define MSR_P4_BPU_ESCR0 0x000003b2 951 #define MSR_P4_BPU_ESCR1 0x000003b3 952 #define MSR_P4_BSU_ESCR0 0x000003a0 953 #define MSR_P4_BSU_ESCR1 0x000003a1 954 #define MSR_P4_CRU_ESCR0 0x000003b8 955 #define MSR_P4_CRU_ESCR1 0x000003b9 956 #define MSR_P4_CRU_ESCR2 0x000003cc 957 #define MSR_P4_CRU_ESCR3 0x000003cd 958 #define MSR_P4_CRU_ESCR4 0x000003e0 959 #define MSR_P4_CRU_ESCR5 0x000003e1 960 #define MSR_P4_DAC_ESCR0 0x000003a8 961 #define MSR_P4_DAC_ESCR1 0x000003a9 962 #define MSR_P4_FIRM_ESCR0 0x000003a4 963 #define MSR_P4_FIRM_ESCR1 0x000003a5 964 #define MSR_P4_FLAME_ESCR0 0x000003a6 965 #define MSR_P4_FLAME_ESCR1 0x000003a7 966 #define MSR_P4_FSB_ESCR0 0x000003a2 967 #define MSR_P4_FSB_ESCR1 0x000003a3 968 #define MSR_P4_IQ_ESCR0 0x000003ba 969 #define MSR_P4_IQ_ESCR1 0x000003bb 970 #define MSR_P4_IS_ESCR0 0x000003b4 971 #define MSR_P4_IS_ESCR1 0x000003b5 972 #define MSR_P4_ITLB_ESCR0 0x000003b6 973 #define MSR_P4_ITLB_ESCR1 0x000003b7 974 #define MSR_P4_IX_ESCR0 0x000003c8 975 #define MSR_P4_IX_ESCR1 0x000003c9 976 #define MSR_P4_MOB_ESCR0 0x000003aa 977 #define MSR_P4_MOB_ESCR1 0x000003ab 978 #define MSR_P4_MS_ESCR0 0x000003c0 979 #define MSR_P4_MS_ESCR1 0x000003c1 980 #define MSR_P4_PMH_ESCR0 0x000003ac 981 #define MSR_P4_PMH_ESCR1 0x000003ad 982 #define MSR_P4_RAT_ESCR0 0x000003bc 983 #define MSR_P4_RAT_ESCR1 0x000003bd 984 #define MSR_P4_SAAT_ESCR0 0x000003ae 985 #define MSR_P4_SAAT_ESCR1 0x000003af 986 #define MSR_P4_SSU_ESCR0 0x000003be 987 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 988 989 #define MSR_P4_TBPU_ESCR0 0x000003c2 990 #define MSR_P4_TBPU_ESCR1 0x000003c3 991 #define MSR_P4_TC_ESCR0 0x000003c4 992 #define MSR_P4_TC_ESCR1 0x000003c5 993 #define MSR_P4_U2L_ESCR0 0x000003b0 994 #define MSR_P4_U2L_ESCR1 0x000003b1 995 996 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 997 998 /* Intel Core-based CPU performance counters */ 999 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1000 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1001 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 1002 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1003 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1004 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1005 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1006 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1007 1008 #define MSR_PERF_METRICS 0x00000329 1009 1010 /* PERF_GLOBAL_OVF_CTL bits */ 1011 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 1012 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1013 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1014 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1015 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1016 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 1017 1018 /* Geode defined MSRs */ 1019 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1020 1021 /* Intel VT MSRs */ 1022 #define MSR_IA32_VMX_BASIC 0x00000480 1023 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1024 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1025 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1026 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1027 #define MSR_IA32_VMX_MISC 0x00000485 1028 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1029 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1030 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1031 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1032 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1033 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1034 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1035 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1036 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1037 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1038 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1039 #define MSR_IA32_VMX_VMFUNC 0x00000491 1040 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1041 1042 /* VMX_BASIC bits and bitmasks */ 1043 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1044 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1045 #define VMX_BASIC_64 0x0001000000000000LLU 1046 #define VMX_BASIC_MEM_TYPE_SHIFT 50 1047 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1048 #define VMX_BASIC_MEM_TYPE_WB 6LLU 1049 #define VMX_BASIC_INOUT 0x0040000000000000LLU 1050 1051 /* Resctrl MSRs: */ 1052 /* - Intel: */ 1053 #define MSR_IA32_L3_QOS_CFG 0xc81 1054 #define MSR_IA32_L2_QOS_CFG 0xc82 1055 #define MSR_IA32_QM_EVTSEL 0xc8d 1056 #define MSR_IA32_QM_CTR 0xc8e 1057 #define MSR_IA32_PQR_ASSOC 0xc8f 1058 #define MSR_IA32_L3_CBM_BASE 0xc90 1059 #define MSR_IA32_L2_CBM_BASE 0xd10 1060 #define MSR_IA32_MBA_THRTL_BASE 0xd50 1061 1062 /* - AMD: */ 1063 #define MSR_IA32_MBA_BW_BASE 0xc0000200 1064 1065 /* MSR_IA32_VMX_MISC bits */ 1066 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1067 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1068 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1069 /* AMD-V MSRs */ 1070 1071 #define MSR_VM_CR 0xc0010114 1072 #define MSR_VM_IGNNE 0xc0010115 1073 #define MSR_VM_HSAVE_PA 0xc0010117 1074 1075 /* Hardware Feedback Interface */ 1076 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 1077 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 1078 1079 /* x2APIC locked status */ 1080 #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1081 #define LEGACY_XAPIC_DISABLED BIT(0) /* 1082 * x2APIC mode is locked and 1083 * disabling x2APIC will cause 1084 * a #GP 1085 */ 1086 1087 #endif /* _ASM_X86_MSR_INDEX_H */ 1088