1444e2ff3SArnaldo Carvalho de Melo /* SPDX-License-Identifier: GPL-2.0 */ 2444e2ff3SArnaldo Carvalho de Melo #ifndef _ASM_X86_MSR_INDEX_H 3444e2ff3SArnaldo Carvalho de Melo #define _ASM_X86_MSR_INDEX_H 4444e2ff3SArnaldo Carvalho de Melo 5444e2ff3SArnaldo Carvalho de Melo #include <linux/bits.h> 6444e2ff3SArnaldo Carvalho de Melo 7444e2ff3SArnaldo Carvalho de Melo /* 8444e2ff3SArnaldo Carvalho de Melo * CPU model specific register (MSR) numbers. 9444e2ff3SArnaldo Carvalho de Melo * 10444e2ff3SArnaldo Carvalho de Melo * Do not add new entries to this file unless the definitions are shared 11444e2ff3SArnaldo Carvalho de Melo * between multiple compilation units. 12444e2ff3SArnaldo Carvalho de Melo */ 13444e2ff3SArnaldo Carvalho de Melo 14444e2ff3SArnaldo Carvalho de Melo /* x86-64 specific MSRs */ 15444e2ff3SArnaldo Carvalho de Melo #define MSR_EFER 0xc0000080 /* extended feature register */ 16444e2ff3SArnaldo Carvalho de Melo #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17444e2ff3SArnaldo Carvalho de Melo #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18444e2ff3SArnaldo Carvalho de Melo #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19444e2ff3SArnaldo Carvalho de Melo #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20444e2ff3SArnaldo Carvalho de Melo #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21444e2ff3SArnaldo Carvalho de Melo #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22444e2ff3SArnaldo Carvalho de Melo #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23444e2ff3SArnaldo Carvalho de Melo #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24444e2ff3SArnaldo Carvalho de Melo 25444e2ff3SArnaldo Carvalho de Melo /* EFER bits: */ 26444e2ff3SArnaldo Carvalho de Melo #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27444e2ff3SArnaldo Carvalho de Melo #define _EFER_LME 8 /* Long mode enable */ 28444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMA 10 /* Long mode active (read-only) */ 29444e2ff3SArnaldo Carvalho de Melo #define _EFER_NX 11 /* No execute enable */ 30444e2ff3SArnaldo Carvalho de Melo #define _EFER_SVME 12 /* Enable virtualization */ 31444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32444e2ff3SArnaldo Carvalho de Melo #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33444e2ff3SArnaldo Carvalho de Melo 34444e2ff3SArnaldo Carvalho de Melo #define EFER_SCE (1<<_EFER_SCE) 35444e2ff3SArnaldo Carvalho de Melo #define EFER_LME (1<<_EFER_LME) 36444e2ff3SArnaldo Carvalho de Melo #define EFER_LMA (1<<_EFER_LMA) 37444e2ff3SArnaldo Carvalho de Melo #define EFER_NX (1<<_EFER_NX) 38444e2ff3SArnaldo Carvalho de Melo #define EFER_SVME (1<<_EFER_SVME) 39444e2ff3SArnaldo Carvalho de Melo #define EFER_LMSLE (1<<_EFER_LMSLE) 40444e2ff3SArnaldo Carvalho de Melo #define EFER_FFXSR (1<<_EFER_FFXSR) 41444e2ff3SArnaldo Carvalho de Melo 42444e2ff3SArnaldo Carvalho de Melo /* Intel MSRs. Some also available on other CPUs */ 43444e2ff3SArnaldo Carvalho de Melo 44bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL 0x00000033 45bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47bab1a501SArnaldo Carvalho de Melo 48444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54444e2ff3SArnaldo Carvalho de Melo 55444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56444e2ff3SArnaldo Carvalho de Melo #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 57444e2ff3SArnaldo Carvalho de Melo 58444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN_CTL 0x0000004e 59444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN 0x0000004f 60444e2ff3SArnaldo Carvalho de Melo 61444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR0 0x000000c1 62444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR1 0x000000c2 63444e2ff3SArnaldo Carvalho de Melo #define MSR_FSB_FREQ 0x000000cd 64444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO 0x000000ce 65444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 66444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67444e2ff3SArnaldo Carvalho de Melo 68444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL 0xe1 69444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71444e2ff3SArnaldo Carvalho de Melo /* 72444e2ff3SArnaldo Carvalho de Melo * The time field is bit[31:2], but representing a 32bit value with 73444e2ff3SArnaldo Carvalho de Melo * bit[1:0] zero. 74444e2ff3SArnaldo Carvalho de Melo */ 75444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76444e2ff3SArnaldo Carvalho de Melo 77bab1a501SArnaldo Carvalho de Melo /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 78bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS 0x000000cf 79bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 80bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 81bab1a501SArnaldo Carvalho de Melo 82444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 83444e2ff3SArnaldo Carvalho de Melo #define NHM_C3_AUTO_DEMOTE (1UL << 25) 84444e2ff3SArnaldo Carvalho de Melo #define NHM_C1_AUTO_DEMOTE (1UL << 26) 85444e2ff3SArnaldo Carvalho de Melo #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 86444e2ff3SArnaldo Carvalho de Melo #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 87444e2ff3SArnaldo Carvalho de Melo #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 88444e2ff3SArnaldo Carvalho de Melo 89444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRcap 0x000000fe 90444e2ff3SArnaldo Carvalho de Melo 91444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 92444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 93444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 94444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SSB_NO BIT(4) /* 96444e2ff3SArnaldo Carvalho de Melo * Not susceptible to Speculative Store Bypass 97444e2ff3SArnaldo Carvalho de Melo * attack, so no Speculative Store Bypass 98444e2ff3SArnaldo Carvalho de Melo * control required. 99444e2ff3SArnaldo Carvalho de Melo */ 100444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_MDS_NO BIT(5) /* 101444e2ff3SArnaldo Carvalho de Melo * Not susceptible to 102444e2ff3SArnaldo Carvalho de Melo * Microarchitectural Data 103444e2ff3SArnaldo Carvalho de Melo * Sampling (MDS) vulnerabilities. 104444e2ff3SArnaldo Carvalho de Melo */ 1058122b047SArnaldo Carvalho de Melo #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 1068122b047SArnaldo Carvalho de Melo * The processor is not susceptible to a 1078122b047SArnaldo Carvalho de Melo * machine check error due to modifying the 1088122b047SArnaldo Carvalho de Melo * code page size along with either the 1098122b047SArnaldo Carvalho de Melo * physical address or cache type 1108122b047SArnaldo Carvalho de Melo * without TLB invalidation. 1118122b047SArnaldo Carvalho de Melo */ 1128122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1138122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TAA_NO BIT(8) /* 1148122b047SArnaldo Carvalho de Melo * Not susceptible to 1158122b047SArnaldo Carvalho de Melo * TSX Async Abort (TAA) vulnerabilities. 1168122b047SArnaldo Carvalho de Melo */ 117444e2ff3SArnaldo Carvalho de Melo 118444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_FLUSH_CMD 0x0000010b 119444e2ff3SArnaldo Carvalho de Melo #define L1D_FLUSH BIT(0) /* 120444e2ff3SArnaldo Carvalho de Melo * Writeback and invalidate the 121444e2ff3SArnaldo Carvalho de Melo * L1 data cache. 122444e2ff3SArnaldo Carvalho de Melo */ 123444e2ff3SArnaldo Carvalho de Melo 124444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL 0x00000119 125444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL3 0x0000011e 126444e2ff3SArnaldo Carvalho de Melo 1278122b047SArnaldo Carvalho de Melo #define MSR_IA32_TSX_CTRL 0x00000122 1288122b047SArnaldo Carvalho de Melo #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 1298122b047SArnaldo Carvalho de Melo #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 1308122b047SArnaldo Carvalho de Melo 13125ca7e5cSArnaldo Carvalho de Melo /* SRBDS support */ 13225ca7e5cSArnaldo Carvalho de Melo #define MSR_IA32_MCU_OPT_CTRL 0x00000123 13325ca7e5cSArnaldo Carvalho de Melo #define RNGDS_MITG_DIS BIT(0) 13425ca7e5cSArnaldo Carvalho de Melo 135444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_CS 0x00000174 136444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_ESP 0x00000175 137444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_EIP 0x00000176 138444e2ff3SArnaldo Carvalho de Melo 139444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CAP 0x00000179 140444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_STATUS 0x0000017a 141444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CTL 0x0000017b 142e9bde94fSArnaldo Carvalho de Melo #define MSR_ERROR_CONTROL 0x0000017f 143444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EXT_CTL 0x000004d0 144444e2ff3SArnaldo Carvalho de Melo 145444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_0 0x000001a6 146444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_1 0x000001a7 147444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT 0x000001ad 148444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 149444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT2 0x000001af 150444e2ff3SArnaldo Carvalho de Melo 151444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_SELECT 0x000001c8 152444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_TOS 0x000001c9 153f815fe51SArnaldo Carvalho de Melo 154f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL 0x000001fc 155f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL_BIT_EE 19 156f815fe51SArnaldo Carvalho de Melo 157444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_FROM 0x00000680 158444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_TO 0x000006c0 159444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_FROM 0x00000040 160444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_TO 0x00000060 161444e2ff3SArnaldo Carvalho de Melo 162444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 163444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_MISPRED BIT_ULL(63) 164444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_IN_TX BIT_ULL(62) 165444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_ABORT BIT_ULL(61) 166f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 167444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_CYCLES 0xffff 168f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE_OFFSET 56 169f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 170f815fe51SArnaldo Carvalho de Melo 171f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_CTL 0x000014ce 172f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_LBREN BIT(0) 173f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL_OFFSET 1 174f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 175f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK_OFFSET 3 176f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 177f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER_OFFSET 16 178f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 179f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_DEPTH 0x000014cf 180f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_FROM_0 0x00001500 181f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_TO_0 0x00001600 182f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_INFO_0 0x00001200 183444e2ff3SArnaldo Carvalho de Melo 184444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PEBS_ENABLE 0x000003f1 185444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_DATA_CFG 0x000003f2 186444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DS_AREA 0x00000600 187444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CAPABILITIES 0x00000345 188b3172585SArnaldo Carvalho de Melo #define PERF_CAP_METRICS_IDX 15 189b3172585SArnaldo Carvalho de Melo #define PERF_CAP_PT_IDX 16 190b3172585SArnaldo Carvalho de Melo 191444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 192444e2ff3SArnaldo Carvalho de Melo 193444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CTL 0x00000570 194444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TRACEEN BIT(0) 195444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYCLEACC BIT(1) 196444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_OS BIT(2) 197444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_USR BIT(3) 198444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PWR_EVT_EN BIT(4) 199444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FUP_ON_PTW BIT(5) 200444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FABRIC_EN BIT(6) 201444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CR3EN BIT(7) 202444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TOPA BIT(8) 203444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_EN BIT(9) 204444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TSC_EN BIT(10) 205444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_DISRETC BIT(11) 206444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PTW_EN BIT(12) 207444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_BRANCH_EN BIT(13) 208444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE_OFFSET 14 209444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 210444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH_OFFSET 19 211444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 212444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ_OFFSET 24 213444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 214444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0_OFFSET 32 215444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 216444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1_OFFSET 36 217444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 218444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2_OFFSET 40 219444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 220444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3_OFFSET 44 221444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 222444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_STATUS 0x00000571 223444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_FILTEREN BIT(0) 224444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_CONTEXTEN BIT(1) 225444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_TRIGGEREN BIT(2) 226444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BUFFOVF BIT(3) 227444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_ERROR BIT(4) 228444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_STOPPED BIT(5) 229444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT_OFFSET 32 230444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 231444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_A 0x00000580 232444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_B 0x00000581 233444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_A 0x00000582 234444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_B 0x00000583 235444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_A 0x00000584 236444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_B 0x00000585 237444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_A 0x00000586 238444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_B 0x00000587 239444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 240444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 241444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 242444e2ff3SArnaldo Carvalho de Melo 243444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix64K_00000 0x00000250 244444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_80000 0x00000258 245444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_A0000 0x00000259 246444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C0000 0x00000268 247444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C8000 0x00000269 248444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D0000 0x0000026a 249444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D8000 0x0000026b 250444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E0000 0x0000026c 251444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E8000 0x0000026d 252444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F0000 0x0000026e 253444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F8000 0x0000026f 254444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRdefType 0x000002ff 255444e2ff3SArnaldo Carvalho de Melo 256444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_CR_PAT 0x00000277 257444e2ff3SArnaldo Carvalho de Melo 258444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DEBUGCTLMSR 0x000001d9 259444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 260444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 261444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTFROMIP 0x000001dd 262444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTTOIP 0x000001de 263444e2ff3SArnaldo Carvalho de Melo 26432b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID 0x00000d93 26532b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID_VALID BIT_ULL(31) 26632b734e0SArnaldo Carvalho de Melo 267444e2ff3SArnaldo Carvalho de Melo /* DEBUGCTLMSR bits (others vary by model): */ 268444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 269444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF_SHIFT 1 270444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 271b3172585SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 272444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_TR (1UL << 6) 273444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS (1UL << 7) 274444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTINT (1UL << 8) 275444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 276444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 277444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 278444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 279444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 280444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 281444e2ff3SArnaldo Carvalho de Melo 282444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_FRONTEND 0x000003f7 283444e2ff3SArnaldo Carvalho de Melo 284444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL 0x00000400 285444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_STATUS 0x00000401 286444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_ADDR 0x00000402 287444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_MISC 0x00000403 288444e2ff3SArnaldo Carvalho de Melo 289444e2ff3SArnaldo Carvalho de Melo /* C-state Residency Counters */ 290444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C3_RESIDENCY 0x000003f8 291444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C6_RESIDENCY 0x000003f9 292444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 293444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C7_RESIDENCY 0x000003fa 294444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C3_RESIDENCY 0x000003fc 295444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C6_RESIDENCY 0x000003fd 296444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C7_RESIDENCY 0x000003fe 297444e2ff3SArnaldo Carvalho de Melo #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 298444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C2_RESIDENCY 0x0000060d 299444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C8_RESIDENCY 0x00000630 300444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C9_RESIDENCY 0x00000631 301444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C10_RESIDENCY 0x00000632 302444e2ff3SArnaldo Carvalho de Melo 303444e2ff3SArnaldo Carvalho de Melo /* Interrupt Response Limit */ 304444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC3_IRTL 0x0000060a 305444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC6_IRTL 0x0000060b 306444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC7_IRTL 0x0000060c 307444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC8_IRTL 0x00000633 308444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC9_IRTL 0x00000634 309444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC10_IRTL 0x00000635 310444e2ff3SArnaldo Carvalho de Melo 311444e2ff3SArnaldo Carvalho de Melo /* Run Time Average Power Limiting (RAPL) Interface */ 312444e2ff3SArnaldo Carvalho de Melo 313444e2ff3SArnaldo Carvalho de Melo #define MSR_RAPL_POWER_UNIT 0x00000606 314444e2ff3SArnaldo Carvalho de Melo 315444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_LIMIT 0x00000610 316444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ENERGY_STATUS 0x00000611 317444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_PERF_STATUS 0x00000613 318444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_INFO 0x00000614 319444e2ff3SArnaldo Carvalho de Melo 320444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_LIMIT 0x00000618 321444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_ENERGY_STATUS 0x00000619 322444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_PERF_STATUS 0x0000061b 323444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_INFO 0x0000061c 324444e2ff3SArnaldo Carvalho de Melo 325444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POWER_LIMIT 0x00000638 326444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_ENERGY_STATUS 0x00000639 327444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POLICY 0x0000063a 328444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_PERF_STATUS 0x0000063b 329444e2ff3SArnaldo Carvalho de Melo 330444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POWER_LIMIT 0x00000640 331444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_ENERGY_STATUS 0x00000641 332444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POLICY 0x00000642 333444e2ff3SArnaldo Carvalho de Melo 3343b1f47d6SArnaldo Carvalho de Melo #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 335e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 336e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 3373b1f47d6SArnaldo Carvalho de Melo 338444e2ff3SArnaldo Carvalho de Melo /* Config TDP MSRs */ 339444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_NOMINAL 0x00000648 340444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 341444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 342444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_CONTROL 0x0000064B 343444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 344444e2ff3SArnaldo Carvalho de Melo 345444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 346444e2ff3SArnaldo Carvalho de Melo 347444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 348444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 349444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 350444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 351444e2ff3SArnaldo Carvalho de Melo 352444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C1_RES 0x00000660 353444e2ff3SArnaldo Carvalho de Melo #define MSR_MODULE_C6_RES_MS 0x00000664 354444e2ff3SArnaldo Carvalho de Melo 355444e2ff3SArnaldo Carvalho de Melo #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 356444e2ff3SArnaldo Carvalho de Melo #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 357444e2ff3SArnaldo Carvalho de Melo 358444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_RATIOS 0x0000066a 359444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_VIDS 0x0000066b 360444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 361444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 362444e2ff3SArnaldo Carvalho de Melo 363444e2ff3SArnaldo Carvalho de Melo 364444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 365444e2ff3SArnaldo Carvalho de Melo #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 366444e2ff3SArnaldo Carvalho de Melo #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 367444e2ff3SArnaldo Carvalho de Melo 368444e2ff3SArnaldo Carvalho de Melo /* Hardware P state interface */ 369444e2ff3SArnaldo Carvalho de Melo #define MSR_PPERF 0x0000064e 370444e2ff3SArnaldo Carvalho de Melo #define MSR_PERF_LIMIT_REASONS 0x0000064f 371444e2ff3SArnaldo Carvalho de Melo #define MSR_PM_ENABLE 0x00000770 372444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_CAPABILITIES 0x00000771 373444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST_PKG 0x00000772 374444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_INTERRUPT 0x00000773 375444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST 0x00000774 376444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_STATUS 0x00000777 377444e2ff3SArnaldo Carvalho de Melo 378444e2ff3SArnaldo Carvalho de Melo /* CPUID.6.EAX */ 379444e2ff3SArnaldo Carvalho de Melo #define HWP_BASE_BIT (1<<7) 380444e2ff3SArnaldo Carvalho de Melo #define HWP_NOTIFICATIONS_BIT (1<<8) 381444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 382444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 383444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 384444e2ff3SArnaldo Carvalho de Melo 385444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_CAPABILITIES */ 386444e2ff3SArnaldo Carvalho de Melo #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 387444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 388444e2ff3SArnaldo Carvalho de Melo #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 389444e2ff3SArnaldo Carvalho de Melo #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 390444e2ff3SArnaldo Carvalho de Melo 391444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_REQUEST */ 392444e2ff3SArnaldo Carvalho de Melo #define HWP_MIN_PERF(x) (x & 0xff) 393444e2ff3SArnaldo Carvalho de Melo #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 394444e2ff3SArnaldo Carvalho de Melo #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 395444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 396444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_PERFORMANCE 0x00 397444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_PERFORMANCE 0x80 398444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_POWERSAVE 0xC0 399444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_POWERSAVE 0xFF 400444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 401444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 402444e2ff3SArnaldo Carvalho de Melo 403444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_STATUS */ 404444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 405444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 406444e2ff3SArnaldo Carvalho de Melo 407444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_INTERRUPT */ 408444e2ff3SArnaldo Carvalho de Melo #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 409444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 410444e2ff3SArnaldo Carvalho de Melo 411444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MC0_MASK 0xc0010044 412444e2ff3SArnaldo Carvalho de Melo 413444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 414444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 415444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 416444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 417444e2ff3SArnaldo Carvalho de Melo 418444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 419444e2ff3SArnaldo Carvalho de Melo 420444e2ff3SArnaldo Carvalho de Melo /* These are consecutive and not in the normal 4er MCE bank block */ 421444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL2 0x00000280 422444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 423444e2ff3SArnaldo Carvalho de Melo 424444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR0 0x000000c1 425444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR1 0x000000c2 426444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL0 0x00000186 427444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL1 0x00000187 428444e2ff3SArnaldo Carvalho de Melo 429444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR0 0x00000020 430444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR1 0x00000021 431444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL0 0x00000028 432444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL1 0x00000029 433444e2ff3SArnaldo Carvalho de Melo 434444e2ff3SArnaldo Carvalho de Melo /* Alternative perfctr range with full access. */ 435444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PMC0 0x000004c1 436444e2ff3SArnaldo Carvalho de Melo 437444e2ff3SArnaldo Carvalho de Melo /* Auto-reload via MSR instead of DS area */ 438444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_PMC0 0x000014c1 439444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_FIXED_CTR0 0x00001309 440444e2ff3SArnaldo Carvalho de Melo 441444e2ff3SArnaldo Carvalho de Melo /* 442444e2ff3SArnaldo Carvalho de Melo * AMD64 MSRs. Not complete. See the architecture manual for a more 443444e2ff3SArnaldo Carvalho de Melo * complete list. 444444e2ff3SArnaldo Carvalho de Melo */ 445444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LEVEL 0x0000008b 446444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_TSC_RATIO 0xc0000104 447444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_NB_CFG 0xc001001f 448444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LOADER 0xc0010020 449444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_CTL 0xc0010062 450444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_STATUS 0xc0010063 451444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 452444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 453444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_STATUS 0xc0010141 4548122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN_CTL 0xc00102f0 4558122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN 0xc00102f1 456f815fe51SArnaldo Carvalho de Melo #define MSR_AMD64_CPUID_FN_1 0xc0011004 457444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_LS_CFG 0xc0011020 458444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_DC_CFG 0xc0011022 459444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_BU_CFG2 0xc001102a 460444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHCTL 0xc0011030 461444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 462444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 463444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_COUNT 3 464444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 465444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPCTL 0xc0011033 466444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPRIP 0xc0011034 467444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA 0xc0011035 468444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA2 0xc0011036 469444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA3 0xc0011037 470444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCLINAD 0xc0011038 471444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 472444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_COUNT 7 473444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 474444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSCTL 0xc001103a 475444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSBRTARGET 0xc001103b 47632b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 477444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA4 0xc001103d 478444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 4795b061a32SArnaldo Carvalho de Melo #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 480fde66824SArnaldo Carvalho de Melo #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 48132b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 482444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV 0xc0010131 483444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED_BIT 0 48432b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 485444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 48632b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 487444e2ff3SArnaldo Carvalho de Melo 488444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 489444e2ff3SArnaldo Carvalho de Melo 490e652ab64SArnaldo Carvalho de Melo /* AMD Collaborative Processor Performance Control MSRs */ 491e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP1 0xc00102b0 492e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_ENABLE 0xc00102b1 493e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP2 0xc00102b2 494e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_REQ 0xc00102b3 495e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_STATUS 0xc00102b4 496e652ab64SArnaldo Carvalho de Melo 497e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 498e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 499e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 500e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 501e652ab64SArnaldo Carvalho de Melo 502e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 503e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 504e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 505e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 506e652ab64SArnaldo Carvalho de Melo 507444e2ff3SArnaldo Carvalho de Melo /* Fam 17h MSRs */ 508444e2ff3SArnaldo Carvalho de Melo #define MSR_F17H_IRPERF 0xc00000e9 509444e2ff3SArnaldo Carvalho de Melo 510444e2ff3SArnaldo Carvalho de Melo /* Fam 16h MSRs */ 511444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTL 0xc0010230 512444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTR 0xc0010231 513444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 514444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 515444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 516444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 517444e2ff3SArnaldo Carvalho de Melo 518444e2ff3SArnaldo Carvalho de Melo /* Fam 15h MSRs */ 519f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 520f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 521444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL 0xc0010200 522444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 523444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 524444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 525444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 526444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 527444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 528444e2ff3SArnaldo Carvalho de Melo 529444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR 0xc0010201 530444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 531444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 532444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 533444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 534444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 535444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 536444e2ff3SArnaldo Carvalho de Melo 537444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTL 0xc0010240 538444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTR 0xc0010241 539444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PTSC 0xc0010280 540444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_IC_CFG 0xc0011021 541444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_EX_CFG 0xc001102c 542444e2ff3SArnaldo Carvalho de Melo 543444e2ff3SArnaldo Carvalho de Melo /* Fam 10h MSRs */ 544444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 545444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_ENABLE (1<<0) 546444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 547444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 548444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 549444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_SHIFT 20 550444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_NODE_ID 0xc001100c 551444e2ff3SArnaldo Carvalho de Melo #define MSR_F10H_DECFG 0xc0011029 552444e2ff3SArnaldo Carvalho de Melo #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 553444e2ff3SArnaldo Carvalho de Melo #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 554444e2ff3SArnaldo Carvalho de Melo 555444e2ff3SArnaldo Carvalho de Melo /* K8 MSRs */ 556444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM1 0xc001001a 557444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM2 0xc001001d 558059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 559059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 560059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 561444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_INT_PENDING_MSG 0xc0010055 562444e2ff3SArnaldo Carvalho de Melo /* C1E active bits in int pending message */ 563444e2ff3SArnaldo Carvalho de Melo #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 564444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_ADDR 0xc0010112 565444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_MASK 0xc0010113 566444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 567444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 568444e2ff3SArnaldo Carvalho de Melo #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 569444e2ff3SArnaldo Carvalho de Melo 570444e2ff3SArnaldo Carvalho de Melo /* K7 MSRs */ 571444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL0 0xc0010000 572444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR0 0xc0010004 573444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL1 0xc0010001 574444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR1 0xc0010005 575444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL2 0xc0010002 576444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR2 0xc0010006 577444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL3 0xc0010003 578444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR3 0xc0010007 579444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_CLK_CTL 0xc001001b 580444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR 0xc0010015 581444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK_BIT 0 582444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 583d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN_BIT 30 584d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 585444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_CTL 0xc0010041 586444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_STATUS 0xc0010042 587444e2ff3SArnaldo Carvalho de Melo 588444e2ff3SArnaldo Carvalho de Melo /* K6 MSRs */ 589444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_WHCR 0xc0000082 590444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_UWCCR 0xc0000085 591444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_EPMR 0xc0000086 592444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PSOR 0xc0000087 593444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PFIR 0xc0000088 594444e2ff3SArnaldo Carvalho de Melo 595444e2ff3SArnaldo Carvalho de Melo /* Centaur-Hauls/IDT defined MSRs. */ 596444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR1 0x00000107 597444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR2 0x00000108 598444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR3 0x00000109 599444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR4 0x0000010a 600444e2ff3SArnaldo Carvalho de Melo 601444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR0 0x00000110 602444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR1 0x00000111 603444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR2 0x00000112 604444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR3 0x00000113 605444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR4 0x00000114 606444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR5 0x00000115 607444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR6 0x00000116 608444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR7 0x00000117 609444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR_CTRL 0x00000120 610444e2ff3SArnaldo Carvalho de Melo 611444e2ff3SArnaldo Carvalho de Melo /* VIA Cyrix defined MSRs*/ 612444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_FCR 0x00001107 613444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_LONGHAUL 0x0000110a 614444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_RNG 0x0000110b 615444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_BCR2 0x00001147 616444e2ff3SArnaldo Carvalho de Melo 617444e2ff3SArnaldo Carvalho de Melo /* Transmeta defined MSRs */ 618444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_CTRL 0x80868010 619444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 620444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_READOUT 0x80868018 621444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 622444e2ff3SArnaldo Carvalho de Melo 623444e2ff3SArnaldo Carvalho de Melo /* Intel defined MSRs. */ 624444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_ADDR 0x00000000 625444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_TYPE 0x00000001 626444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC 0x00000010 627444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PLATFORM_ID 0x00000017 628444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_EBL_CR_POWERON 0x0000002a 629444e2ff3SArnaldo Carvalho de Melo #define MSR_EBC_FREQUENCY_ID 0x0000002c 630444e2ff3SArnaldo Carvalho de Melo #define MSR_SMI_COUNT 0x00000034 631f6505c88SSean Christopherson 632f6505c88SSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 633f6505c88SSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 634f6505c88SSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 635f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 636f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 637e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 638e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_ENABLED BIT(18) 639f6505c88SSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 640f6505c88SSean Christopherson 641444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_ADJUST 0x0000003b 642444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS 0x00000d90 643444e2ff3SArnaldo Carvalho de Melo 644444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 645444e2ff3SArnaldo Carvalho de Melo 6463442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD 0x000001c4 6473442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD_ERR 0x000001c5 648444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_XSS 0x00000da0 649444e2ff3SArnaldo Carvalho de Melo 650444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE 0x0000001b 651444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BSP (1<<8) 652444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_ENABLE (1<<11) 653444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 654444e2ff3SArnaldo Carvalho de Melo 655444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_WRITE 0x00000079 656444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_REV 0x0000008b 657444e2ff3SArnaldo Carvalho de Melo 658e9bde94fSArnaldo Carvalho de Melo /* Intel SGX Launch Enclave Public Key Hash MSRs */ 659e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 660e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 661e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 662e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 663e9bde94fSArnaldo Carvalho de Melo 664444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 665444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMBASE 0x0000009e 666444e2ff3SArnaldo Carvalho de Melo 667444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_STATUS 0x00000198 668444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CTL 0x00000199 669444e2ff3SArnaldo Carvalho de Melo #define INTEL_PERF_CTL_MASK 0xffff 670444e2ff3SArnaldo Carvalho de Melo 671444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MPERF 0x000000e7 672444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APERF 0x000000e8 673444e2ff3SArnaldo Carvalho de Melo 674444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_CONTROL 0x0000019a 675444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_INTERRUPT 0x0000019b 676444e2ff3SArnaldo Carvalho de Melo 677444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_HIGH_ENABLE (1 << 0) 678444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_LOW_ENABLE (1 << 1) 679444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_PLN_ENABLE (1 << 24) 680444e2ff3SArnaldo Carvalho de Melo 681444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_STATUS 0x0000019c 682444e2ff3SArnaldo Carvalho de Melo 683444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_PROCHOT (1 << 0) 684444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_POWER_LIMIT (1 << 10) 685444e2ff3SArnaldo Carvalho de Melo 686444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL 0x0000019d 687444e2ff3SArnaldo Carvalho de Melo 688444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 689444e2ff3SArnaldo Carvalho de Melo 690444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE 0x000001a0 691444e2ff3SArnaldo Carvalho de Melo 692444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 693444e2ff3SArnaldo Carvalho de Melo 694444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURE_CONTROL 0x000001a4 695444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_PWR_MGMT 0x000001aa 696444e2ff3SArnaldo Carvalho de Melo 697444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 698444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_PERFORMANCE 0 699444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 700444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_NORMAL 6 701444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 702444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_POWERSAVE 15 703444e2ff3SArnaldo Carvalho de Melo 704444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 705444e2ff3SArnaldo Carvalho de Melo 706444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 707444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 708*61726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 709444e2ff3SArnaldo Carvalho de Melo 710444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 711444e2ff3SArnaldo Carvalho de Melo 712444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 713444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 714444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 715*61726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 716444e2ff3SArnaldo Carvalho de Melo 717444e2ff3SArnaldo Carvalho de Melo /* Thermal Thresholds Support */ 718444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 719444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD0 8 720444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 721444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 722444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD1 16 723444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 724444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD0 (1 << 6) 725444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD0 (1 << 7) 726444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD1 (1 << 8) 727444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD1 (1 << 9) 728444e2ff3SArnaldo Carvalho de Melo 729444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: architectural */ 730444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 731444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 732444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 733444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 734444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 735444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 736444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 737444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 738444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 739444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 740444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 741444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 742444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 743444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 744444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 745444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 746444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 747444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 748444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 749444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 750444e2ff3SArnaldo Carvalho de Melo 751444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 752444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 753444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 754444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 755444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 756444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 757444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 758444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 759444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 760444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 761444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 762444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 763444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 764444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 765444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 766444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 767444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 768444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 769444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 770444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 771444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 772444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 773444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 774444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 775444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 776444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 777444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 778444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 779444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 780444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 781444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 782444e2ff3SArnaldo Carvalho de Melo 783444e2ff3SArnaldo Carvalho de Melo /* MISC_FEATURES_ENABLES non-architectural features */ 784444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES 0x00000140 785444e2ff3SArnaldo Carvalho de Melo 786444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 787444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 788444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 789444e2ff3SArnaldo Carvalho de Melo 790444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_DEADLINE 0x000006E0 791444e2ff3SArnaldo Carvalho de Melo 792444e2ff3SArnaldo Carvalho de Melo 793444e2ff3SArnaldo Carvalho de Melo #define MSR_TSX_FORCE_ABORT 0x0000010F 794444e2ff3SArnaldo Carvalho de Melo 795444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 796444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 79704df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 79804df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 79904df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 80004df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 801444e2ff3SArnaldo Carvalho de Melo 802444e2ff3SArnaldo Carvalho de Melo /* P4/Xeon+ specific */ 803444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EAX 0x00000180 804444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBX 0x00000181 805444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ECX 0x00000182 806444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDX 0x00000183 807444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESI 0x00000184 808444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDI 0x00000185 809444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBP 0x00000186 810444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESP 0x00000187 811444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EFLAGS 0x00000188 812444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EIP 0x00000189 813444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_RESERVED 0x0000018a 814444e2ff3SArnaldo Carvalho de Melo 815444e2ff3SArnaldo Carvalho de Melo /* Pentium IV performance counter MSRs */ 816444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR0 0x00000300 817444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR1 0x00000301 818444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR2 0x00000302 819444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR3 0x00000303 820444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR0 0x00000304 821444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR1 0x00000305 822444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR2 0x00000306 823444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR3 0x00000307 824444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR0 0x00000308 825444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR1 0x00000309 826444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR2 0x0000030a 827444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR3 0x0000030b 828444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR0 0x0000030c 829444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR1 0x0000030d 830444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR2 0x0000030e 831444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR3 0x0000030f 832444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR4 0x00000310 833444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR5 0x00000311 834444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR0 0x00000360 835444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR1 0x00000361 836444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR2 0x00000362 837444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR3 0x00000363 838444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR0 0x00000364 839444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR1 0x00000365 840444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR2 0x00000366 841444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR3 0x00000367 842444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR0 0x00000368 843444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR1 0x00000369 844444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR2 0x0000036a 845444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR3 0x0000036b 846444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR0 0x0000036c 847444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR1 0x0000036d 848444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR2 0x0000036e 849444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR3 0x0000036f 850444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR4 0x00000370 851444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR5 0x00000371 852444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR0 0x000003ca 853444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR1 0x000003cb 854444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR0 0x000003b2 855444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR1 0x000003b3 856444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR0 0x000003a0 857444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR1 0x000003a1 858444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR0 0x000003b8 859444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR1 0x000003b9 860444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR2 0x000003cc 861444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR3 0x000003cd 862444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR4 0x000003e0 863444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR5 0x000003e1 864444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR0 0x000003a8 865444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR1 0x000003a9 866444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR0 0x000003a4 867444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR1 0x000003a5 868444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR0 0x000003a6 869444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR1 0x000003a7 870444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR0 0x000003a2 871444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR1 0x000003a3 872444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR0 0x000003ba 873444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR1 0x000003bb 874444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR0 0x000003b4 875444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR1 0x000003b5 876444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR0 0x000003b6 877444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR1 0x000003b7 878444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR0 0x000003c8 879444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR1 0x000003c9 880444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR0 0x000003aa 881444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR1 0x000003ab 882444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR0 0x000003c0 883444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR1 0x000003c1 884444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR0 0x000003ac 885444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR1 0x000003ad 886444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR0 0x000003bc 887444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR1 0x000003bd 888444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR0 0x000003ae 889444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR1 0x000003af 890444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR0 0x000003be 891444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 892444e2ff3SArnaldo Carvalho de Melo 893444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR0 0x000003c2 894444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR1 0x000003c3 895444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR0 0x000003c4 896444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR1 0x000003c5 897444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR0 0x000003b0 898444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR1 0x000003b1 899444e2ff3SArnaldo Carvalho de Melo 900444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 901444e2ff3SArnaldo Carvalho de Melo 902444e2ff3SArnaldo Carvalho de Melo /* Intel Core-based CPU performance counters */ 903444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 904444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 905444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 90632b734e0SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 907444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 908444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 909444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 910444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 911444e2ff3SArnaldo Carvalho de Melo 91232b734e0SArnaldo Carvalho de Melo #define MSR_PERF_METRICS 0x00000329 91332b734e0SArnaldo Carvalho de Melo 914444e2ff3SArnaldo Carvalho de Melo /* PERF_GLOBAL_OVF_CTL bits */ 915444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 916444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 917444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 918444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 919444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 920444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 921444e2ff3SArnaldo Carvalho de Melo 922444e2ff3SArnaldo Carvalho de Melo /* Geode defined MSRs */ 923444e2ff3SArnaldo Carvalho de Melo #define MSR_GEODE_BUSCONT_CONF0 0x00001900 924444e2ff3SArnaldo Carvalho de Melo 925444e2ff3SArnaldo Carvalho de Melo /* Intel VT MSRs */ 926444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_BASIC 0x00000480 927444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 928444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 929444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 930444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 931444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC 0x00000485 932444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 933444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 934444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 935444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 936444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 937444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 938444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 939444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 940444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 941444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 942444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 943444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMFUNC 0x00000491 944444e2ff3SArnaldo Carvalho de Melo 945444e2ff3SArnaldo Carvalho de Melo /* VMX_BASIC bits and bitmasks */ 946444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_VMCS_SIZE_SHIFT 32 947444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 948444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_64 0x0001000000000000LLU 949444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_SHIFT 50 950444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 951444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_WB 6LLU 952444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_INOUT 0x0040000000000000LLU 953444e2ff3SArnaldo Carvalho de Melo 954444e2ff3SArnaldo Carvalho de Melo /* MSR_IA32_VMX_MISC bits */ 955444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 956444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 957444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 958444e2ff3SArnaldo Carvalho de Melo /* AMD-V MSRs */ 959444e2ff3SArnaldo Carvalho de Melo 960444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_CR 0xc0010114 961444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_IGNNE 0xc0010115 962444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_HSAVE_PA 0xc0010117 963444e2ff3SArnaldo Carvalho de Melo 964*61726144SArnaldo Carvalho de Melo /* Hardware Feedback Interface */ 965*61726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 966*61726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 967*61726144SArnaldo Carvalho de Melo 968444e2ff3SArnaldo Carvalho de Melo #endif /* _ASM_X86_MSR_INDEX_H */ 969