1444e2ff3SArnaldo Carvalho de Melo /* SPDX-License-Identifier: GPL-2.0 */ 2444e2ff3SArnaldo Carvalho de Melo #ifndef _ASM_X86_MSR_INDEX_H 3444e2ff3SArnaldo Carvalho de Melo #define _ASM_X86_MSR_INDEX_H 4444e2ff3SArnaldo Carvalho de Melo 5444e2ff3SArnaldo Carvalho de Melo #include <linux/bits.h> 6444e2ff3SArnaldo Carvalho de Melo 7444e2ff3SArnaldo Carvalho de Melo /* 8444e2ff3SArnaldo Carvalho de Melo * CPU model specific register (MSR) numbers. 9444e2ff3SArnaldo Carvalho de Melo * 10444e2ff3SArnaldo Carvalho de Melo * Do not add new entries to this file unless the definitions are shared 11444e2ff3SArnaldo Carvalho de Melo * between multiple compilation units. 12444e2ff3SArnaldo Carvalho de Melo */ 13444e2ff3SArnaldo Carvalho de Melo 14444e2ff3SArnaldo Carvalho de Melo /* x86-64 specific MSRs */ 15444e2ff3SArnaldo Carvalho de Melo #define MSR_EFER 0xc0000080 /* extended feature register */ 16444e2ff3SArnaldo Carvalho de Melo #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17444e2ff3SArnaldo Carvalho de Melo #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18444e2ff3SArnaldo Carvalho de Melo #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19444e2ff3SArnaldo Carvalho de Melo #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20444e2ff3SArnaldo Carvalho de Melo #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21444e2ff3SArnaldo Carvalho de Melo #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22444e2ff3SArnaldo Carvalho de Melo #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23444e2ff3SArnaldo Carvalho de Melo #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24444e2ff3SArnaldo Carvalho de Melo 25444e2ff3SArnaldo Carvalho de Melo /* EFER bits: */ 26444e2ff3SArnaldo Carvalho de Melo #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27444e2ff3SArnaldo Carvalho de Melo #define _EFER_LME 8 /* Long mode enable */ 28444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMA 10 /* Long mode active (read-only) */ 29444e2ff3SArnaldo Carvalho de Melo #define _EFER_NX 11 /* No execute enable */ 30444e2ff3SArnaldo Carvalho de Melo #define _EFER_SVME 12 /* Enable virtualization */ 31444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32444e2ff3SArnaldo Carvalho de Melo #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33444e2ff3SArnaldo Carvalho de Melo 34444e2ff3SArnaldo Carvalho de Melo #define EFER_SCE (1<<_EFER_SCE) 35444e2ff3SArnaldo Carvalho de Melo #define EFER_LME (1<<_EFER_LME) 36444e2ff3SArnaldo Carvalho de Melo #define EFER_LMA (1<<_EFER_LMA) 37444e2ff3SArnaldo Carvalho de Melo #define EFER_NX (1<<_EFER_NX) 38444e2ff3SArnaldo Carvalho de Melo #define EFER_SVME (1<<_EFER_SVME) 39444e2ff3SArnaldo Carvalho de Melo #define EFER_LMSLE (1<<_EFER_LMSLE) 40444e2ff3SArnaldo Carvalho de Melo #define EFER_FFXSR (1<<_EFER_FFXSR) 41444e2ff3SArnaldo Carvalho de Melo 42444e2ff3SArnaldo Carvalho de Melo /* Intel MSRs. Some also available on other CPUs */ 43444e2ff3SArnaldo Carvalho de Melo 44bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL 0x00000033 45bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47bab1a501SArnaldo Carvalho de Melo 48444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 544ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 554ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 56444e2ff3SArnaldo Carvalho de Melo 57444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 58444e2ff3SArnaldo Carvalho de Melo #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 59444e2ff3SArnaldo Carvalho de Melo 60444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN_CTL 0x0000004e 61444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN 0x0000004f 62444e2ff3SArnaldo Carvalho de Melo 63444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR0 0x000000c1 64444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR1 0x000000c2 65444e2ff3SArnaldo Carvalho de Melo #define MSR_FSB_FREQ 0x000000cd 66444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO 0x000000ce 67444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 68444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 69444e2ff3SArnaldo Carvalho de Melo 70444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL 0xe1 71444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 72444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 73444e2ff3SArnaldo Carvalho de Melo /* 74444e2ff3SArnaldo Carvalho de Melo * The time field is bit[31:2], but representing a 32bit value with 75444e2ff3SArnaldo Carvalho de Melo * bit[1:0] zero. 76444e2ff3SArnaldo Carvalho de Melo */ 77444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 78444e2ff3SArnaldo Carvalho de Melo 79bab1a501SArnaldo Carvalho de Melo /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 80bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS 0x000000cf 819dde6cadSArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 829dde6cadSArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 83bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 84bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 85bab1a501SArnaldo Carvalho de Melo 86444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 87444e2ff3SArnaldo Carvalho de Melo #define NHM_C3_AUTO_DEMOTE (1UL << 25) 88444e2ff3SArnaldo Carvalho de Melo #define NHM_C1_AUTO_DEMOTE (1UL << 26) 89444e2ff3SArnaldo Carvalho de Melo #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 90444e2ff3SArnaldo Carvalho de Melo #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 91444e2ff3SArnaldo Carvalho de Melo #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 92444e2ff3SArnaldo Carvalho de Melo 93444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRcap 0x000000fe 94444e2ff3SArnaldo Carvalho de Melo 95444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 96444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 97444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 9891d248c3SArnaldo Carvalho de Melo #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 99444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 100444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SSB_NO BIT(4) /* 101444e2ff3SArnaldo Carvalho de Melo * Not susceptible to Speculative Store Bypass 102444e2ff3SArnaldo Carvalho de Melo * attack, so no Speculative Store Bypass 103444e2ff3SArnaldo Carvalho de Melo * control required. 104444e2ff3SArnaldo Carvalho de Melo */ 105444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_MDS_NO BIT(5) /* 106444e2ff3SArnaldo Carvalho de Melo * Not susceptible to 107444e2ff3SArnaldo Carvalho de Melo * Microarchitectural Data 108444e2ff3SArnaldo Carvalho de Melo * Sampling (MDS) vulnerabilities. 109444e2ff3SArnaldo Carvalho de Melo */ 1108122b047SArnaldo Carvalho de Melo #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 1118122b047SArnaldo Carvalho de Melo * The processor is not susceptible to a 1128122b047SArnaldo Carvalho de Melo * machine check error due to modifying the 1138122b047SArnaldo Carvalho de Melo * code page size along with either the 1148122b047SArnaldo Carvalho de Melo * physical address or cache type 1158122b047SArnaldo Carvalho de Melo * without TLB invalidation. 1168122b047SArnaldo Carvalho de Melo */ 1178122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1188122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TAA_NO BIT(8) /* 1198122b047SArnaldo Carvalho de Melo * Not susceptible to 1208122b047SArnaldo Carvalho de Melo * TSX Async Abort (TAA) vulnerabilities. 1218122b047SArnaldo Carvalho de Melo */ 12251802186SPawan Gupta #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 12351802186SPawan Gupta * Not susceptible to SBDR and SSDP 12451802186SPawan Gupta * variants of Processor MMIO stale data 12551802186SPawan Gupta * vulnerabilities. 12651802186SPawan Gupta */ 12751802186SPawan Gupta #define ARCH_CAP_FBSDP_NO BIT(14) /* 12851802186SPawan Gupta * Not susceptible to FBSDP variant of 12951802186SPawan Gupta * Processor MMIO stale data 13051802186SPawan Gupta * vulnerabilities. 13151802186SPawan Gupta */ 13251802186SPawan Gupta #define ARCH_CAP_PSDP_NO BIT(15) /* 13351802186SPawan Gupta * Not susceptible to PSDP variant of 13451802186SPawan Gupta * Processor MMIO stale data 13551802186SPawan Gupta * vulnerabilities. 13651802186SPawan Gupta */ 13751802186SPawan Gupta #define ARCH_CAP_FB_CLEAR BIT(17) /* 13851802186SPawan Gupta * VERW clears CPU fill buffer 13951802186SPawan Gupta * even on MDS_NO CPUs. 14051802186SPawan Gupta */ 141027bbb88SPawan Gupta #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 142027bbb88SPawan Gupta * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 143027bbb88SPawan Gupta * bit available to control VERW 144027bbb88SPawan Gupta * behavior. 145027bbb88SPawan Gupta */ 1464ad3278dSPawan Gupta #define ARCH_CAP_RRSBA BIT(19) /* 1474ad3278dSPawan Gupta * Indicates RET may use predictors 1484ad3278dSPawan Gupta * other than the RSB. With eIBRS 1494ad3278dSPawan Gupta * enabled predictions in kernel mode 1504ad3278dSPawan Gupta * are restricted to targets in 1514ad3278dSPawan Gupta * kernel. 1524ad3278dSPawan Gupta */ 1532b129932SDaniel Sneddon #define ARCH_CAP_PBRSB_NO BIT(24) /* 1542b129932SDaniel Sneddon * Not susceptible to Post-Barrier 1552b129932SDaniel Sneddon * Return Stack Buffer Predictions. 1562b129932SDaniel Sneddon */ 157444e2ff3SArnaldo Carvalho de Melo 158a3a36565SArnaldo Carvalho de Melo #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 159a3a36565SArnaldo Carvalho de Melo * IA32_XAPIC_DISABLE_STATUS MSR 160a3a36565SArnaldo Carvalho de Melo * supported 161a3a36565SArnaldo Carvalho de Melo */ 162a3a36565SArnaldo Carvalho de Melo 163444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_FLUSH_CMD 0x0000010b 164444e2ff3SArnaldo Carvalho de Melo #define L1D_FLUSH BIT(0) /* 165444e2ff3SArnaldo Carvalho de Melo * Writeback and invalidate the 166444e2ff3SArnaldo Carvalho de Melo * L1 data cache. 167444e2ff3SArnaldo Carvalho de Melo */ 168444e2ff3SArnaldo Carvalho de Melo 169444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL 0x00000119 170444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL3 0x0000011e 171444e2ff3SArnaldo Carvalho de Melo 1728122b047SArnaldo Carvalho de Melo #define MSR_IA32_TSX_CTRL 0x00000122 1738122b047SArnaldo Carvalho de Melo #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 1748122b047SArnaldo Carvalho de Melo #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 1758122b047SArnaldo Carvalho de Melo 17625ca7e5cSArnaldo Carvalho de Melo #define MSR_IA32_MCU_OPT_CTRL 0x00000123 177400331f8SPawan Gupta #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 178400331f8SPawan Gupta #define RTM_ALLOW BIT(1) /* TSX development mode */ 179027bbb88SPawan Gupta #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 18025ca7e5cSArnaldo Carvalho de Melo 181444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_CS 0x00000174 182444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_ESP 0x00000175 183444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_EIP 0x00000176 184444e2ff3SArnaldo Carvalho de Melo 185444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CAP 0x00000179 186444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_STATUS 0x0000017a 187444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CTL 0x0000017b 188e9bde94fSArnaldo Carvalho de Melo #define MSR_ERROR_CONTROL 0x0000017f 189444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EXT_CTL 0x000004d0 190444e2ff3SArnaldo Carvalho de Melo 191444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_0 0x000001a6 192444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_1 0x000001a7 193444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT 0x000001ad 194444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 195444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT2 0x000001af 196444e2ff3SArnaldo Carvalho de Melo 197444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_SELECT 0x000001c8 198444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_TOS 0x000001c9 199f815fe51SArnaldo Carvalho de Melo 200f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL 0x000001fc 201f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL_BIT_EE 19 202f815fe51SArnaldo Carvalho de Melo 2039dde6cadSArnaldo Carvalho de Melo /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 2049dde6cadSArnaldo Carvalho de Melo #define MSR_INTEGRITY_CAPS 0x000002d9 2059dde6cadSArnaldo Carvalho de Melo #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 2069dde6cadSArnaldo Carvalho de Melo #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 2079dde6cadSArnaldo Carvalho de Melo 208444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_FROM 0x00000680 209444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_TO 0x000006c0 210444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_FROM 0x00000040 211444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_TO 0x00000060 212444e2ff3SArnaldo Carvalho de Melo 213444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 214444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_MISPRED BIT_ULL(63) 215444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_IN_TX BIT_ULL(62) 216444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_ABORT BIT_ULL(61) 217f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 218444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_CYCLES 0xffff 219f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE_OFFSET 56 220f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 221f815fe51SArnaldo Carvalho de Melo 222f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_CTL 0x000014ce 223f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_LBREN BIT(0) 224f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL_OFFSET 1 225f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 226f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK_OFFSET 3 227f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 228f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER_OFFSET 16 229f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 230f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_DEPTH 0x000014cf 231f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_FROM_0 0x00001500 232f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_TO_0 0x00001600 233f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_INFO_0 0x00001200 234444e2ff3SArnaldo Carvalho de Melo 235444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PEBS_ENABLE 0x000003f1 236444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_DATA_CFG 0x000003f2 237444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DS_AREA 0x00000600 238444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CAPABILITIES 0x00000345 239b3172585SArnaldo Carvalho de Melo #define PERF_CAP_METRICS_IDX 15 240b3172585SArnaldo Carvalho de Melo #define PERF_CAP_PT_IDX 16 241b3172585SArnaldo Carvalho de Melo 242444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 2437f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 2447f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_ARCH_REG BIT_ULL(7) 2457f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_FORMAT 0xf00 2467f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 2477f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 2487f7f86a7SArnaldo Carvalho de Melo PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 249444e2ff3SArnaldo Carvalho de Melo 250444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CTL 0x00000570 251444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TRACEEN BIT(0) 252444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYCLEACC BIT(1) 253444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_OS BIT(2) 254444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_USR BIT(3) 255444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PWR_EVT_EN BIT(4) 256444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FUP_ON_PTW BIT(5) 257444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FABRIC_EN BIT(6) 258444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CR3EN BIT(7) 259444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TOPA BIT(8) 260444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_EN BIT(9) 261444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TSC_EN BIT(10) 262444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_DISRETC BIT(11) 263444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PTW_EN BIT(12) 264444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_BRANCH_EN BIT(13) 265672b259fSArnaldo Carvalho de Melo #define RTIT_CTL_EVENT_EN BIT(31) 266672b259fSArnaldo Carvalho de Melo #define RTIT_CTL_NOTNT BIT_ULL(55) 267444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE_OFFSET 14 268444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 269444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH_OFFSET 19 270444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 271444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ_OFFSET 24 272444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 273444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0_OFFSET 32 274444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 275444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1_OFFSET 36 276444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 277444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2_OFFSET 40 278444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 279444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3_OFFSET 44 280444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 281444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_STATUS 0x00000571 282444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_FILTEREN BIT(0) 283444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_CONTEXTEN BIT(1) 284444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_TRIGGEREN BIT(2) 285444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BUFFOVF BIT(3) 286444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_ERROR BIT(4) 287444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_STOPPED BIT(5) 288444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT_OFFSET 32 289444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 290444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_A 0x00000580 291444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_B 0x00000581 292444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_A 0x00000582 293444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_B 0x00000583 294444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_A 0x00000584 295444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_B 0x00000585 296444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_A 0x00000586 297444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_B 0x00000587 298444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 299444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 300444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 301444e2ff3SArnaldo Carvalho de Melo 302444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix64K_00000 0x00000250 303444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_80000 0x00000258 304444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_A0000 0x00000259 305444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C0000 0x00000268 306444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C8000 0x00000269 307444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D0000 0x0000026a 308444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D8000 0x0000026b 309444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E0000 0x0000026c 310444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E8000 0x0000026d 311444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F0000 0x0000026e 312444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F8000 0x0000026f 313444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRdefType 0x000002ff 314444e2ff3SArnaldo Carvalho de Melo 315444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_CR_PAT 0x00000277 316444e2ff3SArnaldo Carvalho de Melo 317444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DEBUGCTLMSR 0x000001d9 318444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 319444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 320444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTFROMIP 0x000001dd 321444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTTOIP 0x000001de 322444e2ff3SArnaldo Carvalho de Melo 32332b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID 0x00000d93 32432b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID_VALID BIT_ULL(31) 32532b734e0SArnaldo Carvalho de Melo 326444e2ff3SArnaldo Carvalho de Melo /* DEBUGCTLMSR bits (others vary by model): */ 327444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 328444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF_SHIFT 1 329444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 330b3172585SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 331444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_TR (1UL << 6) 332444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS (1UL << 7) 333444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTINT (1UL << 8) 334444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 335444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 336444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 337444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 338444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 339444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 340444e2ff3SArnaldo Carvalho de Melo 341444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_FRONTEND 0x000003f7 342444e2ff3SArnaldo Carvalho de Melo 343444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL 0x00000400 344444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_STATUS 0x00000401 345444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_ADDR 0x00000402 346444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_MISC 0x00000403 347444e2ff3SArnaldo Carvalho de Melo 348444e2ff3SArnaldo Carvalho de Melo /* C-state Residency Counters */ 349444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C3_RESIDENCY 0x000003f8 350444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C6_RESIDENCY 0x000003f9 351444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 352444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C7_RESIDENCY 0x000003fa 353444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C3_RESIDENCY 0x000003fc 354444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C6_RESIDENCY 0x000003fd 355444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C7_RESIDENCY 0x000003fe 356444e2ff3SArnaldo Carvalho de Melo #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 357444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C2_RESIDENCY 0x0000060d 358444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C8_RESIDENCY 0x00000630 359444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C9_RESIDENCY 0x00000631 360444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C10_RESIDENCY 0x00000632 361444e2ff3SArnaldo Carvalho de Melo 362444e2ff3SArnaldo Carvalho de Melo /* Interrupt Response Limit */ 363444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC3_IRTL 0x0000060a 364444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC6_IRTL 0x0000060b 365444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC7_IRTL 0x0000060c 366444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC8_IRTL 0x00000633 367444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC9_IRTL 0x00000634 368444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC10_IRTL 0x00000635 369444e2ff3SArnaldo Carvalho de Melo 370444e2ff3SArnaldo Carvalho de Melo /* Run Time Average Power Limiting (RAPL) Interface */ 371444e2ff3SArnaldo Carvalho de Melo 3729dde6cadSArnaldo Carvalho de Melo #define MSR_VR_CURRENT_CONFIG 0x00000601 373444e2ff3SArnaldo Carvalho de Melo #define MSR_RAPL_POWER_UNIT 0x00000606 374444e2ff3SArnaldo Carvalho de Melo 375444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_LIMIT 0x00000610 376444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ENERGY_STATUS 0x00000611 377444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_PERF_STATUS 0x00000613 378444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_INFO 0x00000614 379444e2ff3SArnaldo Carvalho de Melo 380444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_LIMIT 0x00000618 381444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_ENERGY_STATUS 0x00000619 382444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_PERF_STATUS 0x0000061b 383444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_INFO 0x0000061c 384444e2ff3SArnaldo Carvalho de Melo 385444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POWER_LIMIT 0x00000638 386444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_ENERGY_STATUS 0x00000639 387444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POLICY 0x0000063a 388444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_PERF_STATUS 0x0000063b 389444e2ff3SArnaldo Carvalho de Melo 390444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POWER_LIMIT 0x00000640 391444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_ENERGY_STATUS 0x00000641 392444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POLICY 0x00000642 393444e2ff3SArnaldo Carvalho de Melo 3943b1f47d6SArnaldo Carvalho de Melo #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 395e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 396e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 3973b1f47d6SArnaldo Carvalho de Melo 398444e2ff3SArnaldo Carvalho de Melo /* Config TDP MSRs */ 399444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_NOMINAL 0x00000648 400444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 401444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 402444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_CONTROL 0x0000064B 403444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 404444e2ff3SArnaldo Carvalho de Melo 405444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 4067f7f86a7SArnaldo Carvalho de Melo #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 407444e2ff3SArnaldo Carvalho de Melo 408444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 409444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 410444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 411444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 412444e2ff3SArnaldo Carvalho de Melo 413444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C1_RES 0x00000660 414444e2ff3SArnaldo Carvalho de Melo #define MSR_MODULE_C6_RES_MS 0x00000664 415444e2ff3SArnaldo Carvalho de Melo 416444e2ff3SArnaldo Carvalho de Melo #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 417444e2ff3SArnaldo Carvalho de Melo #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 418444e2ff3SArnaldo Carvalho de Melo 419444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_RATIOS 0x0000066a 420444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_VIDS 0x0000066b 421444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 422444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 423444e2ff3SArnaldo Carvalho de Melo 424444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 425444e2ff3SArnaldo Carvalho de Melo #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 426444e2ff3SArnaldo Carvalho de Melo #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 427444e2ff3SArnaldo Carvalho de Melo 428672b259fSArnaldo Carvalho de Melo /* Control-flow Enforcement Technology MSRs */ 429672b259fSArnaldo Carvalho de Melo #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 430672b259fSArnaldo Carvalho de Melo #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 431672b259fSArnaldo Carvalho de Melo #define CET_SHSTK_EN BIT_ULL(0) 432672b259fSArnaldo Carvalho de Melo #define CET_WRSS_EN BIT_ULL(1) 433672b259fSArnaldo Carvalho de Melo #define CET_ENDBR_EN BIT_ULL(2) 434672b259fSArnaldo Carvalho de Melo #define CET_LEG_IW_EN BIT_ULL(3) 435672b259fSArnaldo Carvalho de Melo #define CET_NO_TRACK_EN BIT_ULL(4) 436672b259fSArnaldo Carvalho de Melo #define CET_SUPPRESS_DISABLE BIT_ULL(5) 437672b259fSArnaldo Carvalho de Melo #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 438672b259fSArnaldo Carvalho de Melo #define CET_SUPPRESS BIT_ULL(10) 439672b259fSArnaldo Carvalho de Melo #define CET_WAIT_ENDBR BIT_ULL(11) 440672b259fSArnaldo Carvalho de Melo 441672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 442672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 443672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 444672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 445672b259fSArnaldo Carvalho de Melo #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 446672b259fSArnaldo Carvalho de Melo 447444e2ff3SArnaldo Carvalho de Melo /* Hardware P state interface */ 448444e2ff3SArnaldo Carvalho de Melo #define MSR_PPERF 0x0000064e 449444e2ff3SArnaldo Carvalho de Melo #define MSR_PERF_LIMIT_REASONS 0x0000064f 450444e2ff3SArnaldo Carvalho de Melo #define MSR_PM_ENABLE 0x00000770 451444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_CAPABILITIES 0x00000771 452444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST_PKG 0x00000772 453444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_INTERRUPT 0x00000773 454444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST 0x00000774 455444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_STATUS 0x00000777 456444e2ff3SArnaldo Carvalho de Melo 457444e2ff3SArnaldo Carvalho de Melo /* CPUID.6.EAX */ 458444e2ff3SArnaldo Carvalho de Melo #define HWP_BASE_BIT (1<<7) 459444e2ff3SArnaldo Carvalho de Melo #define HWP_NOTIFICATIONS_BIT (1<<8) 460444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 461444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 462444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 463444e2ff3SArnaldo Carvalho de Melo 464444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_CAPABILITIES */ 465444e2ff3SArnaldo Carvalho de Melo #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 466444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 467444e2ff3SArnaldo Carvalho de Melo #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 468444e2ff3SArnaldo Carvalho de Melo #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 469444e2ff3SArnaldo Carvalho de Melo 470444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_REQUEST */ 471444e2ff3SArnaldo Carvalho de Melo #define HWP_MIN_PERF(x) (x & 0xff) 472444e2ff3SArnaldo Carvalho de Melo #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 473444e2ff3SArnaldo Carvalho de Melo #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 474444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 475444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_PERFORMANCE 0x00 476444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_PERFORMANCE 0x80 477444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_POWERSAVE 0xC0 478444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_POWERSAVE 0xFF 479444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 480444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 481444e2ff3SArnaldo Carvalho de Melo 482444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_STATUS */ 483444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 484444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 485444e2ff3SArnaldo Carvalho de Melo 486444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_INTERRUPT */ 487444e2ff3SArnaldo Carvalho de Melo #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 488444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 489444e2ff3SArnaldo Carvalho de Melo 490444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MC0_MASK 0xc0010044 491444e2ff3SArnaldo Carvalho de Melo 492444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 493444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 494444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 495444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 496444e2ff3SArnaldo Carvalho de Melo 497444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 498444e2ff3SArnaldo Carvalho de Melo 499444e2ff3SArnaldo Carvalho de Melo /* These are consecutive and not in the normal 4er MCE bank block */ 500444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL2 0x00000280 501444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 502444e2ff3SArnaldo Carvalho de Melo 503444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR0 0x000000c1 504444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR1 0x000000c2 505444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL0 0x00000186 506444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL1 0x00000187 507444e2ff3SArnaldo Carvalho de Melo 508444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR0 0x00000020 509444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR1 0x00000021 510444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL0 0x00000028 511444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL1 0x00000029 512444e2ff3SArnaldo Carvalho de Melo 513444e2ff3SArnaldo Carvalho de Melo /* Alternative perfctr range with full access. */ 514444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PMC0 0x000004c1 515444e2ff3SArnaldo Carvalho de Melo 516444e2ff3SArnaldo Carvalho de Melo /* Auto-reload via MSR instead of DS area */ 517444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_PMC0 0x000014c1 518444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_FIXED_CTR0 0x00001309 519444e2ff3SArnaldo Carvalho de Melo 520444e2ff3SArnaldo Carvalho de Melo /* 521444e2ff3SArnaldo Carvalho de Melo * AMD64 MSRs. Not complete. See the architecture manual for a more 522444e2ff3SArnaldo Carvalho de Melo * complete list. 523444e2ff3SArnaldo Carvalho de Melo */ 524444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LEVEL 0x0000008b 525444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_TSC_RATIO 0xc0000104 526444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_NB_CFG 0xc001001f 527444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LOADER 0xc0010020 528444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_CTL 0xc0010062 529444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_STATUS 0xc0010063 530444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 531444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 532444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_STATUS 0xc0010141 5338122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN_CTL 0xc00102f0 5348122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN 0xc00102f1 535f815fe51SArnaldo Carvalho de Melo #define MSR_AMD64_CPUID_FN_1 0xc0011004 536444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_LS_CFG 0xc0011020 537444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_DC_CFG 0xc0011022 538*2632daebSBorislav Petkov 539*2632daebSBorislav Petkov #define MSR_AMD64_DE_CFG 0xc0011029 540*2632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 541*2632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 542*2632daebSBorislav Petkov 543444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_BU_CFG2 0xc001102a 544444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHCTL 0xc0011030 545444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 546444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 547444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_COUNT 3 548444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 549444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPCTL 0xc0011033 550444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPRIP 0xc0011034 551444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA 0xc0011035 552444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA2 0xc0011036 553444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA3 0xc0011037 554444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCLINAD 0xc0011038 555444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 556444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_COUNT 7 557444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 558444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSCTL 0xc001103a 559444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSBRTARGET 0xc001103b 56032b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 561444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA4 0xc001103d 562444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 5635b061a32SArnaldo Carvalho de Melo #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 564fde66824SArnaldo Carvalho de Melo #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 56532b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 566444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV 0xc0010131 567444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED_BIT 0 56832b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 5699dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 570444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 57132b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 5729dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 573444e2ff3SArnaldo Carvalho de Melo 574444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 575444e2ff3SArnaldo Carvalho de Melo 576e652ab64SArnaldo Carvalho de Melo /* AMD Collaborative Processor Performance Control MSRs */ 577e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP1 0xc00102b0 578e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_ENABLE 0xc00102b1 579e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP2 0xc00102b2 580e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_REQ 0xc00102b3 581e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_STATUS 0xc00102b4 582e652ab64SArnaldo Carvalho de Melo 583e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 584e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 585e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 586e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 587e652ab64SArnaldo Carvalho de Melo 588e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 589e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 590e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 591e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 592e652ab64SArnaldo Carvalho de Melo 5939dde6cadSArnaldo Carvalho de Melo /* AMD Performance Counter Global Status and Control MSRs */ 5949dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 5959dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 5969dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 5979dde6cadSArnaldo Carvalho de Melo 598a3a36565SArnaldo Carvalho de Melo /* AMD Last Branch Record MSRs */ 599a3a36565SArnaldo Carvalho de Melo #define MSR_AMD64_LBR_SELECT 0xc000010e 600a3a36565SArnaldo Carvalho de Melo 601444e2ff3SArnaldo Carvalho de Melo /* Fam 17h MSRs */ 602444e2ff3SArnaldo Carvalho de Melo #define MSR_F17H_IRPERF 0xc00000e9 603444e2ff3SArnaldo Carvalho de Melo 60491d248c3SArnaldo Carvalho de Melo #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 60591d248c3SArnaldo Carvalho de Melo #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 60691d248c3SArnaldo Carvalho de Melo 607444e2ff3SArnaldo Carvalho de Melo /* Fam 16h MSRs */ 608444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTL 0xc0010230 609444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTR 0xc0010231 610444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 611444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 612444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 613444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 614444e2ff3SArnaldo Carvalho de Melo 615444e2ff3SArnaldo Carvalho de Melo /* Fam 15h MSRs */ 616f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 617f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 618444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL 0xc0010200 619444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 620444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 621444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 622444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 623444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 624444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 625444e2ff3SArnaldo Carvalho de Melo 626444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR 0xc0010201 627444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 628444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 629444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 630444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 631444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 632444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 633444e2ff3SArnaldo Carvalho de Melo 634444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTL 0xc0010240 635444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTR 0xc0010241 636444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PTSC 0xc0010280 637444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_IC_CFG 0xc0011021 638444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_EX_CFG 0xc001102c 639444e2ff3SArnaldo Carvalho de Melo 640444e2ff3SArnaldo Carvalho de Melo /* Fam 10h MSRs */ 641444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 642444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_ENABLE (1<<0) 643444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 644444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 645444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 646444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_SHIFT 20 647444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_NODE_ID 0xc001100c 648444e2ff3SArnaldo Carvalho de Melo 649444e2ff3SArnaldo Carvalho de Melo /* K8 MSRs */ 650444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM1 0xc001001a 651444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM2 0xc001001d 652059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 653059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 654059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 655444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_INT_PENDING_MSG 0xc0010055 656444e2ff3SArnaldo Carvalho de Melo /* C1E active bits in int pending message */ 657444e2ff3SArnaldo Carvalho de Melo #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 658444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_ADDR 0xc0010112 659444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_MASK 0xc0010113 660444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 661444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 662444e2ff3SArnaldo Carvalho de Melo #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 663444e2ff3SArnaldo Carvalho de Melo 664444e2ff3SArnaldo Carvalho de Melo /* K7 MSRs */ 665444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL0 0xc0010000 666444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR0 0xc0010004 667444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL1 0xc0010001 668444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR1 0xc0010005 669444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL2 0xc0010002 670444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR2 0xc0010006 671444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL3 0xc0010003 672444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR3 0xc0010007 673444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_CLK_CTL 0xc001001b 674444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR 0xc0010015 675444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK_BIT 0 676444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 677d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN_BIT 30 678d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 679444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_CTL 0xc0010041 680444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_STATUS 0xc0010042 681444e2ff3SArnaldo Carvalho de Melo 682444e2ff3SArnaldo Carvalho de Melo /* K6 MSRs */ 683444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_WHCR 0xc0000082 684444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_UWCCR 0xc0000085 685444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_EPMR 0xc0000086 686444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PSOR 0xc0000087 687444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PFIR 0xc0000088 688444e2ff3SArnaldo Carvalho de Melo 689444e2ff3SArnaldo Carvalho de Melo /* Centaur-Hauls/IDT defined MSRs. */ 690444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR1 0x00000107 691444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR2 0x00000108 692444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR3 0x00000109 693444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR4 0x0000010a 694444e2ff3SArnaldo Carvalho de Melo 695444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR0 0x00000110 696444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR1 0x00000111 697444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR2 0x00000112 698444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR3 0x00000113 699444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR4 0x00000114 700444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR5 0x00000115 701444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR6 0x00000116 702444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR7 0x00000117 703444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR_CTRL 0x00000120 704444e2ff3SArnaldo Carvalho de Melo 705444e2ff3SArnaldo Carvalho de Melo /* VIA Cyrix defined MSRs*/ 706444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_FCR 0x00001107 707444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_LONGHAUL 0x0000110a 708444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_RNG 0x0000110b 709444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_BCR2 0x00001147 710444e2ff3SArnaldo Carvalho de Melo 711444e2ff3SArnaldo Carvalho de Melo /* Transmeta defined MSRs */ 712444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_CTRL 0x80868010 713444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 714444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_READOUT 0x80868018 715444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 716444e2ff3SArnaldo Carvalho de Melo 717444e2ff3SArnaldo Carvalho de Melo /* Intel defined MSRs. */ 718444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_ADDR 0x00000000 719444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_TYPE 0x00000001 720444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC 0x00000010 721444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PLATFORM_ID 0x00000017 722444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_EBL_CR_POWERON 0x0000002a 723444e2ff3SArnaldo Carvalho de Melo #define MSR_EBC_FREQUENCY_ID 0x0000002c 724444e2ff3SArnaldo Carvalho de Melo #define MSR_SMI_COUNT 0x00000034 725f6505c88SSean Christopherson 726f6505c88SSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 727f6505c88SSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 728f6505c88SSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 729f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 730f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 731e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 732e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_ENABLED BIT(18) 733f6505c88SSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 734f6505c88SSean Christopherson 735444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_ADJUST 0x0000003b 736444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS 0x00000d90 737444e2ff3SArnaldo Carvalho de Melo 738444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 739444e2ff3SArnaldo Carvalho de Melo 7403442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD 0x000001c4 7413442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD_ERR 0x000001c5 742444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_XSS 0x00000da0 743444e2ff3SArnaldo Carvalho de Melo 744444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE 0x0000001b 745444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BSP (1<<8) 746444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_ENABLE (1<<11) 747444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 748444e2ff3SArnaldo Carvalho de Melo 749444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_WRITE 0x00000079 750444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_REV 0x0000008b 751444e2ff3SArnaldo Carvalho de Melo 752e9bde94fSArnaldo Carvalho de Melo /* Intel SGX Launch Enclave Public Key Hash MSRs */ 753e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 754e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 755e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 756e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 757e9bde94fSArnaldo Carvalho de Melo 758444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 759444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMBASE 0x0000009e 760444e2ff3SArnaldo Carvalho de Melo 761444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_STATUS 0x00000198 762444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CTL 0x00000199 763444e2ff3SArnaldo Carvalho de Melo #define INTEL_PERF_CTL_MASK 0xffff 764444e2ff3SArnaldo Carvalho de Melo 7659dde6cadSArnaldo Carvalho de Melo /* AMD Branch Sampling configuration */ 7669dde6cadSArnaldo Carvalho de Melo #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 7679dde6cadSArnaldo Carvalho de Melo #define MSR_AMD_SAMP_BR_FROM 0xc0010300 7689dde6cadSArnaldo Carvalho de Melo 769a3a36565SArnaldo Carvalho de Melo #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 770a3a36565SArnaldo Carvalho de Melo 771444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MPERF 0x000000e7 772444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APERF 0x000000e8 773444e2ff3SArnaldo Carvalho de Melo 774444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_CONTROL 0x0000019a 775444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_INTERRUPT 0x0000019b 776444e2ff3SArnaldo Carvalho de Melo 777444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_HIGH_ENABLE (1 << 0) 778444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_LOW_ENABLE (1 << 1) 779444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_PLN_ENABLE (1 << 24) 780444e2ff3SArnaldo Carvalho de Melo 781444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_STATUS 0x0000019c 782444e2ff3SArnaldo Carvalho de Melo 783444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_PROCHOT (1 << 0) 784444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_POWER_LIMIT (1 << 10) 785444e2ff3SArnaldo Carvalho de Melo 786444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL 0x0000019d 787444e2ff3SArnaldo Carvalho de Melo 788444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 789444e2ff3SArnaldo Carvalho de Melo 790444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE 0x000001a0 791444e2ff3SArnaldo Carvalho de Melo 792444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 793444e2ff3SArnaldo Carvalho de Melo 794444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURE_CONTROL 0x000001a4 795444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_PWR_MGMT 0x000001aa 796444e2ff3SArnaldo Carvalho de Melo 797444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 798444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_PERFORMANCE 0 799444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 800444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_NORMAL 6 801444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 802444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_POWERSAVE 15 803444e2ff3SArnaldo Carvalho de Melo 804444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 805444e2ff3SArnaldo Carvalho de Melo 806444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 807444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 80861726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 809444e2ff3SArnaldo Carvalho de Melo 810444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 811444e2ff3SArnaldo Carvalho de Melo 812444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 813444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 814444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 81561726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 816444e2ff3SArnaldo Carvalho de Melo 817444e2ff3SArnaldo Carvalho de Melo /* Thermal Thresholds Support */ 818444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 819444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD0 8 820444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 821444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 822444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD1 16 823444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 824444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD0 (1 << 6) 825444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD0 (1 << 7) 826444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD1 (1 << 8) 827444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD1 (1 << 9) 828444e2ff3SArnaldo Carvalho de Melo 829444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: architectural */ 830444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 831444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 832444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 833444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 834444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 835444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 836444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 837444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 838444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 839444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 840444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 841444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 842444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 843444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 844444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 845444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 846444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 847444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 848444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 849444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 850444e2ff3SArnaldo Carvalho de Melo 851444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 852444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 853444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 854444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 855444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 856444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 857444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 858444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 859444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 860444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 861444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 862444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 863444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 864444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 865444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 866444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 867444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 868444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 869444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 870444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 871444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 872444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 873444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 874444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 875444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 876444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 877444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 878444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 879444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 880444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 881444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 882444e2ff3SArnaldo Carvalho de Melo 883444e2ff3SArnaldo Carvalho de Melo /* MISC_FEATURES_ENABLES non-architectural features */ 884444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES 0x00000140 885444e2ff3SArnaldo Carvalho de Melo 886444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 887444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 888444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 889444e2ff3SArnaldo Carvalho de Melo 890444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_DEADLINE 0x000006E0 891444e2ff3SArnaldo Carvalho de Melo 892444e2ff3SArnaldo Carvalho de Melo 893444e2ff3SArnaldo Carvalho de Melo #define MSR_TSX_FORCE_ABORT 0x0000010F 894444e2ff3SArnaldo Carvalho de Melo 895444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 896444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 89704df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 89804df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 89904df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 90004df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 901444e2ff3SArnaldo Carvalho de Melo 902444e2ff3SArnaldo Carvalho de Melo /* P4/Xeon+ specific */ 903444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EAX 0x00000180 904444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBX 0x00000181 905444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ECX 0x00000182 906444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDX 0x00000183 907444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESI 0x00000184 908444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDI 0x00000185 909444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBP 0x00000186 910444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESP 0x00000187 911444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EFLAGS 0x00000188 912444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EIP 0x00000189 913444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_RESERVED 0x0000018a 914444e2ff3SArnaldo Carvalho de Melo 915444e2ff3SArnaldo Carvalho de Melo /* Pentium IV performance counter MSRs */ 916444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR0 0x00000300 917444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR1 0x00000301 918444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR2 0x00000302 919444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR3 0x00000303 920444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR0 0x00000304 921444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR1 0x00000305 922444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR2 0x00000306 923444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR3 0x00000307 924444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR0 0x00000308 925444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR1 0x00000309 926444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR2 0x0000030a 927444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR3 0x0000030b 928444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR0 0x0000030c 929444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR1 0x0000030d 930444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR2 0x0000030e 931444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR3 0x0000030f 932444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR4 0x00000310 933444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR5 0x00000311 934444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR0 0x00000360 935444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR1 0x00000361 936444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR2 0x00000362 937444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR3 0x00000363 938444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR0 0x00000364 939444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR1 0x00000365 940444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR2 0x00000366 941444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR3 0x00000367 942444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR0 0x00000368 943444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR1 0x00000369 944444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR2 0x0000036a 945444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR3 0x0000036b 946444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR0 0x0000036c 947444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR1 0x0000036d 948444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR2 0x0000036e 949444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR3 0x0000036f 950444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR4 0x00000370 951444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR5 0x00000371 952444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR0 0x000003ca 953444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR1 0x000003cb 954444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR0 0x000003b2 955444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR1 0x000003b3 956444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR0 0x000003a0 957444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR1 0x000003a1 958444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR0 0x000003b8 959444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR1 0x000003b9 960444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR2 0x000003cc 961444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR3 0x000003cd 962444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR4 0x000003e0 963444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR5 0x000003e1 964444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR0 0x000003a8 965444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR1 0x000003a9 966444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR0 0x000003a4 967444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR1 0x000003a5 968444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR0 0x000003a6 969444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR1 0x000003a7 970444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR0 0x000003a2 971444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR1 0x000003a3 972444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR0 0x000003ba 973444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR1 0x000003bb 974444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR0 0x000003b4 975444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR1 0x000003b5 976444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR0 0x000003b6 977444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR1 0x000003b7 978444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR0 0x000003c8 979444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR1 0x000003c9 980444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR0 0x000003aa 981444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR1 0x000003ab 982444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR0 0x000003c0 983444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR1 0x000003c1 984444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR0 0x000003ac 985444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR1 0x000003ad 986444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR0 0x000003bc 987444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR1 0x000003bd 988444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR0 0x000003ae 989444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR1 0x000003af 990444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR0 0x000003be 991444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 992444e2ff3SArnaldo Carvalho de Melo 993444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR0 0x000003c2 994444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR1 0x000003c3 995444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR0 0x000003c4 996444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR1 0x000003c5 997444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR0 0x000003b0 998444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR1 0x000003b1 999444e2ff3SArnaldo Carvalho de Melo 1000444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1001444e2ff3SArnaldo Carvalho de Melo 1002444e2ff3SArnaldo Carvalho de Melo /* Intel Core-based CPU performance counters */ 1003444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1004444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1005444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 100632b734e0SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1007444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1008444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1009444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1010444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1011444e2ff3SArnaldo Carvalho de Melo 101232b734e0SArnaldo Carvalho de Melo #define MSR_PERF_METRICS 0x00000329 101332b734e0SArnaldo Carvalho de Melo 1014444e2ff3SArnaldo Carvalho de Melo /* PERF_GLOBAL_OVF_CTL bits */ 1015444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 1016444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1017444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1018444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1019444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1020444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 1021444e2ff3SArnaldo Carvalho de Melo 1022444e2ff3SArnaldo Carvalho de Melo /* Geode defined MSRs */ 1023444e2ff3SArnaldo Carvalho de Melo #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1024444e2ff3SArnaldo Carvalho de Melo 1025444e2ff3SArnaldo Carvalho de Melo /* Intel VT MSRs */ 1026444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_BASIC 0x00000480 1027444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1028444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1029444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1030444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1031444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC 0x00000485 1032444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1033444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1034444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1035444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1036444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1037444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1038444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1039444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1040444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1041444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1042444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1043444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMFUNC 0x00000491 10447f7f86a7SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1045444e2ff3SArnaldo Carvalho de Melo 1046444e2ff3SArnaldo Carvalho de Melo /* VMX_BASIC bits and bitmasks */ 1047444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1048444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1049444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_64 0x0001000000000000LLU 1050444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_SHIFT 50 1051444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1052444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_WB 6LLU 1053444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_INOUT 0x0040000000000000LLU 1054444e2ff3SArnaldo Carvalho de Melo 1055444e2ff3SArnaldo Carvalho de Melo /* MSR_IA32_VMX_MISC bits */ 1056444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1057444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1058444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1059444e2ff3SArnaldo Carvalho de Melo /* AMD-V MSRs */ 1060444e2ff3SArnaldo Carvalho de Melo 1061444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_CR 0xc0010114 1062444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_IGNNE 0xc0010115 1063444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_HSAVE_PA 0xc0010117 1064444e2ff3SArnaldo Carvalho de Melo 106561726144SArnaldo Carvalho de Melo /* Hardware Feedback Interface */ 106661726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 106761726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 106861726144SArnaldo Carvalho de Melo 1069a3a36565SArnaldo Carvalho de Melo /* x2APIC locked status */ 1070a3a36565SArnaldo Carvalho de Melo #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1071a3a36565SArnaldo Carvalho de Melo #define LEGACY_XAPIC_DISABLED BIT(0) /* 1072a3a36565SArnaldo Carvalho de Melo * x2APIC mode is locked and 1073a3a36565SArnaldo Carvalho de Melo * disabling x2APIC will cause 1074a3a36565SArnaldo Carvalho de Melo * a #GP 1075a3a36565SArnaldo Carvalho de Melo */ 1076a3a36565SArnaldo Carvalho de Melo 1077444e2ff3SArnaldo Carvalho de Melo #endif /* _ASM_X86_MSR_INDEX_H */ 1078