1444e2ff3SArnaldo Carvalho de Melo /* SPDX-License-Identifier: GPL-2.0 */ 2444e2ff3SArnaldo Carvalho de Melo #ifndef _ASM_X86_MSR_INDEX_H 3444e2ff3SArnaldo Carvalho de Melo #define _ASM_X86_MSR_INDEX_H 4444e2ff3SArnaldo Carvalho de Melo 5444e2ff3SArnaldo Carvalho de Melo #include <linux/bits.h> 6444e2ff3SArnaldo Carvalho de Melo 7444e2ff3SArnaldo Carvalho de Melo /* 8444e2ff3SArnaldo Carvalho de Melo * CPU model specific register (MSR) numbers. 9444e2ff3SArnaldo Carvalho de Melo * 10444e2ff3SArnaldo Carvalho de Melo * Do not add new entries to this file unless the definitions are shared 11444e2ff3SArnaldo Carvalho de Melo * between multiple compilation units. 12444e2ff3SArnaldo Carvalho de Melo */ 13444e2ff3SArnaldo Carvalho de Melo 14444e2ff3SArnaldo Carvalho de Melo /* x86-64 specific MSRs */ 15444e2ff3SArnaldo Carvalho de Melo #define MSR_EFER 0xc0000080 /* extended feature register */ 16444e2ff3SArnaldo Carvalho de Melo #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17444e2ff3SArnaldo Carvalho de Melo #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18444e2ff3SArnaldo Carvalho de Melo #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19444e2ff3SArnaldo Carvalho de Melo #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20444e2ff3SArnaldo Carvalho de Melo #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21444e2ff3SArnaldo Carvalho de Melo #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22444e2ff3SArnaldo Carvalho de Melo #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23444e2ff3SArnaldo Carvalho de Melo #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24444e2ff3SArnaldo Carvalho de Melo 25444e2ff3SArnaldo Carvalho de Melo /* EFER bits: */ 26444e2ff3SArnaldo Carvalho de Melo #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27444e2ff3SArnaldo Carvalho de Melo #define _EFER_LME 8 /* Long mode enable */ 28444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMA 10 /* Long mode active (read-only) */ 29444e2ff3SArnaldo Carvalho de Melo #define _EFER_NX 11 /* No execute enable */ 30444e2ff3SArnaldo Carvalho de Melo #define _EFER_SVME 12 /* Enable virtualization */ 31444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32444e2ff3SArnaldo Carvalho de Melo #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33444e2ff3SArnaldo Carvalho de Melo 34444e2ff3SArnaldo Carvalho de Melo #define EFER_SCE (1<<_EFER_SCE) 35444e2ff3SArnaldo Carvalho de Melo #define EFER_LME (1<<_EFER_LME) 36444e2ff3SArnaldo Carvalho de Melo #define EFER_LMA (1<<_EFER_LMA) 37444e2ff3SArnaldo Carvalho de Melo #define EFER_NX (1<<_EFER_NX) 38444e2ff3SArnaldo Carvalho de Melo #define EFER_SVME (1<<_EFER_SVME) 39444e2ff3SArnaldo Carvalho de Melo #define EFER_LMSLE (1<<_EFER_LMSLE) 40444e2ff3SArnaldo Carvalho de Melo #define EFER_FFXSR (1<<_EFER_FFXSR) 41444e2ff3SArnaldo Carvalho de Melo 42444e2ff3SArnaldo Carvalho de Melo /* Intel MSRs. Some also available on other CPUs */ 43444e2ff3SArnaldo Carvalho de Melo 44bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL 0x00000033 45bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47bab1a501SArnaldo Carvalho de Melo 48444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54444e2ff3SArnaldo Carvalho de Melo 55444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56444e2ff3SArnaldo Carvalho de Melo #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 57444e2ff3SArnaldo Carvalho de Melo 58444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN_CTL 0x0000004e 59444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN 0x0000004f 60444e2ff3SArnaldo Carvalho de Melo 61444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR0 0x000000c1 62444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR1 0x000000c2 63444e2ff3SArnaldo Carvalho de Melo #define MSR_FSB_FREQ 0x000000cd 64444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO 0x000000ce 65444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 66444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67444e2ff3SArnaldo Carvalho de Melo 68444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL 0xe1 69444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71444e2ff3SArnaldo Carvalho de Melo /* 72444e2ff3SArnaldo Carvalho de Melo * The time field is bit[31:2], but representing a 32bit value with 73444e2ff3SArnaldo Carvalho de Melo * bit[1:0] zero. 74444e2ff3SArnaldo Carvalho de Melo */ 75444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76444e2ff3SArnaldo Carvalho de Melo 77bab1a501SArnaldo Carvalho de Melo /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 78bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS 0x000000cf 79bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 80bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 81bab1a501SArnaldo Carvalho de Melo 82444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 83444e2ff3SArnaldo Carvalho de Melo #define NHM_C3_AUTO_DEMOTE (1UL << 25) 84444e2ff3SArnaldo Carvalho de Melo #define NHM_C1_AUTO_DEMOTE (1UL << 26) 85444e2ff3SArnaldo Carvalho de Melo #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 86444e2ff3SArnaldo Carvalho de Melo #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 87444e2ff3SArnaldo Carvalho de Melo #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 88444e2ff3SArnaldo Carvalho de Melo 89444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRcap 0x000000fe 90444e2ff3SArnaldo Carvalho de Melo 91444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 92444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 93444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 94444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SSB_NO BIT(4) /* 96444e2ff3SArnaldo Carvalho de Melo * Not susceptible to Speculative Store Bypass 97444e2ff3SArnaldo Carvalho de Melo * attack, so no Speculative Store Bypass 98444e2ff3SArnaldo Carvalho de Melo * control required. 99444e2ff3SArnaldo Carvalho de Melo */ 100444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_MDS_NO BIT(5) /* 101444e2ff3SArnaldo Carvalho de Melo * Not susceptible to 102444e2ff3SArnaldo Carvalho de Melo * Microarchitectural Data 103444e2ff3SArnaldo Carvalho de Melo * Sampling (MDS) vulnerabilities. 104444e2ff3SArnaldo Carvalho de Melo */ 1058122b047SArnaldo Carvalho de Melo #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 1068122b047SArnaldo Carvalho de Melo * The processor is not susceptible to a 1078122b047SArnaldo Carvalho de Melo * machine check error due to modifying the 1088122b047SArnaldo Carvalho de Melo * code page size along with either the 1098122b047SArnaldo Carvalho de Melo * physical address or cache type 1108122b047SArnaldo Carvalho de Melo * without TLB invalidation. 1118122b047SArnaldo Carvalho de Melo */ 1128122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1138122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TAA_NO BIT(8) /* 1148122b047SArnaldo Carvalho de Melo * Not susceptible to 1158122b047SArnaldo Carvalho de Melo * TSX Async Abort (TAA) vulnerabilities. 1168122b047SArnaldo Carvalho de Melo */ 11751802186SPawan Gupta #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 11851802186SPawan Gupta * Not susceptible to SBDR and SSDP 11951802186SPawan Gupta * variants of Processor MMIO stale data 12051802186SPawan Gupta * vulnerabilities. 12151802186SPawan Gupta */ 12251802186SPawan Gupta #define ARCH_CAP_FBSDP_NO BIT(14) /* 12351802186SPawan Gupta * Not susceptible to FBSDP variant of 12451802186SPawan Gupta * Processor MMIO stale data 12551802186SPawan Gupta * vulnerabilities. 12651802186SPawan Gupta */ 12751802186SPawan Gupta #define ARCH_CAP_PSDP_NO BIT(15) /* 12851802186SPawan Gupta * Not susceptible to PSDP variant of 12951802186SPawan Gupta * Processor MMIO stale data 13051802186SPawan Gupta * vulnerabilities. 13151802186SPawan Gupta */ 13251802186SPawan Gupta #define ARCH_CAP_FB_CLEAR BIT(17) /* 13351802186SPawan Gupta * VERW clears CPU fill buffer 13451802186SPawan Gupta * even on MDS_NO CPUs. 13551802186SPawan Gupta */ 136*027bbb88SPawan Gupta #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 137*027bbb88SPawan Gupta * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 138*027bbb88SPawan Gupta * bit available to control VERW 139*027bbb88SPawan Gupta * behavior. 140*027bbb88SPawan Gupta */ 141444e2ff3SArnaldo Carvalho de Melo 142444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_FLUSH_CMD 0x0000010b 143444e2ff3SArnaldo Carvalho de Melo #define L1D_FLUSH BIT(0) /* 144444e2ff3SArnaldo Carvalho de Melo * Writeback and invalidate the 145444e2ff3SArnaldo Carvalho de Melo * L1 data cache. 146444e2ff3SArnaldo Carvalho de Melo */ 147444e2ff3SArnaldo Carvalho de Melo 148444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL 0x00000119 149444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL3 0x0000011e 150444e2ff3SArnaldo Carvalho de Melo 1518122b047SArnaldo Carvalho de Melo #define MSR_IA32_TSX_CTRL 0x00000122 1528122b047SArnaldo Carvalho de Melo #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 1538122b047SArnaldo Carvalho de Melo #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 1548122b047SArnaldo Carvalho de Melo 15525ca7e5cSArnaldo Carvalho de Melo #define MSR_IA32_MCU_OPT_CTRL 0x00000123 156400331f8SPawan Gupta #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 157400331f8SPawan Gupta #define RTM_ALLOW BIT(1) /* TSX development mode */ 158*027bbb88SPawan Gupta #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 15925ca7e5cSArnaldo Carvalho de Melo 160444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_CS 0x00000174 161444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_ESP 0x00000175 162444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_EIP 0x00000176 163444e2ff3SArnaldo Carvalho de Melo 164444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CAP 0x00000179 165444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_STATUS 0x0000017a 166444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CTL 0x0000017b 167e9bde94fSArnaldo Carvalho de Melo #define MSR_ERROR_CONTROL 0x0000017f 168444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EXT_CTL 0x000004d0 169444e2ff3SArnaldo Carvalho de Melo 170444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_0 0x000001a6 171444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_1 0x000001a7 172444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT 0x000001ad 173444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 174444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT2 0x000001af 175444e2ff3SArnaldo Carvalho de Melo 176444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_SELECT 0x000001c8 177444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_TOS 0x000001c9 178f815fe51SArnaldo Carvalho de Melo 179f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL 0x000001fc 180f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL_BIT_EE 19 181f815fe51SArnaldo Carvalho de Melo 182444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_FROM 0x00000680 183444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_TO 0x000006c0 184444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_FROM 0x00000040 185444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_TO 0x00000060 186444e2ff3SArnaldo Carvalho de Melo 187444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 188444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_MISPRED BIT_ULL(63) 189444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_IN_TX BIT_ULL(62) 190444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_ABORT BIT_ULL(61) 191f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 192444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_CYCLES 0xffff 193f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE_OFFSET 56 194f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 195f815fe51SArnaldo Carvalho de Melo 196f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_CTL 0x000014ce 197f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_LBREN BIT(0) 198f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL_OFFSET 1 199f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 200f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK_OFFSET 3 201f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 202f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER_OFFSET 16 203f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 204f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_DEPTH 0x000014cf 205f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_FROM_0 0x00001500 206f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_TO_0 0x00001600 207f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_INFO_0 0x00001200 208444e2ff3SArnaldo Carvalho de Melo 209444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PEBS_ENABLE 0x000003f1 210444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_DATA_CFG 0x000003f2 211444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DS_AREA 0x00000600 212444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CAPABILITIES 0x00000345 213b3172585SArnaldo Carvalho de Melo #define PERF_CAP_METRICS_IDX 15 214b3172585SArnaldo Carvalho de Melo #define PERF_CAP_PT_IDX 16 215b3172585SArnaldo Carvalho de Melo 216444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 217444e2ff3SArnaldo Carvalho de Melo 218444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CTL 0x00000570 219444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TRACEEN BIT(0) 220444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYCLEACC BIT(1) 221444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_OS BIT(2) 222444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_USR BIT(3) 223444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PWR_EVT_EN BIT(4) 224444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FUP_ON_PTW BIT(5) 225444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FABRIC_EN BIT(6) 226444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CR3EN BIT(7) 227444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TOPA BIT(8) 228444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_EN BIT(9) 229444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TSC_EN BIT(10) 230444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_DISRETC BIT(11) 231444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PTW_EN BIT(12) 232444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_BRANCH_EN BIT(13) 233672b259fSArnaldo Carvalho de Melo #define RTIT_CTL_EVENT_EN BIT(31) 234672b259fSArnaldo Carvalho de Melo #define RTIT_CTL_NOTNT BIT_ULL(55) 235444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE_OFFSET 14 236444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 237444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH_OFFSET 19 238444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 239444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ_OFFSET 24 240444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 241444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0_OFFSET 32 242444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 243444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1_OFFSET 36 244444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 245444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2_OFFSET 40 246444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 247444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3_OFFSET 44 248444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 249444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_STATUS 0x00000571 250444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_FILTEREN BIT(0) 251444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_CONTEXTEN BIT(1) 252444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_TRIGGEREN BIT(2) 253444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BUFFOVF BIT(3) 254444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_ERROR BIT(4) 255444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_STOPPED BIT(5) 256444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT_OFFSET 32 257444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 258444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_A 0x00000580 259444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_B 0x00000581 260444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_A 0x00000582 261444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_B 0x00000583 262444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_A 0x00000584 263444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_B 0x00000585 264444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_A 0x00000586 265444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_B 0x00000587 266444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 267444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 268444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 269444e2ff3SArnaldo Carvalho de Melo 270444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix64K_00000 0x00000250 271444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_80000 0x00000258 272444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_A0000 0x00000259 273444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C0000 0x00000268 274444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C8000 0x00000269 275444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D0000 0x0000026a 276444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D8000 0x0000026b 277444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E0000 0x0000026c 278444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E8000 0x0000026d 279444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F0000 0x0000026e 280444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F8000 0x0000026f 281444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRdefType 0x000002ff 282444e2ff3SArnaldo Carvalho de Melo 283444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_CR_PAT 0x00000277 284444e2ff3SArnaldo Carvalho de Melo 285444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DEBUGCTLMSR 0x000001d9 286444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 287444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 288444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTFROMIP 0x000001dd 289444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTTOIP 0x000001de 290444e2ff3SArnaldo Carvalho de Melo 29132b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID 0x00000d93 29232b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID_VALID BIT_ULL(31) 29332b734e0SArnaldo Carvalho de Melo 294444e2ff3SArnaldo Carvalho de Melo /* DEBUGCTLMSR bits (others vary by model): */ 295444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 296444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF_SHIFT 1 297444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 298b3172585SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 299444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_TR (1UL << 6) 300444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS (1UL << 7) 301444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTINT (1UL << 8) 302444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 303444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 304444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 305444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 306444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 307444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 308444e2ff3SArnaldo Carvalho de Melo 309444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_FRONTEND 0x000003f7 310444e2ff3SArnaldo Carvalho de Melo 311444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL 0x00000400 312444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_STATUS 0x00000401 313444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_ADDR 0x00000402 314444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_MISC 0x00000403 315444e2ff3SArnaldo Carvalho de Melo 316444e2ff3SArnaldo Carvalho de Melo /* C-state Residency Counters */ 317444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C3_RESIDENCY 0x000003f8 318444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C6_RESIDENCY 0x000003f9 319444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 320444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C7_RESIDENCY 0x000003fa 321444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C3_RESIDENCY 0x000003fc 322444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C6_RESIDENCY 0x000003fd 323444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C7_RESIDENCY 0x000003fe 324444e2ff3SArnaldo Carvalho de Melo #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 325444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C2_RESIDENCY 0x0000060d 326444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C8_RESIDENCY 0x00000630 327444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C9_RESIDENCY 0x00000631 328444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C10_RESIDENCY 0x00000632 329444e2ff3SArnaldo Carvalho de Melo 330444e2ff3SArnaldo Carvalho de Melo /* Interrupt Response Limit */ 331444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC3_IRTL 0x0000060a 332444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC6_IRTL 0x0000060b 333444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC7_IRTL 0x0000060c 334444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC8_IRTL 0x00000633 335444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC9_IRTL 0x00000634 336444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC10_IRTL 0x00000635 337444e2ff3SArnaldo Carvalho de Melo 338444e2ff3SArnaldo Carvalho de Melo /* Run Time Average Power Limiting (RAPL) Interface */ 339444e2ff3SArnaldo Carvalho de Melo 340444e2ff3SArnaldo Carvalho de Melo #define MSR_RAPL_POWER_UNIT 0x00000606 341444e2ff3SArnaldo Carvalho de Melo 342444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_LIMIT 0x00000610 343444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ENERGY_STATUS 0x00000611 344444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_PERF_STATUS 0x00000613 345444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_INFO 0x00000614 346444e2ff3SArnaldo Carvalho de Melo 347444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_LIMIT 0x00000618 348444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_ENERGY_STATUS 0x00000619 349444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_PERF_STATUS 0x0000061b 350444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_INFO 0x0000061c 351444e2ff3SArnaldo Carvalho de Melo 352444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POWER_LIMIT 0x00000638 353444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_ENERGY_STATUS 0x00000639 354444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POLICY 0x0000063a 355444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_PERF_STATUS 0x0000063b 356444e2ff3SArnaldo Carvalho de Melo 357444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POWER_LIMIT 0x00000640 358444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_ENERGY_STATUS 0x00000641 359444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POLICY 0x00000642 360444e2ff3SArnaldo Carvalho de Melo 3613b1f47d6SArnaldo Carvalho de Melo #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 362e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 363e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 3643b1f47d6SArnaldo Carvalho de Melo 365444e2ff3SArnaldo Carvalho de Melo /* Config TDP MSRs */ 366444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_NOMINAL 0x00000648 367444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 368444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 369444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_CONTROL 0x0000064B 370444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 371444e2ff3SArnaldo Carvalho de Melo 372444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 373444e2ff3SArnaldo Carvalho de Melo 374444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 375444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 376444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 377444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 378444e2ff3SArnaldo Carvalho de Melo 379444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C1_RES 0x00000660 380444e2ff3SArnaldo Carvalho de Melo #define MSR_MODULE_C6_RES_MS 0x00000664 381444e2ff3SArnaldo Carvalho de Melo 382444e2ff3SArnaldo Carvalho de Melo #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 383444e2ff3SArnaldo Carvalho de Melo #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 384444e2ff3SArnaldo Carvalho de Melo 385444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_RATIOS 0x0000066a 386444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_VIDS 0x0000066b 387444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 388444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 389444e2ff3SArnaldo Carvalho de Melo 390444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 391444e2ff3SArnaldo Carvalho de Melo #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 392444e2ff3SArnaldo Carvalho de Melo #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 393444e2ff3SArnaldo Carvalho de Melo 394672b259fSArnaldo Carvalho de Melo /* Control-flow Enforcement Technology MSRs */ 395672b259fSArnaldo Carvalho de Melo #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 396672b259fSArnaldo Carvalho de Melo #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 397672b259fSArnaldo Carvalho de Melo #define CET_SHSTK_EN BIT_ULL(0) 398672b259fSArnaldo Carvalho de Melo #define CET_WRSS_EN BIT_ULL(1) 399672b259fSArnaldo Carvalho de Melo #define CET_ENDBR_EN BIT_ULL(2) 400672b259fSArnaldo Carvalho de Melo #define CET_LEG_IW_EN BIT_ULL(3) 401672b259fSArnaldo Carvalho de Melo #define CET_NO_TRACK_EN BIT_ULL(4) 402672b259fSArnaldo Carvalho de Melo #define CET_SUPPRESS_DISABLE BIT_ULL(5) 403672b259fSArnaldo Carvalho de Melo #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 404672b259fSArnaldo Carvalho de Melo #define CET_SUPPRESS BIT_ULL(10) 405672b259fSArnaldo Carvalho de Melo #define CET_WAIT_ENDBR BIT_ULL(11) 406672b259fSArnaldo Carvalho de Melo 407672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 408672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 409672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 410672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 411672b259fSArnaldo Carvalho de Melo #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 412672b259fSArnaldo Carvalho de Melo 413444e2ff3SArnaldo Carvalho de Melo /* Hardware P state interface */ 414444e2ff3SArnaldo Carvalho de Melo #define MSR_PPERF 0x0000064e 415444e2ff3SArnaldo Carvalho de Melo #define MSR_PERF_LIMIT_REASONS 0x0000064f 416444e2ff3SArnaldo Carvalho de Melo #define MSR_PM_ENABLE 0x00000770 417444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_CAPABILITIES 0x00000771 418444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST_PKG 0x00000772 419444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_INTERRUPT 0x00000773 420444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST 0x00000774 421444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_STATUS 0x00000777 422444e2ff3SArnaldo Carvalho de Melo 423444e2ff3SArnaldo Carvalho de Melo /* CPUID.6.EAX */ 424444e2ff3SArnaldo Carvalho de Melo #define HWP_BASE_BIT (1<<7) 425444e2ff3SArnaldo Carvalho de Melo #define HWP_NOTIFICATIONS_BIT (1<<8) 426444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 427444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 428444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 429444e2ff3SArnaldo Carvalho de Melo 430444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_CAPABILITIES */ 431444e2ff3SArnaldo Carvalho de Melo #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 432444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 433444e2ff3SArnaldo Carvalho de Melo #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 434444e2ff3SArnaldo Carvalho de Melo #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 435444e2ff3SArnaldo Carvalho de Melo 436444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_REQUEST */ 437444e2ff3SArnaldo Carvalho de Melo #define HWP_MIN_PERF(x) (x & 0xff) 438444e2ff3SArnaldo Carvalho de Melo #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 439444e2ff3SArnaldo Carvalho de Melo #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 440444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 441444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_PERFORMANCE 0x00 442444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_PERFORMANCE 0x80 443444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_POWERSAVE 0xC0 444444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_POWERSAVE 0xFF 445444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 446444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 447444e2ff3SArnaldo Carvalho de Melo 448444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_STATUS */ 449444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 450444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 451444e2ff3SArnaldo Carvalho de Melo 452444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_INTERRUPT */ 453444e2ff3SArnaldo Carvalho de Melo #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 454444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 455444e2ff3SArnaldo Carvalho de Melo 456444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MC0_MASK 0xc0010044 457444e2ff3SArnaldo Carvalho de Melo 458444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 459444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 460444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 461444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 462444e2ff3SArnaldo Carvalho de Melo 463444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 464444e2ff3SArnaldo Carvalho de Melo 465444e2ff3SArnaldo Carvalho de Melo /* These are consecutive and not in the normal 4er MCE bank block */ 466444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL2 0x00000280 467444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 468444e2ff3SArnaldo Carvalho de Melo 469444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR0 0x000000c1 470444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR1 0x000000c2 471444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL0 0x00000186 472444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL1 0x00000187 473444e2ff3SArnaldo Carvalho de Melo 474444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR0 0x00000020 475444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR1 0x00000021 476444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL0 0x00000028 477444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL1 0x00000029 478444e2ff3SArnaldo Carvalho de Melo 479444e2ff3SArnaldo Carvalho de Melo /* Alternative perfctr range with full access. */ 480444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PMC0 0x000004c1 481444e2ff3SArnaldo Carvalho de Melo 482444e2ff3SArnaldo Carvalho de Melo /* Auto-reload via MSR instead of DS area */ 483444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_PMC0 0x000014c1 484444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_FIXED_CTR0 0x00001309 485444e2ff3SArnaldo Carvalho de Melo 486444e2ff3SArnaldo Carvalho de Melo /* 487444e2ff3SArnaldo Carvalho de Melo * AMD64 MSRs. Not complete. See the architecture manual for a more 488444e2ff3SArnaldo Carvalho de Melo * complete list. 489444e2ff3SArnaldo Carvalho de Melo */ 490444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LEVEL 0x0000008b 491444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_TSC_RATIO 0xc0000104 492444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_NB_CFG 0xc001001f 493444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LOADER 0xc0010020 494444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_CTL 0xc0010062 495444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_STATUS 0xc0010063 496444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 497444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 498444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_STATUS 0xc0010141 4998122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN_CTL 0xc00102f0 5008122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN 0xc00102f1 501f815fe51SArnaldo Carvalho de Melo #define MSR_AMD64_CPUID_FN_1 0xc0011004 502444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_LS_CFG 0xc0011020 503444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_DC_CFG 0xc0011022 504444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_BU_CFG2 0xc001102a 505444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHCTL 0xc0011030 506444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 507444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 508444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_COUNT 3 509444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 510444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPCTL 0xc0011033 511444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPRIP 0xc0011034 512444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA 0xc0011035 513444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA2 0xc0011036 514444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA3 0xc0011037 515444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCLINAD 0xc0011038 516444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 517444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_COUNT 7 518444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 519444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSCTL 0xc001103a 520444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSBRTARGET 0xc001103b 52132b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 522444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA4 0xc001103d 523444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 5245b061a32SArnaldo Carvalho de Melo #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 525fde66824SArnaldo Carvalho de Melo #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 52632b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 527444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV 0xc0010131 528444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED_BIT 0 52932b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 530444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 53132b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 532444e2ff3SArnaldo Carvalho de Melo 533444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 534444e2ff3SArnaldo Carvalho de Melo 535e652ab64SArnaldo Carvalho de Melo /* AMD Collaborative Processor Performance Control MSRs */ 536e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP1 0xc00102b0 537e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_ENABLE 0xc00102b1 538e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP2 0xc00102b2 539e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_REQ 0xc00102b3 540e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_STATUS 0xc00102b4 541e652ab64SArnaldo Carvalho de Melo 542e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 543e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 544e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 545e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 546e652ab64SArnaldo Carvalho de Melo 547e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 548e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 549e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 550e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 551e652ab64SArnaldo Carvalho de Melo 552444e2ff3SArnaldo Carvalho de Melo /* Fam 17h MSRs */ 553444e2ff3SArnaldo Carvalho de Melo #define MSR_F17H_IRPERF 0xc00000e9 554444e2ff3SArnaldo Carvalho de Melo 555444e2ff3SArnaldo Carvalho de Melo /* Fam 16h MSRs */ 556444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTL 0xc0010230 557444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTR 0xc0010231 558444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 559444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 560444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 561444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 562444e2ff3SArnaldo Carvalho de Melo 563444e2ff3SArnaldo Carvalho de Melo /* Fam 15h MSRs */ 564f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 565f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 566444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL 0xc0010200 567444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 568444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 569444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 570444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 571444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 572444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 573444e2ff3SArnaldo Carvalho de Melo 574444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR 0xc0010201 575444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 576444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 577444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 578444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 579444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 580444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 581444e2ff3SArnaldo Carvalho de Melo 582444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTL 0xc0010240 583444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTR 0xc0010241 584444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PTSC 0xc0010280 585444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_IC_CFG 0xc0011021 586444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_EX_CFG 0xc001102c 587444e2ff3SArnaldo Carvalho de Melo 588444e2ff3SArnaldo Carvalho de Melo /* Fam 10h MSRs */ 589444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 590444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_ENABLE (1<<0) 591444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 592444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 593444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 594444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_SHIFT 20 595444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_NODE_ID 0xc001100c 596444e2ff3SArnaldo Carvalho de Melo #define MSR_F10H_DECFG 0xc0011029 597444e2ff3SArnaldo Carvalho de Melo #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 598444e2ff3SArnaldo Carvalho de Melo #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 599444e2ff3SArnaldo Carvalho de Melo 600444e2ff3SArnaldo Carvalho de Melo /* K8 MSRs */ 601444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM1 0xc001001a 602444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM2 0xc001001d 603059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 604059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 605059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 606444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_INT_PENDING_MSG 0xc0010055 607444e2ff3SArnaldo Carvalho de Melo /* C1E active bits in int pending message */ 608444e2ff3SArnaldo Carvalho de Melo #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 609444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_ADDR 0xc0010112 610444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_MASK 0xc0010113 611444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 612444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 613444e2ff3SArnaldo Carvalho de Melo #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 614444e2ff3SArnaldo Carvalho de Melo 615444e2ff3SArnaldo Carvalho de Melo /* K7 MSRs */ 616444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL0 0xc0010000 617444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR0 0xc0010004 618444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL1 0xc0010001 619444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR1 0xc0010005 620444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL2 0xc0010002 621444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR2 0xc0010006 622444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL3 0xc0010003 623444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR3 0xc0010007 624444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_CLK_CTL 0xc001001b 625444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR 0xc0010015 626444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK_BIT 0 627444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 628d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN_BIT 30 629d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 630444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_CTL 0xc0010041 631444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_STATUS 0xc0010042 632444e2ff3SArnaldo Carvalho de Melo 633444e2ff3SArnaldo Carvalho de Melo /* K6 MSRs */ 634444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_WHCR 0xc0000082 635444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_UWCCR 0xc0000085 636444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_EPMR 0xc0000086 637444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PSOR 0xc0000087 638444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PFIR 0xc0000088 639444e2ff3SArnaldo Carvalho de Melo 640444e2ff3SArnaldo Carvalho de Melo /* Centaur-Hauls/IDT defined MSRs. */ 641444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR1 0x00000107 642444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR2 0x00000108 643444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR3 0x00000109 644444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR4 0x0000010a 645444e2ff3SArnaldo Carvalho de Melo 646444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR0 0x00000110 647444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR1 0x00000111 648444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR2 0x00000112 649444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR3 0x00000113 650444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR4 0x00000114 651444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR5 0x00000115 652444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR6 0x00000116 653444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR7 0x00000117 654444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR_CTRL 0x00000120 655444e2ff3SArnaldo Carvalho de Melo 656444e2ff3SArnaldo Carvalho de Melo /* VIA Cyrix defined MSRs*/ 657444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_FCR 0x00001107 658444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_LONGHAUL 0x0000110a 659444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_RNG 0x0000110b 660444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_BCR2 0x00001147 661444e2ff3SArnaldo Carvalho de Melo 662444e2ff3SArnaldo Carvalho de Melo /* Transmeta defined MSRs */ 663444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_CTRL 0x80868010 664444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 665444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_READOUT 0x80868018 666444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 667444e2ff3SArnaldo Carvalho de Melo 668444e2ff3SArnaldo Carvalho de Melo /* Intel defined MSRs. */ 669444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_ADDR 0x00000000 670444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_TYPE 0x00000001 671444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC 0x00000010 672444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PLATFORM_ID 0x00000017 673444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_EBL_CR_POWERON 0x0000002a 674444e2ff3SArnaldo Carvalho de Melo #define MSR_EBC_FREQUENCY_ID 0x0000002c 675444e2ff3SArnaldo Carvalho de Melo #define MSR_SMI_COUNT 0x00000034 676f6505c88SSean Christopherson 677f6505c88SSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 678f6505c88SSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 679f6505c88SSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 680f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 681f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 682e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 683e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_ENABLED BIT(18) 684f6505c88SSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 685f6505c88SSean Christopherson 686444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_ADJUST 0x0000003b 687444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS 0x00000d90 688444e2ff3SArnaldo Carvalho de Melo 689444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 690444e2ff3SArnaldo Carvalho de Melo 6913442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD 0x000001c4 6923442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD_ERR 0x000001c5 693444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_XSS 0x00000da0 694444e2ff3SArnaldo Carvalho de Melo 695444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE 0x0000001b 696444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BSP (1<<8) 697444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_ENABLE (1<<11) 698444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 699444e2ff3SArnaldo Carvalho de Melo 700444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_WRITE 0x00000079 701444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_REV 0x0000008b 702444e2ff3SArnaldo Carvalho de Melo 703e9bde94fSArnaldo Carvalho de Melo /* Intel SGX Launch Enclave Public Key Hash MSRs */ 704e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 705e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 706e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 707e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 708e9bde94fSArnaldo Carvalho de Melo 709444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 710444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMBASE 0x0000009e 711444e2ff3SArnaldo Carvalho de Melo 712444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_STATUS 0x00000198 713444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CTL 0x00000199 714444e2ff3SArnaldo Carvalho de Melo #define INTEL_PERF_CTL_MASK 0xffff 715444e2ff3SArnaldo Carvalho de Melo 716444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MPERF 0x000000e7 717444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APERF 0x000000e8 718444e2ff3SArnaldo Carvalho de Melo 719444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_CONTROL 0x0000019a 720444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_INTERRUPT 0x0000019b 721444e2ff3SArnaldo Carvalho de Melo 722444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_HIGH_ENABLE (1 << 0) 723444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_LOW_ENABLE (1 << 1) 724444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_PLN_ENABLE (1 << 24) 725444e2ff3SArnaldo Carvalho de Melo 726444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_STATUS 0x0000019c 727444e2ff3SArnaldo Carvalho de Melo 728444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_PROCHOT (1 << 0) 729444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_POWER_LIMIT (1 << 10) 730444e2ff3SArnaldo Carvalho de Melo 731444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL 0x0000019d 732444e2ff3SArnaldo Carvalho de Melo 733444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 734444e2ff3SArnaldo Carvalho de Melo 735444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE 0x000001a0 736444e2ff3SArnaldo Carvalho de Melo 737444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 738444e2ff3SArnaldo Carvalho de Melo 739444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURE_CONTROL 0x000001a4 740444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_PWR_MGMT 0x000001aa 741444e2ff3SArnaldo Carvalho de Melo 742444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 743444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_PERFORMANCE 0 744444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 745444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_NORMAL 6 746444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 747444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_POWERSAVE 15 748444e2ff3SArnaldo Carvalho de Melo 749444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 750444e2ff3SArnaldo Carvalho de Melo 751444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 752444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 75361726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 754444e2ff3SArnaldo Carvalho de Melo 755444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 756444e2ff3SArnaldo Carvalho de Melo 757444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 758444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 759444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 76061726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 761444e2ff3SArnaldo Carvalho de Melo 762444e2ff3SArnaldo Carvalho de Melo /* Thermal Thresholds Support */ 763444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 764444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD0 8 765444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 766444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 767444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD1 16 768444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 769444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD0 (1 << 6) 770444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD0 (1 << 7) 771444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD1 (1 << 8) 772444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD1 (1 << 9) 773444e2ff3SArnaldo Carvalho de Melo 774444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: architectural */ 775444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 776444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 777444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 778444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 779444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 780444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 781444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 782444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 783444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 784444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 785444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 786444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 787444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 788444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 789444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 790444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 791444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 792444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 793444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 794444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 795444e2ff3SArnaldo Carvalho de Melo 796444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 797444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 798444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 799444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 800444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 801444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 802444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 803444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 804444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 805444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 806444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 807444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 808444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 809444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 810444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 811444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 812444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 813444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 814444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 815444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 816444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 817444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 818444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 819444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 820444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 821444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 822444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 823444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 824444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 825444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 826444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 827444e2ff3SArnaldo Carvalho de Melo 828444e2ff3SArnaldo Carvalho de Melo /* MISC_FEATURES_ENABLES non-architectural features */ 829444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES 0x00000140 830444e2ff3SArnaldo Carvalho de Melo 831444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 832444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 833444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 834444e2ff3SArnaldo Carvalho de Melo 835444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_DEADLINE 0x000006E0 836444e2ff3SArnaldo Carvalho de Melo 837444e2ff3SArnaldo Carvalho de Melo 838444e2ff3SArnaldo Carvalho de Melo #define MSR_TSX_FORCE_ABORT 0x0000010F 839444e2ff3SArnaldo Carvalho de Melo 840444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 841444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 84204df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 84304df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 84404df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 84504df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 846444e2ff3SArnaldo Carvalho de Melo 847444e2ff3SArnaldo Carvalho de Melo /* P4/Xeon+ specific */ 848444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EAX 0x00000180 849444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBX 0x00000181 850444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ECX 0x00000182 851444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDX 0x00000183 852444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESI 0x00000184 853444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDI 0x00000185 854444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBP 0x00000186 855444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESP 0x00000187 856444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EFLAGS 0x00000188 857444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EIP 0x00000189 858444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_RESERVED 0x0000018a 859444e2ff3SArnaldo Carvalho de Melo 860444e2ff3SArnaldo Carvalho de Melo /* Pentium IV performance counter MSRs */ 861444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR0 0x00000300 862444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR1 0x00000301 863444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR2 0x00000302 864444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR3 0x00000303 865444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR0 0x00000304 866444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR1 0x00000305 867444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR2 0x00000306 868444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR3 0x00000307 869444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR0 0x00000308 870444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR1 0x00000309 871444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR2 0x0000030a 872444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR3 0x0000030b 873444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR0 0x0000030c 874444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR1 0x0000030d 875444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR2 0x0000030e 876444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR3 0x0000030f 877444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR4 0x00000310 878444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR5 0x00000311 879444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR0 0x00000360 880444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR1 0x00000361 881444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR2 0x00000362 882444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR3 0x00000363 883444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR0 0x00000364 884444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR1 0x00000365 885444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR2 0x00000366 886444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR3 0x00000367 887444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR0 0x00000368 888444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR1 0x00000369 889444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR2 0x0000036a 890444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR3 0x0000036b 891444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR0 0x0000036c 892444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR1 0x0000036d 893444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR2 0x0000036e 894444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR3 0x0000036f 895444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR4 0x00000370 896444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR5 0x00000371 897444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR0 0x000003ca 898444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR1 0x000003cb 899444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR0 0x000003b2 900444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR1 0x000003b3 901444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR0 0x000003a0 902444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR1 0x000003a1 903444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR0 0x000003b8 904444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR1 0x000003b9 905444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR2 0x000003cc 906444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR3 0x000003cd 907444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR4 0x000003e0 908444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR5 0x000003e1 909444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR0 0x000003a8 910444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR1 0x000003a9 911444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR0 0x000003a4 912444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR1 0x000003a5 913444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR0 0x000003a6 914444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR1 0x000003a7 915444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR0 0x000003a2 916444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR1 0x000003a3 917444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR0 0x000003ba 918444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR1 0x000003bb 919444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR0 0x000003b4 920444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR1 0x000003b5 921444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR0 0x000003b6 922444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR1 0x000003b7 923444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR0 0x000003c8 924444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR1 0x000003c9 925444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR0 0x000003aa 926444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR1 0x000003ab 927444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR0 0x000003c0 928444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR1 0x000003c1 929444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR0 0x000003ac 930444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR1 0x000003ad 931444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR0 0x000003bc 932444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR1 0x000003bd 933444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR0 0x000003ae 934444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR1 0x000003af 935444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR0 0x000003be 936444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 937444e2ff3SArnaldo Carvalho de Melo 938444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR0 0x000003c2 939444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR1 0x000003c3 940444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR0 0x000003c4 941444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR1 0x000003c5 942444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR0 0x000003b0 943444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR1 0x000003b1 944444e2ff3SArnaldo Carvalho de Melo 945444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 946444e2ff3SArnaldo Carvalho de Melo 947444e2ff3SArnaldo Carvalho de Melo /* Intel Core-based CPU performance counters */ 948444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 949444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 950444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 95132b734e0SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 952444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 953444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 954444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 955444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 956444e2ff3SArnaldo Carvalho de Melo 95732b734e0SArnaldo Carvalho de Melo #define MSR_PERF_METRICS 0x00000329 95832b734e0SArnaldo Carvalho de Melo 959444e2ff3SArnaldo Carvalho de Melo /* PERF_GLOBAL_OVF_CTL bits */ 960444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 961444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 962444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 963444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 964444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 965444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 966444e2ff3SArnaldo Carvalho de Melo 967444e2ff3SArnaldo Carvalho de Melo /* Geode defined MSRs */ 968444e2ff3SArnaldo Carvalho de Melo #define MSR_GEODE_BUSCONT_CONF0 0x00001900 969444e2ff3SArnaldo Carvalho de Melo 970444e2ff3SArnaldo Carvalho de Melo /* Intel VT MSRs */ 971444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_BASIC 0x00000480 972444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 973444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 974444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 975444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 976444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC 0x00000485 977444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 978444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 979444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 980444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 981444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 982444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 983444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 984444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 985444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 986444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 987444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 988444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMFUNC 0x00000491 989444e2ff3SArnaldo Carvalho de Melo 990444e2ff3SArnaldo Carvalho de Melo /* VMX_BASIC bits and bitmasks */ 991444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_VMCS_SIZE_SHIFT 32 992444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 993444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_64 0x0001000000000000LLU 994444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_SHIFT 50 995444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 996444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_WB 6LLU 997444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_INOUT 0x0040000000000000LLU 998444e2ff3SArnaldo Carvalho de Melo 999444e2ff3SArnaldo Carvalho de Melo /* MSR_IA32_VMX_MISC bits */ 1000444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1001444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1002444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1003444e2ff3SArnaldo Carvalho de Melo /* AMD-V MSRs */ 1004444e2ff3SArnaldo Carvalho de Melo 1005444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_CR 0xc0010114 1006444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_IGNNE 0xc0010115 1007444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_HSAVE_PA 0xc0010117 1008444e2ff3SArnaldo Carvalho de Melo 100961726144SArnaldo Carvalho de Melo /* Hardware Feedback Interface */ 101061726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 101161726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 101261726144SArnaldo Carvalho de Melo 1013444e2ff3SArnaldo Carvalho de Melo #endif /* _ASM_X86_MSR_INDEX_H */ 1014