1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 27d7d1bf1SArnaldo Carvalho de Melo #ifndef _ASM_X86_CPUFEATURES_H 37d7d1bf1SArnaldo Carvalho de Melo #define _ASM_X86_CPUFEATURES_H 47d7d1bf1SArnaldo Carvalho de Melo 57d7d1bf1SArnaldo Carvalho de Melo #ifndef _ASM_X86_REQUIRED_FEATURES_H 67d7d1bf1SArnaldo Carvalho de Melo #include <asm/required-features.h> 77d7d1bf1SArnaldo Carvalho de Melo #endif 87d7d1bf1SArnaldo Carvalho de Melo 97d7d1bf1SArnaldo Carvalho de Melo #ifndef _ASM_X86_DISABLED_FEATURES_H 107d7d1bf1SArnaldo Carvalho de Melo #include <asm/disabled-features.h> 117d7d1bf1SArnaldo Carvalho de Melo #endif 127d7d1bf1SArnaldo Carvalho de Melo 137d7d1bf1SArnaldo Carvalho de Melo /* 147d7d1bf1SArnaldo Carvalho de Melo * Defines x86 CPU feature bits 157d7d1bf1SArnaldo Carvalho de Melo */ 164053717aSArnaldo Carvalho de Melo #define NCAPINTS 19 /* N 32-bit words worth of info */ 177d7d1bf1SArnaldo Carvalho de Melo #define NBUGINTS 1 /* N 32-bit bug flags */ 187d7d1bf1SArnaldo Carvalho de Melo 197d7d1bf1SArnaldo Carvalho de Melo /* 207d7d1bf1SArnaldo Carvalho de Melo * Note: If the comment begins with a quoted string, that string is used 217d7d1bf1SArnaldo Carvalho de Melo * in /proc/cpuinfo instead of the macro name. If the string is "", 227d7d1bf1SArnaldo Carvalho de Melo * this feature bit is not displayed in /proc/cpuinfo at all. 230b44cfb8SIngo Molnar * 240b44cfb8SIngo Molnar * When adding new features here that depend on other features, 250b44cfb8SIngo Molnar * please update the table in kernel/cpu/cpuid-deps.c as well. 267d7d1bf1SArnaldo Carvalho de Melo */ 277d7d1bf1SArnaldo Carvalho de Melo 280b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ 297d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ 307d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ 317d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ 327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ 337d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ 347d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ 357d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ 367d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ 377d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ 387d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ 397d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ 407d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ 417d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ 427d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ 430b44cfb8SIngo Molnar #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ 447d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ 457d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ 467d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ 477d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ 487d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ 497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ 507d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ 517d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ 527d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ 537d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ 547d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ 557d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ 567d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ 577d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ 587d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ 597d7d1bf1SArnaldo Carvalho de Melo 607d7d1bf1SArnaldo Carvalho de Melo /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 617d7d1bf1SArnaldo Carvalho de Melo /* Don't duplicate feature flags which are redundant with Intel! */ 627d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ 630b44cfb8SIngo Molnar #define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ 647d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ 657d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ 667d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ 677d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ 687d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ 690b44cfb8SIngo Molnar #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ 700b44cfb8SIngo Molnar #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ 710b44cfb8SIngo Molnar #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ 727d7d1bf1SArnaldo Carvalho de Melo 737d7d1bf1SArnaldo Carvalho de Melo /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ 747d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ 757d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ 767d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ 777d7d1bf1SArnaldo Carvalho de Melo 787d7d1bf1SArnaldo Carvalho de Melo /* Other features, Linux-defined mapping, word 3 */ 797d7d1bf1SArnaldo Carvalho de Melo /* This range is used for feature bits which conflict or are synthesized */ 807d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ 817d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ 827d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 837d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ 840b44cfb8SIngo Molnar 850b44cfb8SIngo Molnar /* CPU types for specific tunings: */ 867d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ 877d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ 887d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ 897d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ 907d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ 910b44cfb8SIngo Molnar #define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ 920b44cfb8SIngo Molnar #define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ 937d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ 947d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ 957d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ 960b44cfb8SIngo Molnar #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ 970b44cfb8SIngo Molnar #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ 980b44cfb8SIngo Molnar #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ 990b44cfb8SIngo Molnar #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ 1000b44cfb8SIngo Molnar #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ 1017d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ 1027d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ 1037d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ 1040b44cfb8SIngo Molnar #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ 1057d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ 1067d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ 10774beb09aSArnaldo Carvalho de Melo #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ 1080b44cfb8SIngo Molnar #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ 1090b44cfb8SIngo Molnar #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ 1100b44cfb8SIngo Molnar #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ 1117d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ 112c0621acfSIngo Molnar #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ 1137d7d1bf1SArnaldo Carvalho de Melo 1140b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ 1157d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ 1167d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ 1177d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ 1180b44cfb8SIngo Molnar #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ 1190b44cfb8SIngo Molnar #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ 1207d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ 1210b44cfb8SIngo Molnar #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ 1227d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ 1237d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ 1247d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ 1257d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ 1267d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ 1277d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ 1280b44cfb8SIngo Molnar #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ 1297d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ 1300b44cfb8SIngo Molnar #define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ 1317d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ 1327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ 1337d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ 1347d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ 1350b44cfb8SIngo Molnar #define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ 1367d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ 1377d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ 1380b44cfb8SIngo Molnar #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ 1397d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ 1400b44cfb8SIngo Molnar #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ 1410b44cfb8SIngo Molnar #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ 1427d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ 1430b44cfb8SIngo Molnar #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ 1440b44cfb8SIngo Molnar #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ 1457d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ 1467d7d1bf1SArnaldo Carvalho de Melo 1477d7d1bf1SArnaldo Carvalho de Melo /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 1487d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ 1497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ 1507d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ 1517d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ 1527d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ 1537d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ 1547d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ 1557d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ 1567d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ 1577d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ 1587d7d1bf1SArnaldo Carvalho de Melo 1590b44cfb8SIngo Molnar /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ 1607d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ 1617d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ 1620b44cfb8SIngo Molnar #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ 1637d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ 1647d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ 1657d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ 1667d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ 1677d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ 1687d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ 1697d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ 1707d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ 1717d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ 1727d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ 1737d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ 1747d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ 1757d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ 1760b44cfb8SIngo Molnar #define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ 1777d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ 1780b44cfb8SIngo Molnar #define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ 1790b44cfb8SIngo Molnar #define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ 1800b44cfb8SIngo Molnar #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ 1817d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ 1820b44cfb8SIngo Molnar #define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ 1830b44cfb8SIngo Molnar #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ 184a2105f8aSArnaldo Carvalho de Melo #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ 1850b44cfb8SIngo Molnar #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ 1867d7d1bf1SArnaldo Carvalho de Melo 1877d7d1bf1SArnaldo Carvalho de Melo /* 1887d7d1bf1SArnaldo Carvalho de Melo * Auxiliary flags: Linux defined - For features scattered in various 1897d7d1bf1SArnaldo Carvalho de Melo * CPUID levels like 0x6, 0xA etc, word 7. 1907d7d1bf1SArnaldo Carvalho de Melo * 1917d7d1bf1SArnaldo Carvalho de Melo * Reuse free bits when adding new feature flags! 1927d7d1bf1SArnaldo Carvalho de Melo */ 1930b44cfb8SIngo Molnar #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ 194fb7b7561SArnaldo Carvalho de Melo #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ 1957d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ 1967d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ 197c0621acfSIngo Molnar #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ 198c0621acfSIngo Molnar #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ 199c0621acfSIngo Molnar #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ 2005d64db29SArnaldo Carvalho de Melo #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */ 2017d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ 2027d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ 203549a3976SIngo Molnar #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ 2045d64db29SArnaldo Carvalho de Melo #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ 2054053717aSArnaldo Carvalho de Melo #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ 2064053717aSArnaldo Carvalho de Melo #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */ 207c0621acfSIngo Molnar #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ 2084053717aSArnaldo Carvalho de Melo #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ 209a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ 210a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */ 2116e30437bSIngo Molnar #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ 2124053717aSArnaldo Carvalho de Melo #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ 213f091f1d6SIngo Molnar #define X86_FEATURE_SEV ( 7*32+20) /* AMD Secure Encrypted Virtualization */ 2144053717aSArnaldo Carvalho de Melo #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ 2154caea057SArnaldo Carvalho de Melo #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */ 216a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */ 217a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */ 218a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ 219a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ 220a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ 221a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ 222e24f14b0SDavid Woodhouse #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ 2236e30437bSIngo Molnar 2247d7d1bf1SArnaldo Carvalho de Melo /* Virtualization flags: Linux defined, word 8 */ 2257d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ 2267d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ 2277d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ 2287d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ 2297d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ 2307d7d1bf1SArnaldo Carvalho de Melo 2310b44cfb8SIngo Molnar #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ 2327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ 2337d7d1bf1SArnaldo Carvalho de Melo 2347d7d1bf1SArnaldo Carvalho de Melo 2350b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ 2360b44cfb8SIngo Molnar #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ 2370b44cfb8SIngo Molnar #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ 2387d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ 2397d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ 2407d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ 2417d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ 2427d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ 2430b44cfb8SIngo Molnar #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ 2447d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ 2457d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ 2467d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ 2477d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ 248c0621acfSIngo Molnar #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ 2497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ 2507d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ 2510b44cfb8SIngo Molnar #define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ 2520b44cfb8SIngo Molnar #define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ 2537d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ 254c0621acfSIngo Molnar #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ 2557d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ 2567d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ 2574053717aSArnaldo Carvalho de Melo #define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */ 2587d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ 2597d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ 2607d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ 2617d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ 2627d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ 2637d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ 2647d7d1bf1SArnaldo Carvalho de Melo 2650b44cfb8SIngo Molnar /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ 2660b44cfb8SIngo Molnar #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ 2670b44cfb8SIngo Molnar #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ 2680b44cfb8SIngo Molnar #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ 2690b44cfb8SIngo Molnar #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ 2707d7d1bf1SArnaldo Carvalho de Melo 2710b44cfb8SIngo Molnar /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ 2727d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ 2737d7d1bf1SArnaldo Carvalho de Melo 2740b44cfb8SIngo Molnar /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ 2750b44cfb8SIngo Molnar #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ 2767d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ 2777d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ 2787d7d1bf1SArnaldo Carvalho de Melo 2790b44cfb8SIngo Molnar /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ 2807d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ 2817d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ 282643e345cSIngo Molnar #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ 283a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ 284a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ 285a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ 28632fdbd90SIngo Molnar #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ 287a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ 28832fdbd90SIngo Molnar #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ 2897d7d1bf1SArnaldo Carvalho de Melo 2900b44cfb8SIngo Molnar /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ 2917d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ 2927d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ 2937d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ 2947d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ 2957d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ 2967d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ 2977d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ 2987d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ 2997d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ 3007d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ 3017d7d1bf1SArnaldo Carvalho de Melo 3020b44cfb8SIngo Molnar /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ 3037d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ 3047d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ 3057d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ 3067d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ 3077d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ 3087d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ 3097d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ 3107d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ 3117d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ 3127d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ 3137d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ 314a2105f8aSArnaldo Carvalho de Melo #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ 315549a3976SIngo Molnar #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ 3167d7d1bf1SArnaldo Carvalho de Melo 3170b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ 318c0621acfSIngo Molnar #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ 3190b44cfb8SIngo Molnar #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ 3207d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ 3217d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ 3220b44cfb8SIngo Molnar #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ 3230b44cfb8SIngo Molnar #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ 3240b44cfb8SIngo Molnar #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ 3250b44cfb8SIngo Molnar #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ 3260b44cfb8SIngo Molnar #define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ 3270b44cfb8SIngo Molnar #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ 3285e2a146bSArnaldo Carvalho de Melo #define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */ 32906b35d93SPiotr Luc #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ 330f2ba3ee0SArnaldo Carvalho de Melo #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ 331c0621acfSIngo Molnar #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ 332605e71cdSArnaldo Carvalho de Melo #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */ 3337d7d1bf1SArnaldo Carvalho de Melo 3340b44cfb8SIngo Molnar /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ 3357d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ 3367d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ 3377d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ 3387d7d1bf1SArnaldo Carvalho de Melo 3394053717aSArnaldo Carvalho de Melo /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ 3404053717aSArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ 3414053717aSArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ 3425e2a146bSArnaldo Carvalho de Melo #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ 3434053717aSArnaldo Carvalho de Melo #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ 3444053717aSArnaldo Carvalho de Melo #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ 345e24f14b0SDavid Woodhouse #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ 3464053717aSArnaldo Carvalho de Melo #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ 347a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ 3484053717aSArnaldo Carvalho de Melo 3497d7d1bf1SArnaldo Carvalho de Melo /* 3507d7d1bf1SArnaldo Carvalho de Melo * BUG word(s) 3517d7d1bf1SArnaldo Carvalho de Melo */ 3527d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG(x) (NCAPINTS*32 + (x)) 3537d7d1bf1SArnaldo Carvalho de Melo 3547d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ 3557d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ 3567d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ 3577d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ 3587d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ 3597d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ 3607d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ 3617d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ 3627d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ 3637d7d1bf1SArnaldo Carvalho de Melo #ifdef CONFIG_X86_32 3647d7d1bf1SArnaldo Carvalho de Melo /* 3657d7d1bf1SArnaldo Carvalho de Melo * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional 3667d7d1bf1SArnaldo Carvalho de Melo * to avoid confusion. 3677d7d1bf1SArnaldo Carvalho de Melo */ 3687d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ 3697d7d1bf1SArnaldo Carvalho de Melo #endif 370bebfb730SArnaldo Carvalho de Melo #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ 371bebfb730SArnaldo Carvalho de Melo #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ 372bebfb730SArnaldo Carvalho de Melo #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ 373c0621acfSIngo Molnar #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ 3745d64db29SArnaldo Carvalho de Melo #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ 3754053717aSArnaldo Carvalho de Melo #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ 3764053717aSArnaldo Carvalho de Melo #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ 377a20d23bbSArnaldo Carvalho de Melo #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ 378e24f14b0SDavid Woodhouse #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ 3790b44cfb8SIngo Molnar 3807d7d1bf1SArnaldo Carvalho de Melo #endif /* _ASM_X86_CPUFEATURES_H */ 381